| Age | Commit message (Expand) | Author | Files | Lines |
|---|---|---|---|---|
| 2015-06-19 | clk: keystone: add support for post divider register for main pll | Murali Karicheri | 1 | -4/+4 |
| 2013-12-10 | clk: keystone: use clkod register bits for postdiv | Murali Karicheri | 1 | -4/+4 |
| 2013-10-08 | clk: keystone: add Keystone PLL clock driver | Santosh Shilimkar | 1 | -0/+84 |
