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2025-12-30drm/i915/vrr: Pause DC Balancing for DSB commitsVille Syrjälä2-0/+22
Pause the DMC DC Balancing for the remainder of the commit so that vmin/vmax won't change after we've baked them into the DSB vblank evasion commands. --v2: - Remove typo. (Ankit) - Separate vrr enable structuring. (Ankit) --v3: - Add gaurd before accessing DC balance bits. - Remove redundancy checks. --v4: - Move events to separate function. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com> Reviewed-by: Uma Shankar <uma.shankar@intel.com> Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com> Link: https://patch.msgid.link/20251223104542.2688548-17-mitulkumar.ajitkumar.golani@intel.com
2025-12-30drm/i915/dsb: Add pipedmc dc balance enable/disableVille Syrjälä2-0/+20
Add function to control DC balance enable/disable bit via DSB. --v2: Remove redundant forward declaration. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com> Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com> Link: https://patch.msgid.link/20251223104542.2688548-16-mitulkumar.ajitkumar.golani@intel.com
2025-12-30drm/i915/display: Wait for VRR PUSH status updateMitul Golani1-2/+13
After VRR Push is sent, need to wait till flipline decision boundary to get Push bit to get cleared. --v2: - Adjust delays to vrr vmin vblank delays. (Ankit) --v3: - Change intel_vrr_vmin_safe_window_end() so that intel_dsb_wait_for_delayed_vblank() uses correct delay. (Ankit) --v4: - Simplify intel_vrr_vmin_safe_window_end implementation. (Ankit) Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com> Reviewed-by: Uma Shankar <uma.shankar@intel.com> Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com> Link: https://patch.msgid.link/20251223104542.2688548-15-mitulkumar.ajitkumar.golani@intel.com
2025-12-30drm/i915/vrr: Implement vblank evasion with DC balancingVille Syrjälä2-4/+53
Add vblank evasion logic when vrr is already enabled along with dc balance is computed. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com> Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com> Link: https://patch.msgid.link/20251223104542.2688548-14-mitulkumar.ajitkumar.golani@intel.com
2025-12-30drm/i915/vblank: Extract vrr_vblank_start()Ville Syrjälä1-4/+9
Initialise delayed vblank position for evasion logic. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com> Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com> Link: https://patch.msgid.link/20251223104542.2688548-13-mitulkumar.ajitkumar.golani@intel.com
2025-12-30drm/i915/vrr: Write DC balance params to hw registersMitul Golani1-0/+76
Write DC Balance parameters to hw registers. --v2: - Update commit header. - Separate crtc_state params from this patch. (Ankit) --v3: - Write registers at compute config. - Update condition for write. --v4: - Address issue with state checker. --v5: - Initialise some more dc balance register while enabling VRR. --v6: - FLIPLINE_CFG need to be configure at last, as it is double buffer arming point. --v7: - Initialise and reset live value of vmax and vmin as well. --v8: - Add separate functions while writing hw registers. (Ankit) --v9: - Add DC Balance counter enable bit to this patch. (Ankit) --v10: - Add rigister writes to vrr_enable/disable. (Ankit) Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com> Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com> Link: https://patch.msgid.link/20251223104542.2688548-12-mitulkumar.ajitkumar.golani@intel.com
2025-12-30drm/i915/display: Add DC Balance flip count operationsMitul Golani4-0/+24
Track dc balance flip count with params per crtc. Increment DC Balance Flip count before every flip to indicate DMC firmware about new flip occurrence which needs to be adjusted for dc balancing. This is tracked separately from legacy FLIP_COUNT register also Reset DC balance flip count value while disabling VRR adaptive mode, this is to start with fresh counts when VRR adaptive refresh mode is triggered again. --v2: - Call during intel_update_crtc.(Ankit) Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com> Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com> Link: https://patch.msgid.link/20251223104542.2688548-11-mitulkumar.ajitkumar.golani@intel.com
2025-12-30drm/i915/vrr: Add function to reset DC balance accumulated paramsMitul Golani3-0/+17
Add function which resets all accumulated DC Balance parameters whenever adaptive mode of VRR goes off. This helps to give a fresh start when VRR is re-enabled. --v2: - Typo, change crtc_state to old_crtc_state. (Ankit) Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com> Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com> Link: https://patch.msgid.link/20251223104542.2688548-10-mitulkumar.ajitkumar.golani@intel.com
2025-12-30drm/i915/vrr: Add function to check if DC Balance PossibleMitul Golani1-2/+17
Add a function that checks if DC Balance enabling is possible on the requested PIPE. Apart from the DISPLAY_VER check, account for current firmware limitations, which only allow DC Balance on PIPE A and PIPE B. v2: Rephrased commit message. (Ankit) Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com> Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com> Link: https://patch.msgid.link/20251223104542.2688548-9-mitulkumar.ajitkumar.golani@intel.com
2025-12-30drm/i915/vrr: Add compute config for DC Balance paramsMitul Golani1-0/+45
Compute DC Balance parameters and tunable params based on experiments. --v2: - Document tunable params. (Ankit) --v3: - Add line spaces to compute config. (Ankit) - Remove redundancy checks. --v4: - Separate out conpute config to separate function. - As all the valuse are being computed in scanlines, and slope is still in usec, convert and store it to scanlines. --v5: - Update and add comments for slope calculation. (Ankit) - Update early return conditions for dc balance compute. (Ankit) --v6: - Early return condition simplified for dc balance compute config. (Ankit) - Make use of pipe restrictions to this patch. (Ankit) --v7: - Separate out PIPE_A and PIPE_B restrictions to other patch.(Ankit) Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com> Reviewed-by: Uma Shankar <uma.shankar@intel.com> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com> Link: https://patch.msgid.link/20251223104542.2688548-8-mitulkumar.ajitkumar.golani@intel.com
2025-12-30drm/i915/vrr: Add state dump for DC Balance paramsMitul Golani1-0/+8
Add state dump for dc balance params to track DC Balance crtc state config. -v1: -- nitpick: s/Vblank target/vblank target. (Ankit) Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com> Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com> Link: https://patch.msgid.link/20251223104542.2688548-7-mitulkumar.ajitkumar.golani@intel.com
2025-12-30drm/i915/vrr: Add DC Balance params to crtc_stateMitul Golani3-0/+46
Add DC Balance params to crtc_state, also add state checker params for related properties. --v3: - Seggregate crtc_state params with this patch. (Ankit) --v4: - Update commit message and header. (Ankit) - Add +1 to VMIN and VMAX only when it is non-zero. (Ankit) --v5: - Add headers in sorted order. (Jani Nikula) --v6: - Add a separate function to get and check dc_balance params. - Avoid repeatative use of MMIO read. (Ankit) Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com> Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com> Link: https://patch.msgid.link/20251223104542.2688548-6-mitulkumar.ajitkumar.golani@intel.com
2025-12-30drm/i915/vrr: Add functions to read out vmin/vmax stuffVille Syrjälä2-0/+61
Calculate delayed vblank start position with the help of added vmin/vmax stuff for next frame and final computation. --v2: - Correct Author details. --v3: - Separate register details from this patch. --v4: - Add mask macros. --v5: - As live prefix params indicate timings for current frame, read just _live prefix values instead of next frame timings as done previously. - Squash Refactor vrr params patch. --v6: - Use error code while returning invalid values. (Jani, Nikula) Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com> Reviewed-by: Uma Shankar <uma.shankar@intel.com> Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com> Link: https://patch.msgid.link/20251223104542.2688548-5-mitulkumar.ajitkumar.golani@intel.com
2025-12-30drm/i915/vrr: Add VRR DC balance registersMitul Golani1-0/+68
Add VRR register offsets and bits to access DC Balance configuration. --v2: - Separate register definitions. (Ankit) - Remove usage of dev_priv. (Jani, Nikula) --v3: - Convert register address offset, from capital to small. (Ankit) - Move mask bits near to register offsets. (Ankit) --v4: - Use _MMIO_TRANS wherever possible. (Jani) --v5: - Added LIVE Value registers for VMAX and FLIPLINE as provided by DMC fw - For pipe B it is temporary and expected to change later once finalised. --v6: - Add live value registers for DCB VMAX/FLIPLINE. --v7: - Correct commit message file. (Jani Nikula) - Add bits in highest to lowest order. (Jani Nikula) --v8: - Register/bitfields indentation changes as per i915_reg.h mentioned format (Jani, Ankit) --v9: - Remove comment. (Ankit) Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com> Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com> Link: https://patch.msgid.link/20251223104542.2688548-4-mitulkumar.ajitkumar.golani@intel.com
2025-12-30drm/i915/dmc: Add pipe dmc registers and bits for DC BalanceVille Syrjälä1-0/+60
Add pipe dmc registers and access bits for DC Balance params configuration and enablement. --v2: - Separate register definitions for transcoder and pipe dmc. (Ankit) - Use MMIO pipe macros instead of transcoder ones. (Ankit) - Remove dev_priv use. (Jani, Nikula) --v3: - Add all register address, from capital alphabet to small. (Ankit) - Add EVT CTL registers. - Add co-author tag. - Add event flag for Triggering DC Balance. --v4: - Add DCB Flip count and balance reset registers. --v5: - Correct macro usage for flip count. (Ankit) - Use register offset in lower case. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com> Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com> Link: https://patch.msgid.link/20251223104542.2688548-3-mitulkumar.ajitkumar.golani@intel.com
2025-12-30drm/i915/display: Add source param for dc balanceMitul Golani1-0/+1
Add source param for dc balance enablement. --v2: - Arrange in alphabetic order. (Ankit) - Update name. (Ankit) --v3: - Commit message update. (Ankit) Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com> Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com> Link: https://patch.msgid.link/20251223104542.2688548-2-mitulkumar.ajitkumar.golani@intel.com
2025-12-29drm/i915/gvt/display_helper: Get rid of #ifdef/#undefsAnkit Nautiyal4-15/+0
Now that i915/display macros have been substituted with wrappers that call the new display-device helpers, we can drop the conflicting includes from GVT and remove the temporary #ifdef/#undef macro overrides. Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com> Reviewed-by: Jani Nikula <jani.nikula@intel.com> Link: https://patch.msgid.link/20251219060302.2365123-7-ankit.k.nautiyal@intel.com
2025-12-29drm/i915/gvt: Use the appropriate header for the DPLL macroAnkit Nautiyal1-1/+1
The macro `DPLL_ID_SKL_DPLL0` is defined in display/intel_dpll_mgr.h. Previously, GVT included the header display/intel_display_core.h` because other macros also depended on it. After porting those macros to use the new APIs, the only remaining dependency was for the DPLL macro. Replace the indirect include with the correct header and drop intel_display_core.h to reduce unnecessary dependencies. Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com> Reviewed-by: Jani Nikula <jani.nikula@intel.com> Link: https://patch.msgid.link/20251219060302.2365123-6-ankit.k.nautiyal@intel.com
2025-12-29drm/i915/gvt: Change for_each_pipe to use pipe_valid APIAnkit Nautiyal4-5/+19
Add a new API to check if a given pipe is valid using DISPLAY_RUNTIME_INFO() for GVT. Update GVT to use this API instead of accessing `DISPLAY_RUNTIME_INFO->pipe_mask` directly in the `for_each_pipe` macro. Since `for_each_pipe` is defined in i915/display/intel_display.h, which also contains other macros used by gvt/display.c, we cannot drop the intel_display.h header yet. This causes a build error because `for_each_pipe` is included from both i915/display/intel_display.h and gvt/display_helpers.h. To resolve this, rename the GVT macro to `gvt_for_each_pipe` and make it call the new API. This avoids exposing display internals and prepares for display modularization. v2: - Expose API to check if pipe is valid rather than the runtime info pipe mask. (Jani) - Rename the macro to `gvt_for_each_pipe` to resolve build error. v3: - Use EXPORT_SYMBOL_NS_GPL(..., "I915_GVT"); (Jani) - Use enum pipe at call sites instead of casting in the macro. (Jani) Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com> Reviewed-by: Jani Nikula <jani.nikula@intel.com> Link: https://patch.msgid.link/20251219060302.2365123-5-ankit.k.nautiyal@intel.com
2025-12-29drm/i915/gvt: Add header to use display offset functions in macrosAnkit Nautiyal5-0/+49
Introduce gvt/display_helpers.h to make DISPLAY_MMIO_BASE and INTEL_DISPLAY_DEVICE_*_OFFSET macros call exported display functions. This lets GVT keep using existing register macros (e.g., TRANSCONF(display, pipe)) while ensuring offset calculations happen through functions instead of accessing display internals. Ideally, we would remove the display headers that define these macros, but some macros in GVT still depend on them and have not yet been ported. Keeping those headers leads to build conflicts, so as a stopgap, we use temporary ifdef/undef blocks to override the macros with API-backed versions. These will be removed once all dependent macros are ported and the conflicting headers can be safely dropped. Note: TRANSCONF() expects a pipe index but some GVT callers pass a transcoder, causing -Werror=enum-conversion. Fix: cast to enum pipe in the GVT-side macro override. This works for all cases as TRANSCODER_{A,B,C,D} all have 1:1 mapping to PIPE_{A,B,C,D} except for TRANSCODER_EDP which is used in one place. In any case, the cast preserves the previous behaviour. v2: - Remove prefix `gvt/` while including the header file. (Jani) - Explain the rationale behind temporary ifdef/undefs and plan to drop them. (Jani). v3: - Meld the patch to cast argument to enum pipe for the pipe-offset macro. (Jani) - Add a FIXME to highlight the cast. (Jani) Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com> Reviewed-by: Jani Nikula <jani.nikula@intel.com> Link: https://patch.msgid.link/20251219060302.2365123-4-ankit.k.nautiyal@intel.com
2025-12-29drm/i915/display: Add APIs to be used by gvt to get the register offsetsAnkit Nautiyal4-0/+57
GVT code uses macros for register offsets that require display internal structures. This makes clean separation of display code and modularization difficult. Introduce APIs to abstract offset calculations: - intel_display_device_pipe_offset() - intel_display_device_trans_offset() - intel_display_device_cursor_offset() - intel_display_device_mmio_base() These APIs return absolute base offsets for the respective register groups, allowing GVT to compute MMIO addresses without using internal macros or struct fields. This prepares the path to separate display-dependent code from i915/gvt/*. v2: - Build GVT APIs only when GVT is actually enabled. (Jani) Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com> Reviewed-by: Jani Nikula <jani.nikula@intel.com> (#v1) Link: https://patch.msgid.link/20251219060302.2365123-3-ankit.k.nautiyal@intel.com
2025-12-29drm/i915/display: Abstract pipe/trans/cursor offset calculationAnkit Nautiyal2-11/+21
Introduce INTEL_DISPLAY_DEVICE_*_OFFSET() macros to compute absolute MMIO offsets for pipe, transcoder, and cursor registers. Update _MMIO_PIPE2/_MMIO_TRANS2/_MMIO_CURSOR2 to use these macros for cleaner abstraction and to prepare for external API usage (e.g. GVT). Also move DISPLAY_MMIO_BASE() to intel_display_device.h so it can be abstracted in GVT, allowing register macros to resolve via exported helpers rather than peeking into struct intel_display. v2: Wrap the macro argument usages in parenthesis. (Jani) Suggested-by: Jani Nikula <jani.nikula@intel.com> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com> Reviewed-by: Jani Nikula <jani.nikula@intel.com> Link: https://patch.msgid.link/20251219060302.2365123-2-ankit.k.nautiyal@intel.com
2025-12-29drm/i915/display: use to_intel_uncore() to avoid i915_drv.hJani Nikula6-55/+48
A number of places that include i915_drv.h only need it to get from display to i915 to uncore. We have to_intel_uncore() for that, use it to avoid the i915_drv.h include. v2: Rebase Cc: Ville Syrjala <ville.syrjala@linux.intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Michał Grzelak <michal.grzelak@intel.com> Link: https://patch.msgid.link/44a5d526a097ab9276e60162263fa8cd23325ce7.1766406794.git.jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2025-12-29drm/xe/compat: convert uncore macro to static inlinesJani Nikula2-2/+6
Use static inline instead of macro for intel_uncore_arm_unclaimed_mmio_detection() to avoid the need for __maybe_unused annotations. v2: Rebase, intel_uncore_arm_unclaimed_mmio_detection() Cc: Ville Syrjala <ville.syrjala@linux.intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> # v1 Reviewed-by: Michał Grzelak <michal.grzelak@intel.com> Link: https://patch.msgid.link/7ddee71952315e70e4a7df23638100b664e293bd.1766406794.git.jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2025-12-29drm/xe/compat: remove unused forcewake get/put macrosJani Nikula1-5/+0
Since commit 35ec71285c93 ("drm/i915/pc8: Add parent interface for PC8 forcewake tricks"), the compat intel_uncore_forcewake_{get,put} and FORCEWAKE_ALL macros have become unused. Remove them. Reviewed-by: Michał Grzelak <michal.grzelak@intel.com> Link: https://patch.msgid.link/5081b00a6fa20bdbcc1c973c6920cd590e1dc98f.1766406794.git.jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2025-12-29drm/i915: remove unused dev_priv local variableJani Nikula1-2/+1
Since commit 35ec71285c93 ("drm/i915/pc8: Add parent interface for PC8 forcewake tricks"), the __maybe_unused dev_priv has become definitely unused. Remove, along with the i915_drv.h include. Reviewed-by: Michał Grzelak <michal.grzelak@intel.com> Link: https://patch.msgid.link/222871a73efbe1049862d11a03abf253611e46b1.1766406794.git.jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2025-12-29drm/i915/vdsc: Account for DSC slice overhead in intel_vdsc_min_cdclk()Ankit Nautiyal1-4/+31
When DSC is enabled on a pipe, the pipe pixel rate input to the CDCLK frequency and pipe joining calculation needs an adjustment to account for compression overhead "bubbles" added at each horizontal slice boundary. Account for this overhead while computing min cdclk required for DSC. v2: - Get rid of the scaling factor and return unchanged pixel-rate instead of 0. v3: - Use mul_u32_u32() for the bubble-adjusted pixel rate to avoid 64x64 multiplication and drop redundant casts in DIV_ROUND_UP_ULL(). (Imre) Bspec:68912 Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com> Reviewed-by: Imre Deak <imre.deak@intel.com> Link: https://patch.msgid.link/20251223150826.2591182-1-ankit.k.nautiyal@intel.com
2025-12-24drm/i915/cx0: Use the consolidated HDMI tablesSuraj Kandpal1-5/+8
Use the consolidated HDMI tables before we try to compute them via algorithm. The reason is that these are the ideal values and even though the values calculated via the HDMI algorithm are correct but not always ideal. This is done for C20 and already exists for C10. Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com> Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com> Link: https://patch.msgid.link/20251223063422.1444968-1-suraj.kandpal@intel.com
2025-12-22drm/xe/display: drop i915_utils.hJani Nikula3-11/+0
With the i915 switch to generic fault injection, display no longer needs the compat i915_utils.h. Remove it, along with a few includes. Reviewed-by: Michał Grzelak <michal.grzelak@intel.com> Link: https://patch.msgid.link/20251219104036.855258-1-jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2025-12-22drm/i915: drop dependency on struct intel_display from i915 initial planeJani Nikula1-26/+17
The i915 core initial plane handling doesn't actually need struct intel_display for anything. Switch to i915 specific data structures in i915 core code. Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patch.msgid.link/58d7605a16b360080921ff2af7120b6da2eb042d.1765812266.git.jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2025-12-22drm/{i915, xe}: pass struct drm_device instead of drm_device to ->alloc_objJani Nikula4-13/+8
The initial plane parent interface ->alloc_obj hook no longer needs the crtc for anything. Pass struct drm_device instead. Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patch.msgid.link/7a40381be6d98dc0916a5447be5dd6cba86cfd0a.1765812266.git.jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2025-12-22drm/{i915, xe}: pass struct drm_plane_state instead of struct drm_crtc to ↵Jani Nikula4-15/+8
->setup The initial plane parent interface ->setup hook no longer needs the crtc for anything. Pass the struct drm_plane_state instead. Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patch.msgid.link/c3db101ef5fd13c56cb3a9329adecf521a807abc.1765812266.git.jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2025-12-22drm/{i915,xe}: deduplicate initial plane setupJani Nikula3-50/+26
Deduplicate more of the identical parts of i915 and xe initial plane setup. This lets us reduce the core dependency on display internals. Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patch.msgid.link/1a2abbceedb9e7d03f262c44cd54a24556ef6b61.1765812266.git.jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2025-12-22drm/{i915, xe}: deduplicate intel_alloc_initial_plane_obj() FB modifier checksJani Nikula3-26/+14
Move the modifier checks into common code to deduplicate. Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patch.msgid.link/3c62ad48595aa2306219b1d6a215cf7680a67da2.1765812266.git.jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2025-12-22drm/i915: further deduplicate intel_find_initial_plane_obj()Jani Nikula4-111/+88
Move intel_reuse_initial_plane_obj() into common display code, and split the ->find_obj hook into ->alloc_obj and ->setup hooks. Return the struct drm_gem_object from ->alloc_obj in preparation for moving more things to display. Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patch.msgid.link/c71011dbb11afaa5c4da30aa2627833374300d63.1765812266.git.jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2025-12-22drm/xe: return plane_state from intel_reuse_initial_plane_obj()Jani Nikula1-11/+15
Initialize fb in the same level as the other code path. Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patch.msgid.link/47d3272cff13dc8f5d7323c32bfb3cc34c0c977d.1765812266.git.jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2025-12-22drm/i915: return plane_state from intel_reuse_initial_plane_obj()Jani Nikula1-12/+14
Initialize fb and vma in the same level as the other code path. Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patch.msgid.link/96985a18593408f07fba131cf49ca0f97bf8fb93.1765812266.git.jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2025-12-22drm/{i915, xe}: start deduplicating intel_find_initial_plane_obj() between ↵Jani Nikula4-54/+38
i915 and xe Move some easy common parts to display. Initially, the intel_find_initial_plane_obj() error path seems silly, but it'll be more helpful this way for later changes. Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patch.msgid.link/950d308172443d5bae975aa1ab72111720134219.1765812266.git.jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2025-12-22drm/{i915, xe}: deduplicate plane_config_fini() between i915 and xeJani Nikula3-19/+10
Move the common code to display. Retain empty xe_plane_config_fini() for now, in case it's needed in the future. Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patch.msgid.link/14322386cdb1a0f4f6c7ff74a5a9696ea0ff84bf.1765812266.git.jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2025-12-22drm/{i915, xe}: deduplicate intel_initial_plane_config() between i915 and xeJani Nikula4-84/+62
Move the parent interface at one step lower level, allowing deduplication. Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patch.msgid.link/0cb4077a5a39274c7a2dae95d548d7b33365a518.1765812266.git.jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2025-12-22drm/{i915, xe}: move initial plane calls to parent interfaceJani Nikula10-8/+78
Add the initial plane handling functions to the display parent interface. Add the call wrappers in dedicated intel_initial_plane.c instead of intel_parent.c, as we'll be refactoring the calls heavily. Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patch.msgid.link/ab91c891677fe2bb83bf5aafa5ee984b2442b84d.1765812266.git.jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2025-12-22drm/i915: rename intel_plane_initial.h to intel_initial_plane.hJani Nikula5-14/+14
Follow the more naturally flowing naming. Rename both the header and the vblank wait function. Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patch.msgid.link/32c2d68a9ae7d2262ad2c63e873e522e67bc78df.1765812266.git.jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2025-12-22drm/xe/display: rename xe_plane_initial.c to xe_initial_plane.cJani Nikula2-1/+1
Follow i915 with the more naturally flowing naming. Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patch.msgid.link/62eb56fe348a8fe7c17333d784192da701367cc7.1765812266.git.jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2025-12-22drm/i915: move display/intel_plane_initial.c to i915_initial_plane.cJani Nikula2-9/+10
intel_plane_initial.c is i915 specific. Move it to i915 core. Start renaming stuff with the slightly more natural "initial plane" rather than "plane initial". Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patch.msgid.link/cdad733192690a61fbb44921c57fc68cc1cd809f.1765812266.git.jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2025-12-22drm/xe: Fix ggtt fb alignmentTvrtko Ursulin1-1/+1
Pass the correct alignment from intel_fb_pin_to_ggtt() down to __xe_pin_fb_vma(). Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@igalia.com> Reported-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Closes: https://lore.kernel.org/intel-xe/aNL_RgLy13fXJbYx@intel.com/ Cc: Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Fixes: b0228a337de8 ("drm/xe/display: align framebuffers according to hw requirements") Cc: <stable@vger.kernel.org> # v6.13+ Signed-off-by: Thomas Hellström <thomas.hellstrom@linux.intel.com> Link: https://patch.msgid.link/20251208181550.6618-1-tursulin@igalia.com
2025-12-19drm/i915/pc8: Add parent interface for PC8 forcewake tricksVille Syrjälä8-4/+76
We use forcewake to prevent the SoC from actually entering PC8 while performing the PC8 disable sequence. Hide that behind a new parent interface to eliminate the naked forcewake/uncore usage from the display power code. v2: Mark the interface optional and warn if someone calls it when not provided (Jani) Include the header to make sure the extern declaration matches the definition (Jani) v3: Rebase due to shuffling Reviewed-by: Jani Nikula <jani.nikula@intel.com> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patch.msgid.link/20251218182052.18756-1-ville.syrjala@linux.intel.com
2025-12-19drm/i915/cx0: Toggle powerdown states for C10 on HDMIGustavo Sousa1-0/+15
A new step has been added to Bspec with respect to the C10 PHY, which instructs the driver to toggle powerdown value for boths PHY lanes to P0 and then P2 when driving an HDMI connector. This update in the Bspec reflects the changes required by Wa_14026084006, so document it. Note that, unlike other display workarounds, this one is actually tied to the C10 PHY and not to a specific display IP. As such, let's just document it in intel_cx0_phy.c instead of adding it to intel_display_wa.c. Bspec: 64568, 74489 Reviewed-by: Dnyaneshwar Bhadane <dnyaneshwar.bhadane@intel.com> Link: https://patch.msgid.link/20251216-wa_14026084006-c10-hdmi-toggle-powerdown-v1-2-08677b03e2f1@intel.com Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
2025-12-19drm/i915/cx0: Use a more accurate message for powerdown change failureGustavo Sousa1-1/+1
We do not use the function intel_cx0_powerdown_change_sequence() exclusively to take the PHY out of reset, hence the warning message on failure is misleading. Furthermore, in an upcoming change, we will also use that function to implement a new C10 PHY workaround. Use a more accurate message by saying that we failed to change the powerdown state. Reviewed-by: Dnyaneshwar Bhadane <dnyaneshwar.bhadane@intel.com> Link: https://patch.msgid.link/20251216-wa_14026084006-c10-hdmi-toggle-powerdown-v1-1-08677b03e2f1@intel.com Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
2025-12-19drm/i915/dp: Fail state computation for invalid DSC source input BPP valuesImre Deak1-7/+21
There is no reason to accept an invalid minimum/maximum DSC source input BPP value (i.e a minimum DSC input BPP value above the maximum pipe BPP or a maximum DSC input BPP value below the minimum pipe BPP value), fail the state computation in these cases. Reviewed-by: Vinod Govindapillai <vinod.govindapillai@intel.com> Signed-off-by: Imre Deak <imre.deak@intel.com> Link: https://patch.msgid.link/20251215192357.172201-17-imre.deak@intel.com
2025-12-19drm/i915/dp: Fail state computation for invalid max sink compressed BPP valueImre Deak1-2/+1
There is no reason to accept an invalid maximum sink compressed BPP value (i.e. 0), fail the state computation in this case. Reviewed-by: Vinod Govindapillai <vinod.govindapillai@intel.com> Reviewed-by: Luca Coelho <luciano.coelho@intel.com> Signed-off-by: Imre Deak <imre.deak@intel.com> Link: https://patch.msgid.link/20251215192357.172201-16-imre.deak@intel.com
generated by cgit v1.2.3 (git 2.39.0) at 2026-04-29 08:01:35 +0300