diff options
Diffstat (limited to 'include/dt-bindings')
99 files changed, 7409 insertions, 250 deletions
diff --git a/include/dt-bindings/arm/qcom,ids.h b/include/dt-bindings/arm/qcom,ids.h index e850dc3a1ad3..cb8ce53146f0 100644 --- a/include/dt-bindings/arm/qcom,ids.h +++ b/include/dt-bindings/arm/qcom,ids.h @@ -277,13 +277,20 @@ #define QCOM_ID_IPQ5302 595 #define QCOM_ID_QCS8550 603 #define QCOM_ID_QCM8550 604 +#define QCOM_ID_SM8750 618 #define QCOM_ID_IPQ5300 624 +#define QCOM_ID_SM7635 636 +#define QCOM_ID_SM6650 640 +#define QCOM_ID_SM6650P 641 #define QCOM_ID_IPQ5321 650 #define QCOM_ID_IPQ5424 651 +#define QCOM_ID_QCM6690 657 +#define QCOM_ID_QCS6690 658 #define QCOM_ID_IPQ5404 671 #define QCOM_ID_QCS9100 667 #define QCOM_ID_QCS8300 674 #define QCOM_ID_QCS8275 675 +#define QCOM_ID_QCS9075 676 #define QCOM_ID_QCS615 680 /* diff --git a/include/dt-bindings/clock/ast2600-clock.h b/include/dt-bindings/clock/ast2600-clock.h index 7ae96c7bd72f..f60fff261130 100644 --- a/include/dt-bindings/clock/ast2600-clock.h +++ b/include/dt-bindings/clock/ast2600-clock.h @@ -122,6 +122,8 @@ #define ASPEED_RESET_PCIE_DEV_OEN 20 #define ASPEED_RESET_PCIE_RC_O 19 #define ASPEED_RESET_PCIE_RC_OEN 18 +#define ASPEED_RESET_MAC2 12 +#define ASPEED_RESET_MAC1 11 #define ASPEED_RESET_PCI_DP 5 #define ASPEED_RESET_HACE 4 #define ASPEED_RESET_AHB 1 diff --git a/include/dt-bindings/clock/cix,sky1.h b/include/dt-bindings/clock/cix,sky1.h new file mode 100644 index 000000000000..9245ebd1e80a --- /dev/null +++ b/include/dt-bindings/clock/cix,sky1.h @@ -0,0 +1,279 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright 2024-2025 Cix Technology Group Co., Ltd. + */ + +#ifndef _DT_BINDINGS_CLK_CIX_SKY1_H +#define _DT_BINDINGS_CLK_CIX_SKY1_H + +#define CLK_TREE_CPU_GICxCLK 0 +#define CLK_TREE_CPU_PPUCLK 1 +#define CLK_TREE_CPU_PERIPHCLK 2 +#define CLK_TREE_DSU_CLK 3 +#define CLK_TREE_DSU_PCLK 4 +#define CLK_TREE_CPU_CLK_BC0 5 +#define CLK_TREE_CPU_CLK_BC1 6 +#define CLK_TREE_CPU_CLK_BC2 7 +#define CLK_TREE_CPU_CLK_BC3 8 +#define CLK_TREE_CPU_CLK_MC0 9 +#define CLK_TREE_CPU_CLK_MC1 10 +#define CLK_TREE_CPU_CLK_MC2 11 +#define CLK_TREE_CPU_CLK_MC3 12 +#define CLK_TREE_CPU_CLK_LC0 13 +#define CLK_TREE_CPU_CLK_LC1 14 +#define CLK_TREE_CPU_CLK_LC2 15 +#define CLK_TREE_CPU_CLK_LC3 16 +#define CLK_TREE_CSI_CTRL0_PCLK 17 +#define CLK_TREE_CSI_CTRL1_PCLK 18 +#define CLK_TREE_CSI_CTRL2_PCLK 19 +#define CLK_TREE_CSI_CTRL3_PCLK 20 +#define CLK_TREE_CSI_DMA0_PCLK 21 +#define CLK_TREE_CSI_DMA1_PCLK 22 +#define CLK_TREE_CSI_DMA2_PCLK 23 +#define CLK_TREE_CSI_DMA3_PCLK 24 +#define CLK_TREE_CSI_PHY0_PSM 25 +#define CLK_TREE_CSI_PHY1_PSM 26 +#define CLK_TREE_CSI_PHY0_APBCLK 27 +#define CLK_TREE_CSI_PHY1_APBCLK 28 +#define CLK_TREE_FCH_APB_CLK 29 +#define CLK_TREE_GPU_CLK_400M 30 +#define CLK_TREE_GPU_CLK_CORE 31 +#define CLK_TREE_GPU_CLK_STACKS 32 +#define CLK_TREE_DP0_PIXEL0 33 +#define CLK_TREE_DP0_PIXEL1 34 +#define CLK_TREE_DP1_PIXEL0 35 +#define CLK_TREE_DP1_PIXEL1 36 +#define CLK_TREE_DP2_PIXEL0 37 +#define CLK_TREE_DP2_PIXEL1 38 +#define CLK_TREE_DP3_PIXEL0 39 +#define CLK_TREE_DP3_PIXEL1 40 +#define CLK_TREE_DP4_PIXEL0 41 +#define CLK_TREE_DP4_PIXEL1 42 +#define CLK_TREE_DPU_CLK 43 +#define CLK_TREE_DPU0_ACLK 44 +#define CLK_TREE_DPU1_ACLK 45 +#define CLK_TREE_DPU2_ACLK 46 +#define CLK_TREE_DPU3_ACLK 47 +#define CLK_TREE_DPU4_ACLK 48 +#define CLK_TREE_DPC0_VIDCLK0 49 +#define CLK_TREE_DPC0_VIDCLK1 50 +#define CLK_TREE_DPC1_VIDCLK0 51 +#define CLK_TREE_DPC1_VIDCLK1 52 +#define CLK_TREE_DPC2_VIDCLK0 53 +#define CLK_TREE_DPC2_VIDCLK1 54 +#define CLK_TREE_DPC3_VIDCLK0 55 +#define CLK_TREE_DPC3_VIDCLK1 56 +#define CLK_TREE_DPC4_VIDCLK0 57 +#define CLK_TREE_DPC4_VIDCLK1 58 +#define CLK_TREE_DPC0_APBCLK 59 +#define CLK_TREE_DPC1_APBCLK 60 +#define CLK_TREE_DPC2_APBCLK 61 +#define CLK_TREE_DPC3_APBCLK 62 +#define CLK_TREE_DPC4_APBCLK 63 +#define CLK_TREE_NPU_MEMCLK 64 +#define CLK_TREE_NPU_SYSCLK 65 +#define CLK_TREE_NPU_DBGCLK 66 +#define CLK_TREE_VPU_APBCLK 67 +#define CLK_TREE_ISP_ACLK 68 +#define CLK_TREE_ISP_SCLK 69 +#define CLK_TREE_AUDIO_CLK4 70 +#define CLK_TREE_AUDIO_CLK5 71 +#define CLK_TREE_CAMERA_MCLK0 72 +#define CLK_TREE_CAMERA_MCLK1 73 +#define CLK_TREE_CAMERA_MCLK2 74 +#define CLK_TREE_CAMERA_MCLK3 75 +#define CLK_TREE_AUDIO_CLK0 76 +#define CLK_TREE_AUDIO_CLK1 77 +#define CLK_TREE_AUDIO_CLK2 78 +#define CLK_TREE_AUDIO_CLK3 79 +#define CLK_TREE_MM_NI700_CLK 80 +#define CLK_TREE_SYS_NI700_CLK 81 +#define CLK_TREE_GMAC0_ACLK 82 +#define CLK_TREE_GMAC1_ACLK 83 +#define CLK_TREE_GMAC0_DIV_ACLK 84 +#define CLK_TREE_GMAC0_DIV_TXCLK 85 +#define CLK_TREE_GMAC0_RGMII0_TXCLK 86 +#define CLK_TREE_GMAC1_DIV_ACLK 87 +#define CLK_TREE_GMAC1_DIV_TXCLK 88 +#define CLK_TREE_GMAC1_RGMII0_TXCLK 89 +#define CLK_TREE_GMAC0_PCLK 90 +#define CLK_TREE_GMAC1_PCLK 91 +#define CLK_TREE_USB2_0_AXI_GATE 92 +#define CLK_TREE_USB2_0_APB_GATE 93 +#define CLK_TREE_USB2_1_AXI_GATE 94 +#define CLK_TREE_USB2_1_APB_GATE 95 +#define CLK_TREE_USB2_2_AXI_GATE 96 +#define CLK_TREE_USB2_2_APB_GATE 97 +#define CLK_TREE_USB2_3_AXI_GATE 98 +#define CLK_TREE_USB2_3_APB_GATE 99 +#define CLK_TREE_USB2_0_PHY_GATE 100 +#define CLK_TREE_USB2_1_PHY_GATE 101 +#define CLK_TREE_USB2_2_PHY_GATE 102 +#define CLK_TREE_USB2_3_PHY_GATE 103 +#define CLK_TREE_USB3C_DRD_AXI_GATE 104 +#define CLK_TREE_USB3C_DRD_APB_GATE 105 +#define CLK_TREE_USB3C_DRD_PHY2_GATE 106 +#define CLK_TREE_USB3C_DRD_PHY3_GATE 107 +#define CLK_TREE_USB3C_0_AXI_GATE 108 +#define CLK_TREE_USB3C_0_APB_GATE 109 +#define CLK_TREE_USB3C_0_PHY2_GATE 110 +#define CLK_TREE_USB3C_0_PHY3_GATE 111 +#define CLK_TREE_USB3C_1_AXI_GATE 112 +#define CLK_TREE_USB3C_1_APB_GATE 113 +#define CLK_TREE_USB3C_1_PHY2_GATE 114 +#define CLK_TREE_USB3C_1_PHY3_GATE 115 +#define CLK_TREE_USB3C_2_AXI_GATE 116 +#define CLK_TREE_USB3C_2_APB_GATE 117 +#define CLK_TREE_USB3C_2_PHY2_GATE 118 +#define CLK_TREE_USB3C_2_PHY3_GATE 119 +#define CLK_TREE_USB3A_0_AXI_GATE 120 +#define CLK_TREE_USB3A_0_APB_GATE 121 +#define CLK_TREE_USB3A_0_PHY2_GATE 122 +#define CLK_TREE_USB3A_1_AXI_GATE 123 +#define CLK_TREE_USB3A_1_APB_GATE 124 +#define CLK_TREE_USB3A_1_PHY2_GATE 125 +#define CLK_TREE_USB3A_PHY3_GATE 126 +#define CLK_TREE_USB2_0_CLK_SOF 127 +#define CLK_TREE_USB2_1_CLK_SOF 128 +#define CLK_TREE_USB2_2_CLK_SOF 129 +#define CLK_TREE_USB2_3_CLK_SOF 130 +#define CLK_TREE_USB3C_DRD_CLK_SOF 131 +#define CLK_TREE_USB3C_H0_CLK_SOF 132 +#define CLK_TREE_USB3C_H1_CLK_SOF 133 +#define CLK_TREE_USB3C_H2_CLK_SOF 134 +#define CLK_TREE_USB3A_H0_CLK_SOF 135 +#define CLK_TREE_USB3A_H1_CLK_SOF 136 +#define CLK_TREE_USB2_0_CLK_LPM 137 +#define CLK_TREE_USB2_1_CLK_LPM 138 +#define CLK_TREE_USB2_2_CLK_LPM 139 +#define CLK_TREE_USB2_3_CLK_LPM 140 +#define CLK_TREE_USB3C_DRD_CLK_LPM 141 +#define CLK_TREE_USB3C_H0_CLK_LPM 142 +#define CLK_TREE_USB3C_H1_CLK_LPM 143 +#define CLK_TREE_USB3C_H2_CLK_LPM 144 +#define CLK_TREE_USB3A_H0_CLK_LPM 145 +#define CLK_TREE_USB3A_H1_CLK_LPM 146 +#define CLK_TREE_USB2_0_PHY_REF 147 +#define CLK_TREE_USB2_1_PHY_REF 148 +#define CLK_TREE_USB2_2_PHY_REF 149 +#define CLK_TREE_USB2_3_PHY_REF 150 +#define CLK_TREE_USB3C_DRD_PHY_REF 151 +#define CLK_TREE_USB3C_H0_PHY_REF 152 +#define CLK_TREE_USB3C_H1_PHY_REF 153 +#define CLK_TREE_USB3C_H2_PHY_REF 154 +#define CLK_TREE_USB3A_H0_PHY_REF 155 +#define CLK_TREE_USB3A_H1_PHY_REF 156 +#define CLK_TREE_USB3C_DRD_PHY_x4_REF 157 +#define CLK_TREE_USB3C_H0_PHY_x4_REF 158 +#define CLK_TREE_USB3C_H1_PHY_x4_REF 159 +#define CLK_TREE_USB3C_H2_PHY_x4_REF 160 +#define CLK_TREE_USB3A_PHY_x2_REF 161 +#define CLK_TREE_PCIE_X8CTRL_APB 162 +#define CLK_TREE_PCIE_X4CTRL_APB 163 +#define CLK_TREE_PCIE_X2CTRL_APB 164 +#define CLK_TREE_PCIE_X1_0CTRL_APB 165 +#define CLK_TREE_PCIE_X1_1CTRL_APB 166 +#define CLK_TREE_PCIE_X8_PHY_APB 167 +#define CLK_TREE_PCIE_X4_PHY_APB 168 +#define CLK_TREE_PCIE_X211_PHY_APB 169 +#define CLK_TREE_PCIE_NI700_CLK 170 +#define CLK_TREE_PCIE_CTRL0_CLK 171 +#define CLK_TREE_PCIE_CTRL1_CLK 172 +#define CLK_TREE_PCIE_CTRL2_CLK 173 +#define CLK_TREE_PCIE_CTRL3_CLK 174 +#define CLK_TREE_PCIE_CTRL4_CLK 175 +#define CLK_TREE_CSI_CTRL0_SYSCLK 176 +#define CLK_TREE_CSI_CTRL1_SYSCLK 177 +#define CLK_TREE_CSI_CTRL2_SYSCLK 178 +#define CLK_TREE_CSI_CTRL3_SYSCLK 179 +#define CLK_TREE_CSI_CTRL0_PIXEL0_CLK 180 +#define CLK_TREE_CSI_CTRL0_PIXEL1_CLK 181 +#define CLK_TREE_CSI_CTRL0_PIXEL2_CLK 182 +#define CLK_TREE_CSI_CTRL0_PIXEL3_CLK 183 +#define CLK_TREE_CSI_CTRL1_PIXEL0_CLK 184 +#define CLK_TREE_CSI_CTRL2_PIXEL0_CLK 185 +#define CLK_TREE_CSI_CTRL2_PIXEL1_CLK 186 +#define CLK_TREE_CSI_CTRL2_PIXEL2_CLK 187 +#define CLK_TREE_CSI_CTRL2_PIXEL3_CLK 188 +#define CLK_TREE_CSI_CTRL3_PIXEL0_CLK 189 +#define CLK_TREE_CI700_GCLK0 190 +#define CLK_TREE_DDRC0_ACLK_CLK 191 +#define CLK_TREE_DDRC1_ACLK_CLK 192 +#define CLK_TREE_DDRC2_ACLK_CLK 193 +#define CLK_TREE_DDRC3_ACLK_CLK 194 +#define CLK_TREE_DDRC0_DFICLK_CLK 195 +#define CLK_TREE_DDRC1_DFICLK_CLK 196 +#define CLK_TREE_DDRC2_DFICLK_CLK 197 +#define CLK_TREE_DDRC3_DFICLK_CLK 198 +#define CLK_TREE_PHY0_SYNC_CLK 199 +#define CLK_TREE_PHY1_SYNC_CLK 200 +#define CLK_TREE_PHY2_SYNC_CLK 201 +#define CLK_TREE_PHY3_SYNC_CLK 202 +#define CLK_TREE_PHY0_BYPASS_CLK 203 +#define CLK_TREE_PHY1_BYPASS_CLK 204 +#define CLK_TREE_PHY2_BYPASS_CLK 205 +#define CLK_TREE_PHY3_BYPASS_CLK 206 +#define CLK_TREE_DDRC_0_APB 207 +#define CLK_TREE_DDRC_1_APB 208 +#define CLK_TREE_DDRC_2_APB 209 +#define CLK_TREE_DDRC_3_APB 210 +#define CLK_TREE_TZC400_0_APB 211 +#define CLK_TREE_TZC400_1_APB 212 +#define CLK_TREE_TZC400_2_APB 213 +#define CLK_TREE_TZC400_3_APB 214 +#define CLK_TREE_S5_SENSOR_HUB_25M 215 +#define CLK_TREE_S5_SENSOR_HUB_400M 216 +#define CLK_TREE_S5_CSS600_100M 217 +#define CLK_TREE_S5_DFD_800M 218 +#define CLK_TREE_S5_CSU_SE_800M 219 +#define CLK_TREE_S5_CSU_PM_800M 220 +#define CLK_TREE_PCIE_REF_B0 221 +#define CLK_TREE_PCIE_REF_B1 222 +#define CLK_TREE_PCIE_REF_B2 223 +#define CLK_TREE_PCIE_REF_B3 224 +#define CLK_TREE_PCIE_REF_B4 225 +#define CLK_TREE_PCIE_REF_PHY_X8 226 +#define CLK_TREE_PCIE_REF_PHY_X4 227 +#define CLK_TREE_PCIE_REF_PHY_X211 228 +#define CLK_TREE_GMAC_REC_CLK 229 +#define CLK_TREE_GPUTOP_PLL 230 +#define CLK_TREE_GPUCORE_PLL 231 +#define CLK_TREE_CPU_PLL_LIT 232 +#define CLK_TREE_CPU_PLL0 233 +#define CLK_TREE_CPU_PLL1 234 +#define CLK_TREE_CPU_PLL2 235 +#define CLK_TREE_CPU_PLL3 236 +#define CLK_TREE_FCH_I3C0_FUNC 237 +#define CLK_TREE_FCH_I3C1_FUNC 238 +#define CLK_TREE_FCH_DMA_ACLK 239 +#define CLK_TREE_FCH_XSPI_FUNC 240 +#define CLK_TREE_FCH_XSPI_MACLK 241 +#define CLK_TREE_FCH_TIMER_FUN 242 +#define CLK_TREE_FCH_APB_IO_S0 243 +#define CLK_TREE_FCH_I3C0_APB 244 +#define CLK_TREE_FCH_I3C1_APB 245 +#define CLK_TREE_FCH_UART0_APB 246 +#define CLK_TREE_FCH_UART1_APB 247 +#define CLK_TREE_FCH_UART2_APB 248 +#define CLK_TREE_FCH_UART3_APB 249 +#define CLK_TREE_FCH_SPI0_APB 250 +#define CLK_TREE_FCH_SPI1_APB 251 +#define CLK_TREE_FCH_XSPI_APB 252 +#define CLK_TREE_FCH_I2C0_APB 253 +#define CLK_TREE_FCH_I2C1_APB 254 +#define CLK_TREE_FCH_I2C2_APB 255 +#define CLK_TREE_FCH_I2C3_APB 256 +#define CLK_TREE_FCH_I2C4_APB 257 +#define CLK_TREE_FCH_I2C5_APB 258 +#define CLK_TREE_FCH_I2C6_APB 259 +#define CLK_TREE_FCH_I2C7_APB 260 +#define CLK_TREE_FCH_TIMER_APB 261 +#define CLK_TREE_FCH_GPIO_APB 262 +#define CLK_TREE_FCH_UART0_FUNC 263 +#define CLK_TREE_FCH_UART1_FUNC 264 +#define CLK_TREE_FCH_UART2_FUNC 265 +#define CLK_TREE_FCH_UART3_FUNC 266 +/* 267~271 not used by AP, skip */ +#define CLK_TREE_GPU_CLK_200M 272 + +#endif diff --git a/include/dt-bindings/clock/mediatek,mt8188-clk.h b/include/dt-bindings/clock/mediatek,mt8188-clk.h index bd5cd100b796..0e87f61c90f4 100644 --- a/include/dt-bindings/clock/mediatek,mt8188-clk.h +++ b/include/dt-bindings/clock/mediatek,mt8188-clk.h @@ -721,6 +721,6 @@ #define CLK_VDO1_DPINTF 58 #define CLK_VDO1_DISP_MONITOR_DPINTF 59 #define CLK_VDO1_26M_SLOW 60 -#define CLK_VDO1_NR_CLK 61 +#define CLK_VDO1_DPI1_HDMI 61 #endif /* _DT_BINDINGS_CLK_MT8188_H */ diff --git a/include/dt-bindings/clock/mediatek,mtmips-sysc.h b/include/dt-bindings/clock/mediatek,mtmips-sysc.h new file mode 100644 index 000000000000..a03335b0e077 --- /dev/null +++ b/include/dt-bindings/clock/mediatek,mtmips-sysc.h @@ -0,0 +1,130 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Author: Sergio Paracuellos <sergio.paracuellos@gmail.com> + */ + +#ifndef _DT_BINDINGS_CLK_MTMIPS_H +#define _DT_BINDINGS_CLK_MTMIPS_H + +/* Ralink RT-2880 clocks */ + +#define RT2880_CLK_XTAL 0 +#define RT2880_CLK_CPU 1 +#define RT2880_CLK_BUS 2 +#define RT2880_CLK_TIMER 3 +#define RT2880_CLK_WATCHDOG 4 +#define RT2880_CLK_UART 5 +#define RT2880_CLK_I2C 6 +#define RT2880_CLK_UARTLITE 7 +#define RT2880_CLK_ETHERNET 8 +#define RT2880_CLK_WMAC 9 + +/* Ralink RT-305X clocks */ + +#define RT305X_CLK_XTAL 0 +#define RT305X_CLK_CPU 1 +#define RT305X_CLK_BUS 2 +#define RT305X_CLK_TIMER 3 +#define RT305X_CLK_WATCHDOG 4 +#define RT305X_CLK_UART 5 +#define RT305X_CLK_I2C 6 +#define RT305X_CLK_I2S 7 +#define RT305X_CLK_SPI1 8 +#define RT305X_CLK_SPI2 9 +#define RT305X_CLK_UARTLITE 10 +#define RT305X_CLK_ETHERNET 11 +#define RT305X_CLK_WMAC 12 + +/* Ralink RT-3352 clocks */ + +#define RT3352_CLK_XTAL 0 +#define RT3352_CLK_CPU 1 +#define RT3352_CLK_PERIPH 2 +#define RT3352_CLK_BUS 3 +#define RT3352_CLK_TIMER 4 +#define RT3352_CLK_WATCHDOG 5 +#define RT3352_CLK_UART 6 +#define RT3352_CLK_I2C 7 +#define RT3352_CLK_I2S 8 +#define RT3352_CLK_SPI1 9 +#define RT3352_CLK_SPI2 10 +#define RT3352_CLK_UARTLITE 11 +#define RT3352_CLK_ETHERNET 12 +#define RT3352_CLK_WMAC 13 + +/* Ralink RT-3883 clocks */ + +#define RT3883_CLK_XTAL 0 +#define RT3883_CLK_CPU 1 +#define RT3883_CLK_BUS 2 +#define RT3883_CLK_PERIPH 3 +#define RT3883_CLK_TIMER 4 +#define RT3883_CLK_WATCHDOG 5 +#define RT3883_CLK_UART 6 +#define RT3883_CLK_I2C 7 +#define RT3883_CLK_I2S 8 +#define RT3883_CLK_SPI1 9 +#define RT3883_CLK_SPI2 10 +#define RT3883_CLK_UARTLITE 11 +#define RT3883_CLK_ETHERNET 12 +#define RT3883_CLK_WMAC 13 + +/* Ralink RT-5350 clocks */ + +#define RT5350_CLK_XTAL 0 +#define RT5350_CLK_CPU 1 +#define RT5350_CLK_BUS 2 +#define RT5350_CLK_PERIPH 3 +#define RT5350_CLK_TIMER 4 +#define RT5350_CLK_WATCHDOG 5 +#define RT5350_CLK_UART 6 +#define RT5350_CLK_I2C 7 +#define RT5350_CLK_I2S 8 +#define RT5350_CLK_SPI1 9 +#define RT5350_CLK_SPI2 10 +#define RT5350_CLK_UARTLITE 11 +#define RT5350_CLK_ETHERNET 12 +#define RT5350_CLK_WMAC 13 + +/* Ralink MT-7620 clocks */ + +#define MT7620_CLK_XTAL 0 +#define MT7620_CLK_PLL 1 +#define MT7620_CLK_CPU 2 +#define MT7620_CLK_PERIPH 3 +#define MT7620_CLK_BUS 4 +#define MT7620_CLK_BBPPLL 5 +#define MT7620_CLK_SDHC 6 +#define MT7620_CLK_TIMER 7 +#define MT7620_CLK_WATCHDOG 8 +#define MT7620_CLK_UART 9 +#define MT7620_CLK_I2C 10 +#define MT7620_CLK_I2S 11 +#define MT7620_CLK_SPI1 12 +#define MT7620_CLK_SPI2 13 +#define MT7620_CLK_UARTLITE 14 +#define MT7620_CLK_MMC 15 +#define MT7620_CLK_WMAC 16 + +/* Ralink MT-76X8 clocks */ + +#define MT76X8_CLK_XTAL 0 +#define MT76X8_CLK_CPU 1 +#define MT76X8_CLK_BBPPLL 2 +#define MT76X8_CLK_PCMI2S 3 +#define MT76X8_CLK_PERIPH 4 +#define MT76X8_CLK_BUS 5 +#define MT76X8_CLK_SDHC 6 +#define MT76X8_CLK_TIMER 7 +#define MT76X8_CLK_WATCHDOG 8 +#define MT76X8_CLK_I2C 9 +#define MT76X8_CLK_I2S 10 +#define MT76X8_CLK_SPI1 11 +#define MT76X8_CLK_SPI2 12 +#define MT76X8_CLK_UART0 13 +#define MT76X8_CLK_UART1 14 +#define MT76X8_CLK_UART2 15 +#define MT76X8_CLK_MMC 16 +#define MT76X8_CLK_WMAC 17 + +#endif /* _DT_BINDINGS_CLK_MTMIPS_H */ diff --git a/include/dt-bindings/clock/nvidia,tegra264.h b/include/dt-bindings/clock/nvidia,tegra264.h new file mode 100644 index 000000000000..0fc2ad5e6cef --- /dev/null +++ b/include/dt-bindings/clock/nvidia,tegra264.h @@ -0,0 +1,466 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* Copyright (c) 2022-2025, NVIDIA CORPORATION. All rights reserved. */ + +#ifndef DT_BINDINGS_CLOCK_NVIDIA_TEGRA264_H +#define DT_BINDINGS_CLOCK_NVIDIA_TEGRA264_H + +#define TEGRA264_CLK_OSC 1 +#define TEGRA264_CLK_CLK_S 2 +#define TEGRA264_CLK_JTAG_REG 3 +#define TEGRA264_CLK_SPLL 4 +#define TEGRA264_CLK_SPLL_OUT0 5 +#define TEGRA264_CLK_SPLL_OUT1 6 +#define TEGRA264_CLK_SPLL_OUT2 7 +#define TEGRA264_CLK_SPLL_OUT3 8 +#define TEGRA264_CLK_SPLL_OUT4 9 +#define TEGRA264_CLK_SPLL_OUT5 10 +#define TEGRA264_CLK_SPLL_OUT6 11 +#define TEGRA264_CLK_SPLL_OUT7 12 +#define TEGRA264_CLK_AON_I2C 13 +#define TEGRA264_CLK_HOST1X 14 +#define TEGRA264_CLK_ISP 15 +#define TEGRA264_CLK_ISP1 16 +#define TEGRA264_CLK_ISP_ROOT 17 +#define TEGRA264_CLK_NAFLL_PVA0_CORE 18 +#define TEGRA264_CLK_NAFLL_PVA0_VPS 19 +#define TEGRA264_CLK_NVCSI 20 +#define TEGRA264_CLK_NVCSILP 21 +#define TEGRA264_CLK_PLLP_OUT0 22 +#define TEGRA264_CLK_PVA0_CPU_AXI 23 +#define TEGRA264_CLK_PVA0_VPS 24 +#define TEGRA264_CLK_PWM10 25 +#define TEGRA264_CLK_PWM2 26 +#define TEGRA264_CLK_PWM3 27 +#define TEGRA264_CLK_PWM4 28 +#define TEGRA264_CLK_PWM5 29 +#define TEGRA264_CLK_PWM9 30 +#define TEGRA264_CLK_QSPI0 31 +#define TEGRA264_CLK_QSPI0_2X_PM 32 +#define TEGRA264_CLK_RCE1_CPU 33 +#define TEGRA264_CLK_RCE1_NIC 34 +#define TEGRA264_CLK_RCE_CPU 35 +#define TEGRA264_CLK_RCE_NIC 36 +#define TEGRA264_CLK_SE 37 +#define TEGRA264_CLK_SEU1 38 +#define TEGRA264_CLK_SEU2 39 +#define TEGRA264_CLK_SEU3 40 +#define TEGRA264_CLK_SE_ROOT 41 +#define TEGRA264_CLK_SPI1 42 +#define TEGRA264_CLK_SPI2 43 +#define TEGRA264_CLK_SPI3 44 +#define TEGRA264_CLK_SPI4 45 +#define TEGRA264_CLK_SPI5 46 +#define TEGRA264_CLK_TOP_I2C 47 +#define TEGRA264_CLK_TSEC 48 +#define TEGRA264_CLK_TSEC_PKA 49 +#define TEGRA264_CLK_UART0 50 +#define TEGRA264_CLK_UART10 51 +#define TEGRA264_CLK_UART11 52 +#define TEGRA264_CLK_UART4 53 +#define TEGRA264_CLK_UART5 54 +#define TEGRA264_CLK_UART8 55 +#define TEGRA264_CLK_UART9 56 +#define TEGRA264_CLK_VI 57 +#define TEGRA264_CLK_VI1 58 +#define TEGRA264_CLK_VIC 59 +#define TEGRA264_CLK_VI_ROOT 60 +#define TEGRA264_CLK_DISPPLL 61 +#define TEGRA264_CLK_SPPLL0 62 +#define TEGRA264_CLK_SPPLL0_CLKOUT1A 63 +#define TEGRA264_CLK_SPPLL0_CLKOUT2A 64 +#define TEGRA264_CLK_SPPLL1 65 +#define TEGRA264_CLK_VPLL0 66 +#define TEGRA264_CLK_VPLL1 67 +#define TEGRA264_CLK_VPLL2 68 +#define TEGRA264_CLK_VPLL3 69 +#define TEGRA264_CLK_VPLL4 70 +#define TEGRA264_CLK_VPLL5 71 +#define TEGRA264_CLK_VPLL6 72 +#define TEGRA264_CLK_VPLL7 73 +#define TEGRA264_CLK_RG0_DIV 74 +#define TEGRA264_CLK_RG1_DIV 75 +#define TEGRA264_CLK_RG2_DIV 76 +#define TEGRA264_CLK_RG3_DIV 77 +#define TEGRA264_CLK_RG4_DIV 78 +#define TEGRA264_CLK_RG5_DIV 79 +#define TEGRA264_CLK_RG6_DIV 80 +#define TEGRA264_CLK_RG7_DIV 81 +#define TEGRA264_CLK_RG0 82 +#define TEGRA264_CLK_RG1 83 +#define TEGRA264_CLK_RG2 84 +#define TEGRA264_CLK_RG3 85 +#define TEGRA264_CLK_RG4 86 +#define TEGRA264_CLK_RG5 87 +#define TEGRA264_CLK_RG6 88 +#define TEGRA264_CLK_RG7 89 +#define TEGRA264_CLK_DISP 90 +#define TEGRA264_CLK_DSC 91 +#define TEGRA264_CLK_DSC_ROOT 92 +#define TEGRA264_CLK_HUB 93 +#define TEGRA264_CLK_VPLLX_SOR0_MUXED 94 +#define TEGRA264_CLK_VPLLX_SOR1_MUXED 95 +#define TEGRA264_CLK_VPLLX_SOR2_MUXED 96 +#define TEGRA264_CLK_VPLLX_SOR3_MUXED 97 +#define TEGRA264_CLK_LINKA_SYM 98 +#define TEGRA264_CLK_LINKB_SYM 99 +#define TEGRA264_CLK_LINKC_SYM 100 +#define TEGRA264_CLK_LINKD_SYM 101 +#define TEGRA264_CLK_PRE_SOR0 102 +#define TEGRA264_CLK_PRE_SOR1 103 +#define TEGRA264_CLK_PRE_SOR2 104 +#define TEGRA264_CLK_PRE_SOR3 105 +#define TEGRA264_CLK_SOR0_PLL_REF 106 +#define TEGRA264_CLK_SOR1_PLL_REF 107 +#define TEGRA264_CLK_SOR2_PLL_REF 108 +#define TEGRA264_CLK_SOR3_PLL_REF 109 +#define TEGRA264_CLK_SOR0_PAD 110 +#define TEGRA264_CLK_SOR1_PAD 111 +#define TEGRA264_CLK_SOR2_PAD 112 +#define TEGRA264_CLK_SOR3_PAD 113 +#define TEGRA264_CLK_SOR0_REF 114 +#define TEGRA264_CLK_SOR1_REF 115 +#define TEGRA264_CLK_SOR2_REF 116 +#define TEGRA264_CLK_SOR3_REF 117 +#define TEGRA264_CLK_SOR0_DIV 118 +#define TEGRA264_CLK_SOR1_DIV 119 +#define TEGRA264_CLK_SOR2_DIV 120 +#define TEGRA264_CLK_SOR3_DIV 121 +#define TEGRA264_CLK_SOR0 122 +#define TEGRA264_CLK_SOR1 123 +#define TEGRA264_CLK_SOR2 124 +#define TEGRA264_CLK_SOR3 125 +#define TEGRA264_CLK_SF0_SOR 126 +#define TEGRA264_CLK_SF1_SOR 127 +#define TEGRA264_CLK_SF2_SOR 128 +#define TEGRA264_CLK_SF3_SOR 129 +#define TEGRA264_CLK_SF4_SOR 130 +#define TEGRA264_CLK_SF5_SOR 131 +#define TEGRA264_CLK_SF6_SOR 132 +#define TEGRA264_CLK_SF7_SOR 133 +#define TEGRA264_CLK_SF0 134 +#define TEGRA264_CLK_SF1 135 +#define TEGRA264_CLK_SF2 136 +#define TEGRA264_CLK_SF3 137 +#define TEGRA264_CLK_SF4 138 +#define TEGRA264_CLK_SF5 139 +#define TEGRA264_CLK_SF6 140 +#define TEGRA264_CLK_SF7 141 +#define TEGRA264_CLK_MAUD 142 +#define TEGRA264_CLK_AZA_2XBIT 143 +#define TEGRA264_CLK_DCE_CPU 144 +#define TEGRA264_CLK_DCE_NIC 145 +#define TEGRA264_CLK_PLLC4 146 +#define TEGRA264_CLK_PLLC4_OUT0 147 +#define TEGRA264_CLK_PLLC4_OUT1 148 +#define TEGRA264_CLK_PLLC4_MUXED 149 +#define TEGRA264_CLK_SDMMC1 150 +#define TEGRA264_CLK_SDMMC_LEGACY_TM 151 +#define TEGRA264_CLK_PLLC0 152 +#define TEGRA264_CLK_NAFLL_BPMP 153 +#define TEGRA264_CLK_PLLP_OUT_PDIV 154 +#define TEGRA264_CLK_DISP_ROOT 155 +#define TEGRA264_CLK_ADSP 156 +#define TEGRA264_CLK_PLLA 157 +#define TEGRA264_CLK_PLLA1 158 +#define TEGRA264_CLK_PLLA1_OUT1 159 +#define TEGRA264_CLK_PLLAON 160 +#define TEGRA264_CLK_PLLAON_APE 161 +#define TEGRA264_CLK_PLLA_OUT0 162 +#define TEGRA264_CLK_AHUB 163 +#define TEGRA264_CLK_APE 164 +#define TEGRA264_CLK_I2S1_SCLK_IN 165 +#define TEGRA264_CLK_I2S2_SCLK_IN 166 +#define TEGRA264_CLK_I2S3_SCLK_IN 167 +#define TEGRA264_CLK_I2S4_SCLK_IN 168 +#define TEGRA264_CLK_I2S5_SCLK_IN 169 +#define TEGRA264_CLK_I2S6_SCLK_IN 170 +#define TEGRA264_CLK_I2S7_SCLK_IN 171 +#define TEGRA264_CLK_I2S8_SCLK_IN 172 +#define TEGRA264_CLK_I2S9_SCLK_IN 173 +#define TEGRA264_CLK_I2S1_AUDIO_SYNC 174 +#define TEGRA264_CLK_I2S2_AUDIO_SYNC 175 +#define TEGRA264_CLK_I2S3_AUDIO_SYNC 176 +#define TEGRA264_CLK_I2S4_AUDIO_SYNC 177 +#define TEGRA264_CLK_I2S5_AUDIO_SYNC 178 +#define TEGRA264_CLK_I2S6_AUDIO_SYNC 179 +#define TEGRA264_CLK_I2S7_AUDIO_SYNC 180 +#define TEGRA264_CLK_I2S8_AUDIO_SYNC 181 +#define TEGRA264_CLK_DMIC1_AUDIO_SYNC 182 +#define TEGRA264_CLK_DSPK1_AUDIO_SYNC 183 +#define TEGRA264_CLK_I2S1 184 +#define TEGRA264_CLK_I2S2 185 +#define TEGRA264_CLK_I2S3 186 +#define TEGRA264_CLK_I2S4 187 +#define TEGRA264_CLK_I2S5 188 +#define TEGRA264_CLK_I2S6 189 +#define TEGRA264_CLK_I2S7 190 +#define TEGRA264_CLK_I2S8 191 +#define TEGRA264_CLK_I2S9 192 +#define TEGRA264_CLK_DMIC1 193 +#define TEGRA264_CLK_DMIC5 194 +#define TEGRA264_CLK_DSPK1 195 +#define TEGRA264_CLK_AON_CPU 196 +#define TEGRA264_CLK_AON_NIC 197 +#define TEGRA264_CLK_BPMP 198 +#define TEGRA264_CLK_AXI_CBB 199 +#define TEGRA264_CLK_FUSE 200 +#define TEGRA264_CLK_TSENSE 201 +#define TEGRA264_CLK_CSITE 202 +#define TEGRA264_CLK_HCSITE 203 +#define TEGRA264_CLK_DBGAPB 204 +#define TEGRA264_CLK_LA 205 +#define TEGRA264_CLK_PLLREFGP 206 +#define TEGRA264_CLK_PLLE0 207 +#define TEGRA264_CLK_UPHY0_PLL0_XDIG 208 +#define TEGRA264_CLK_EQOS_APP 209 +#define TEGRA264_CLK_EQOS_MAC 210 +#define TEGRA264_CLK_EQOS_MACSEC 211 +#define TEGRA264_CLK_EQOS_TX_PCS 212 +#define TEGRA264_CLK_MGBES_PTP_REF 213 +#define TEGRA264_CLK_MGBE0_UPHY1_PLL_XDIG 214 +#define TEGRA264_CLK_MGBE0_TX_PCS 215 +#define TEGRA264_CLK_MGBE0_MAC 216 +#define TEGRA264_CLK_MGBE0_MACSEC 217 +#define TEGRA264_CLK_MGBE0_APP 218 +#define TEGRA264_CLK_MGBE1_UPHY1_PLL_XDIG 219 +#define TEGRA264_CLK_MGBE1_TX_PCS 220 +#define TEGRA264_CLK_MGBE1_MAC 221 +#define TEGRA264_CLK_MGBE1_MACSEC 222 +#define TEGRA264_CLK_MGBE1_APP 223 +#define TEGRA264_CLK_MGBE2_UPHY1_PLL_XDIG 224 +#define TEGRA264_CLK_MGBE2_TX_PCS 225 +#define TEGRA264_CLK_MGBE2_MAC 226 +#define TEGRA264_CLK_MGBE2_MACSEC 227 +#define TEGRA264_CLK_MGBE2_APP 228 +#define TEGRA264_CLK_MGBE3_UPHY1_PLL_XDIG 229 +#define TEGRA264_CLK_MGBE3_TX_PCS 230 +#define TEGRA264_CLK_MGBE3_MAC 231 +#define TEGRA264_CLK_MGBE3_MACSEC 232 +#define TEGRA264_CLK_MGBE3_APP 233 +#define TEGRA264_CLK_PLLREFUFS 234 +#define TEGRA264_CLK_PLLREFUFS_CLKOUT624 235 +#define TEGRA264_CLK_PLLREFUFS_REFCLKOUT 236 +#define TEGRA264_CLK_PLLREFUFS_UFSDEV_REFCLKOUT 237 +#define TEGRA264_CLK_UFSHC_CG_SYS 238 +#define TEGRA264_CLK_MPHY_L0_RX_LS_BIT_DIV 239 +#define TEGRA264_CLK_MPHY_L0_RX_LS_BIT 240 +#define TEGRA264_CLK_MPHY_L0_RX_LS_SYMB_DIV 241 +#define TEGRA264_CLK_MPHY_L0_RX_HS_SYMB_DIV 242 +#define TEGRA264_CLK_MPHY_L0_RX_SYMB 243 +#define TEGRA264_CLK_MPHY_L0_UPHY_TX_FIFO 244 +#define TEGRA264_CLK_MPHY_L0_TX_LS_3XBIT_DIV 245 +#define TEGRA264_CLK_MPHY_L0_TX_LS_SYMB_DIV 246 +#define TEGRA264_CLK_UPHY0_PLL4_XDIG 247 +#define TEGRA264_CLK_MPHY_L0_TX_HS_SYMB_DIV 248 +#define TEGRA264_CLK_MPHY_L0_TX_SYMB 249 +#define TEGRA264_CLK_MPHY_L0_TX_LS_3XBIT 250 +#define TEGRA264_CLK_MPHY_L0_RX_ANA 251 +#define TEGRA264_CLK_MPHY_L1_RX_ANA 252 +#define TEGRA264_CLK_MPHY_TX_1MHZ_REF 253 +#define TEGRA264_CLK_MPHY_CORE_PLL_FIXED 254 +#define TEGRA264_CLK_MPHY_IOBIST 255 +#define TEGRA264_CLK_UFSHC_CG_SYS_DIV 256 +#define TEGRA264_CLK_XUSB1_CORE 257 +#define TEGRA264_CLK_XUSB1_FALCON 258 +#define TEGRA264_CLK_XUSB1_FS 259 +#define TEGRA264_CLK_XUSB1_SS 260 +#define TEGRA264_CLK_UPHY0_USB_P0_RX_CORE 261 +#define TEGRA264_CLK_UPHY0_USB_P1_RX_CORE 262 +#define TEGRA264_CLK_UPHY0_USB_P2_RX_CORE 263 +#define TEGRA264_CLK_UPHY0_USB_P3_RX_CORE 264 +#define TEGRA264_CLK_XUSB1_CLK480M_NVWRAP_CORE 265 +#define TEGRA264_CLK_XUSB1_CORE_HOST 266 +#define TEGRA264_CLK_XUSB1_CORE_DEV 267 +#define TEGRA264_CLK_XUSB1_CORE_SUPERSPEED 268 +#define TEGRA264_CLK_XUSB1_FALCON_HOST 269 +#define TEGRA264_CLK_XUSB1_FALCON_SUPERSPEED 270 +#define TEGRA264_CLK_XUSB1_FS_HOST 271 +#define TEGRA264_CLK_XUSB1_FS_DEV 272 +#define TEGRA264_CLK_XUSB1_HS_HSICP 273 +#define TEGRA264_CLK_XUSB1_SS_DEV 274 +#define TEGRA264_CLK_XUSB1_SS_SUPERSPEED 275 +#define TEGRA264_CLK_AON_TOUCH 276 +#define TEGRA264_CLK_AUD_MCLK 277 +#define TEGRA264_CLK_EXTPERIPH1 278 +#define TEGRA264_CLK_EXTPERIPH2 279 +#define TEGRA264_CLK_EXTPERIPH3 280 +#define TEGRA264_CLK_EXTPERIPH4 281 +#define TEGRA264_CLK_JTAG_REG_UNGATED 282 +#define TEGRA264_CLK_IST_BUS 283 +#define TEGRA264_CLK_IST_BUS_RIST_MCC 284 +#define TEGRA264_CLK_MATHS_SEC_RIST 285 +#define TEGRA264_CLK_NAFLL_IST 286 +#define TEGRA264_CLK_RIST_ROOT 287 +#define TEGRA264_CLK_IST_CONTROLLER_RIST 288 +#define TEGRA264_CLK_MSS_ENCRYPT 289 +#define TEGRA264_CLK_EMC 290 +#define TEGRA264_CLK_SPPLL0_CLKOUT100 291 +#define TEGRA264_CLK_SPPLL0_CLKOUT270 292 +#define TEGRA264_CLK_SPPLL1_CLKOUT100 293 +#define TEGRA264_CLK_SPPLL1_CLKOUT270 294 +#define TEGRA264_CLK_DP_LINKA_REF 295 +#define TEGRA264_CLK_DP_LINKB_REF 296 +#define TEGRA264_CLK_DP_LINKC_REF 297 +#define TEGRA264_CLK_DP_LINKD_REF 298 +#define TEGRA264_CLK_PLLNVCSI 299 +#define TEGRA264_CLK_PLLBPMPCAM 300 +#define TEGRA264_CLK_UTMI_PLL1 301 +#define TEGRA264_CLK_UTMI_PLL1_CLKOUT48 302 +#define TEGRA264_CLK_UTMI_PLL1_CLKOUT60 303 +#define TEGRA264_CLK_UTMI_PLL1_CLKOUT480 304 +#define TEGRA264_CLK_NAFLL_ISP 305 +#define TEGRA264_CLK_NAFLL_RCE 306 +#define TEGRA264_CLK_NAFLL_RCE1 307 +#define TEGRA264_CLK_NAFLL_SE 308 +#define TEGRA264_CLK_NAFLL_VI 309 +#define TEGRA264_CLK_NAFLL_VIC 310 +#define TEGRA264_CLK_NAFLL_DCE 311 +#define TEGRA264_CLK_NAFLL_TSEC 312 +#define TEGRA264_CLK_NAFLL_CPAIR0 313 +#define TEGRA264_CLK_NAFLL_CPAIR1 314 +#define TEGRA264_CLK_NAFLL_CPAIR2 315 +#define TEGRA264_CLK_NAFLL_CPAIR3 316 +#define TEGRA264_CLK_NAFLL_CPAIR4 317 +#define TEGRA264_CLK_NAFLL_CPAIR5 318 +#define TEGRA264_CLK_NAFLL_CPAIR6 319 +#define TEGRA264_CLK_NAFLL_GPU_SYS 320 +#define TEGRA264_CLK_NAFLL_GPU_NVD 321 +#define TEGRA264_CLK_NAFLL_GPU_UPROC 322 +#define TEGRA264_CLK_NAFLL_GPU_GPC0 323 +#define TEGRA264_CLK_NAFLL_GPU_GPC1 324 +#define TEGRA264_CLK_NAFLL_GPU_GPC2 325 +#define TEGRA264_CLK_SOR_LINKA_INPUT 326 +#define TEGRA264_CLK_SOR_LINKB_INPUT 327 +#define TEGRA264_CLK_SOR_LINKC_INPUT 328 +#define TEGRA264_CLK_SOR_LINKD_INPUT 329 +#define TEGRA264_CLK_SOR_LINKA_AFIFO 330 +#define TEGRA264_CLK_SOR_LINKB_AFIFO 331 +#define TEGRA264_CLK_SOR_LINKC_AFIFO 332 +#define TEGRA264_CLK_SOR_LINKD_AFIFO 333 +#define TEGRA264_CLK_I2S1_PAD_M 334 +#define TEGRA264_CLK_I2S2_PAD_M 335 +#define TEGRA264_CLK_I2S3_PAD_M 336 +#define TEGRA264_CLK_I2S4_PAD_M 337 +#define TEGRA264_CLK_I2S5_PAD_M 338 +#define TEGRA264_CLK_I2S6_PAD_M 339 +#define TEGRA264_CLK_I2S7_PAD_M 340 +#define TEGRA264_CLK_I2S8_PAD_M 341 +#define TEGRA264_CLK_I2S9_PAD_M 342 +#define TEGRA264_CLK_BPMP_NIC 343 +#define TEGRA264_CLK_CLK1M 344 +#define TEGRA264_CLK_RDET 345 +#define TEGRA264_CLK_ADC_SOC_REF 346 +#define TEGRA264_CLK_UPHY0_PLL0_TXREF 347 +#define TEGRA264_CLK_EQOS_TX 348 +#define TEGRA264_CLK_EQOS_TX_M 349 +#define TEGRA264_CLK_EQOS_RX_PCS_IN 350 +#define TEGRA264_CLK_EQOS_RX_PCS_M 351 +#define TEGRA264_CLK_EQOS_RX_IN 352 +#define TEGRA264_CLK_EQOS_RX 353 +#define TEGRA264_CLK_EQOS_RX_M 354 +#define TEGRA264_CLK_MGBE0_UPHY1_PLL_TXREF 355 +#define TEGRA264_CLK_MGBE0_TX 356 +#define TEGRA264_CLK_MGBE0_TX_M 357 +#define TEGRA264_CLK_MGBE0_RX_PCS_IN 358 +#define TEGRA264_CLK_MGBE0_RX_PCS_M 359 +#define TEGRA264_CLK_MGBE0_RX_IN 360 +#define TEGRA264_CLK_MGBE0_RX_M 361 +#define TEGRA264_CLK_MGBE1_UPHY1_PLL_TXREF 362 +#define TEGRA264_CLK_MGBE1_TX 363 +#define TEGRA264_CLK_MGBE1_TX_M 364 +#define TEGRA264_CLK_MGBE1_RX_PCS_IN 365 +#define TEGRA264_CLK_MGBE1_RX_PCS_M 366 +#define TEGRA264_CLK_MGBE1_RX_IN 367 +#define TEGRA264_CLK_MGBE1_RX_M 368 +#define TEGRA264_CLK_MGBE2_UPHY1_PLL_TXREF 369 +#define TEGRA264_CLK_MGBE2_TX 370 +#define TEGRA264_CLK_MGBE2_TX_M 371 +#define TEGRA264_CLK_MGBE2_RX_PCS_IN 372 +#define TEGRA264_CLK_MGBE2_RX_PCS_M 373 +#define TEGRA264_CLK_MGBE2_RX_IN 374 +#define TEGRA264_CLK_MGBE2_RX_M 375 +#define TEGRA264_CLK_MGBE3_UPHY1_PLL_TXREF 376 +#define TEGRA264_CLK_MGBE3_TX 377 +#define TEGRA264_CLK_MGBE3_TX_M 378 +#define TEGRA264_CLK_MGBE3_RX_PCS_IN 379 +#define TEGRA264_CLK_MGBE3_RX_PCS_M 380 +#define TEGRA264_CLK_MGBE3_RX_IN 381 +#define TEGRA264_CLK_MGBE3_RX_M 382 +#define TEGRA264_CLK_UPHY0_USB_P0_TX_CORE 383 +#define TEGRA264_CLK_UPHY0_USB_P1_TX_CORE 384 +#define TEGRA264_CLK_UPHY0_USB_P2_TX_CORE 385 +#define TEGRA264_CLK_UPHY0_USB_P3_TX_CORE 386 +#define TEGRA264_CLK_UPHY0_USB_P0_TX 387 +#define TEGRA264_CLK_UPHY0_USB_P1_TX 388 +#define TEGRA264_CLK_UPHY0_USB_P2_TX 389 +#define TEGRA264_CLK_UPHY0_USB_P3_TX 390 +#define TEGRA264_CLK_UPHY0_USB_P0_RX_IN 391 +#define TEGRA264_CLK_UPHY0_USB_P1_RX_IN 392 +#define TEGRA264_CLK_UPHY0_USB_P2_RX_IN 393 +#define TEGRA264_CLK_UPHY0_USB_P3_RX_IN 394 +#define TEGRA264_CLK_UPHY0_USB_P0_RX_M 395 +#define TEGRA264_CLK_UPHY0_USB_P1_RX_M 396 +#define TEGRA264_CLK_UPHY0_USB_P2_RX_M 397 +#define TEGRA264_CLK_UPHY0_USB_P3_RX_M 398 +#define TEGRA264_CLK_UPHY0_LANE0_TX_M 399 +#define TEGRA264_CLK_PCIE_C1_XCLK_NOBG_M 400 +#define TEGRA264_CLK_PCIE_C2_XCLK_NOBG_M 401 +#define TEGRA264_CLK_PCIE_C3_XCLK_NOBG_M 402 +#define TEGRA264_CLK_PCIE_C4_XCLK_NOBG_M 403 +#define TEGRA264_CLK_PCIE_C5_XCLK_NOBG_M 404 +#define TEGRA264_CLK_PCIE_C1_L0_RX_M 405 +#define TEGRA264_CLK_PCIE_C1_L1_RX_M 406 +#define TEGRA264_CLK_PCIE_C1_L2_RX_M 407 +#define TEGRA264_CLK_PCIE_C1_L3_RX_M 408 +#define TEGRA264_CLK_PCIE_C2_L0_RX_M 409 +#define TEGRA264_CLK_PCIE_C2_L1_RX_M 410 +#define TEGRA264_CLK_PCIE_C2_L2_RX_M 411 +#define TEGRA264_CLK_PCIE_C2_L3_RX_M 412 +#define TEGRA264_CLK_PCIE_C3_L0_RX_M 413 +#define TEGRA264_CLK_PCIE_C3_L1_RX_M 414 +#define TEGRA264_CLK_PCIE_C4_L0_RX_M 415 +#define TEGRA264_CLK_PCIE_C4_L1_RX_M 416 +#define TEGRA264_CLK_PCIE_C4_L2_RX_M 417 +#define TEGRA264_CLK_PCIE_C4_L3_RX_M 418 +#define TEGRA264_CLK_PCIE_C4_L4_RX_M 419 +#define TEGRA264_CLK_PCIE_C4_L5_RX_M 420 +#define TEGRA264_CLK_PCIE_C4_L6_RX_M 421 +#define TEGRA264_CLK_PCIE_C4_L7_RX_M 422 +#define TEGRA264_CLK_PCIE_C5_L0_RX_M 423 +#define TEGRA264_CLK_PCIE_C5_L1_RX_M 424 +#define TEGRA264_CLK_PCIE_C5_L2_RX_M 425 +#define TEGRA264_CLK_PCIE_C5_L3_RX_M 426 +#define TEGRA264_CLK_MPHY_L0_RX_PWM_BIT_M 427 +#define TEGRA264_CLK_MPHY_L1_RX_PWM_BIT_M 428 +#define TEGRA264_CLK_DBB_UPHY0 429 +#define TEGRA264_CLK_UPHY0_UXL_CORE 430 +#define TEGRA264_CLK_ISC_CPU_ROOT 431 +#define TEGRA264_CLK_ISC_NIC 432 +#define TEGRA264_CLK_CTC_TXCLK0_M 433 +#define TEGRA264_CLK_CTC_TXCLK1_M 434 +#define TEGRA264_CLK_CTC_RXCLK0_M 435 +#define TEGRA264_CLK_CTC_RXCLK1_M 436 +#define TEGRA264_CLK_PLLREFGP_OUT 437 +#define TEGRA264_CLK_PLLREFGP_OUT1 438 +#define TEGRA264_CLK_GPU_SYS 439 +#define TEGRA264_CLK_GPU_NVD 440 +#define TEGRA264_CLK_GPU_UPROC 441 +#define TEGRA264_CLK_GPU_GPC0 442 +#define TEGRA264_CLK_GPU_GPC1 443 +#define TEGRA264_CLK_GPU_GPC2 444 +#define TEGRA264_CLK_PLLX 445 +#define TEGRA264_CLK_APE_SOUNDWIRE_MSRC0 446 +#define TEGRA264_CLK_APE_SOUNDWIRE_DATA_EN_SHAPER 447 +#define TEGRA264_CLK_AO_SOUNDWIRE_MSRC0 448 +#define TEGRA264_CLK_AO_SOUNDWIRE_DATA_EN_SHAPER 449 +#define TEGRA264_CLK_MGBE0_TX_SER 459 +#define TEGRA264_CLK_MGBE1_TX_SER 460 +#define TEGRA264_CLK_MGBE2_TX_SER 461 +#define TEGRA264_CLK_MGBE3_TX_SER 462 +#define TEGRA264_CLK_MGBE0_RX_SER 463 +#define TEGRA264_CLK_MGBE1_RX_SER 464 +#define TEGRA264_CLK_MGBE2_RX_SER 465 +#define TEGRA264_CLK_MGBE3_RX_SER 466 +#define TEGRA264_CLK_DPAUX 467 + +#endif /* DT_BINDINGS_CLOCK_NVIDIA_TEGRA264_H */ diff --git a/include/dt-bindings/clock/nxp,imx94-clock.h b/include/dt-bindings/clock/nxp,imx94-clock.h new file mode 100644 index 000000000000..c4ba13352b99 --- /dev/null +++ b/include/dt-bindings/clock/nxp,imx94-clock.h @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright 2025 NXP + */ + +#ifndef __DT_BINDINGS_CLOCK_IMX94_H +#define __DT_BINDINGS_CLOCK_IMX94_H + +#define IMX94_CLK_DISPMIX_CLK_SEL 0 + +#define IMX94_CLK_DISPMIX_LVDS_CLK_GATE 0 + +#endif /* __DT_BINDINGS_CLOCK_IMX94_H */ diff --git a/include/dt-bindings/clock/qcom,dsi-phy-28nm.h b/include/dt-bindings/clock/qcom,dsi-phy-28nm.h new file mode 100644 index 000000000000..ab94d58377a1 --- /dev/null +++ b/include/dt-bindings/clock/qcom,dsi-phy-28nm.h @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */ + +#ifndef _DT_BINDINGS_CLK_QCOM_DSI_PHY_28NM_H +#define _DT_BINDINGS_CLK_QCOM_DSI_PHY_28NM_H + +#define DSI_BYTE_PLL_CLK 0 +#define DSI_PIXEL_PLL_CLK 1 + +#endif diff --git a/include/dt-bindings/clock/qcom,gcc-sc8180x.h b/include/dt-bindings/clock/qcom,gcc-sc8180x.h index e364006aa6ea..b9d8438a15ff 100644 --- a/include/dt-bindings/clock/qcom,gcc-sc8180x.h +++ b/include/dt-bindings/clock/qcom,gcc-sc8180x.h @@ -249,6 +249,16 @@ #define GCC_UFS_MEM_CLKREF_EN 239 #define GCC_UFS_CARD_CLKREF_EN 240 #define GPLL9 241 +#define GCC_CAMERA_AHB_CLK 242 +#define GCC_CAMERA_XO_CLK 243 +#define GCC_CPUSS_DVM_BUS_CLK 244 +#define GCC_CPUSS_GNOC_CLK 245 +#define GCC_DISP_AHB_CLK 246 +#define GCC_DISP_XO_CLK 247 +#define GCC_GPU_CFG_AHB_CLK 248 +#define GCC_NPU_CFG_AHB_CLK 249 +#define GCC_VIDEO_AHB_CLK 250 +#define GCC_VIDEO_XO_CLK 251 #define GCC_EMAC_BCR 0 #define GCC_GPU_BCR 1 diff --git a/include/dt-bindings/clock/qcom,gcc-sdm660.h b/include/dt-bindings/clock/qcom,gcc-sdm660.h index df8a6f3d367e..74c22f67da21 100644 --- a/include/dt-bindings/clock/qcom,gcc-sdm660.h +++ b/include/dt-bindings/clock/qcom,gcc-sdm660.h @@ -153,5 +153,7 @@ #define GCC_USB_30_BCR 7 #define GCC_USB_PHY_CFG_AHB2PHY_BCR 8 #define GCC_MSS_RESTART 9 +#define GCC_SDCC1_BCR 10 +#define GCC_SDCC2_BCR 11 #endif diff --git a/include/dt-bindings/clock/qcom,ipq5018-cmn-pll.h b/include/dt-bindings/clock/qcom,ipq5018-cmn-pll.h new file mode 100644 index 000000000000..586d1c9b33b3 --- /dev/null +++ b/include/dt-bindings/clock/qcom,ipq5018-cmn-pll.h @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_IPQ5018_CMN_PLL_H +#define _DT_BINDINGS_CLK_QCOM_IPQ5018_CMN_PLL_H + +/* CMN PLL core clock. */ +#define IPQ5018_CMN_PLL_CLK 0 + +/* The output clocks from CMN PLL of IPQ5018. */ +#define IPQ5018_XO_24MHZ_CLK 1 +#define IPQ5018_SLEEP_32KHZ_CLK 2 +#define IPQ5018_ETH_50MHZ_CLK 3 +#endif diff --git a/include/dt-bindings/clock/qcom,ipq5424-cmn-pll.h b/include/dt-bindings/clock/qcom,ipq5424-cmn-pll.h new file mode 100644 index 000000000000..f643c2668c04 --- /dev/null +++ b/include/dt-bindings/clock/qcom,ipq5424-cmn-pll.h @@ -0,0 +1,22 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) 2025 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_IPQ5424_CMN_PLL_H +#define _DT_BINDINGS_CLK_QCOM_IPQ5424_CMN_PLL_H + +/* CMN PLL core clock. */ +#define IPQ5424_CMN_PLL_CLK 0 + +/* The output clocks from CMN PLL of IPQ5424. */ +#define IPQ5424_XO_24MHZ_CLK 1 +#define IPQ5424_SLEEP_32KHZ_CLK 2 +#define IPQ5424_PCS_31P25MHZ_CLK 3 +#define IPQ5424_NSS_300MHZ_CLK 4 +#define IPQ5424_PPE_375MHZ_CLK 5 +#define IPQ5424_ETH0_50MHZ_CLK 6 +#define IPQ5424_ETH1_50MHZ_CLK 7 +#define IPQ5424_ETH2_50MHZ_CLK 8 +#define IPQ5424_ETH_25MHZ_CLK 9 +#endif diff --git a/include/dt-bindings/clock/qcom,ipq9574-gcc.h b/include/dt-bindings/clock/qcom,ipq9574-gcc.h index f238aa4794a8..0e7c319897f3 100644 --- a/include/dt-bindings/clock/qcom,ipq9574-gcc.h +++ b/include/dt-bindings/clock/qcom,ipq9574-gcc.h @@ -202,4 +202,5 @@ #define GCC_PCIE1_PIPE_CLK 211 #define GCC_PCIE2_PIPE_CLK 212 #define GCC_PCIE3_PIPE_CLK 213 +#define GPLL0_OUT_AUX 214 #endif diff --git a/include/dt-bindings/clock/qcom,ipq9574-nsscc.h b/include/dt-bindings/clock/qcom,ipq9574-nsscc.h new file mode 100644 index 000000000000..21a16dc0e64c --- /dev/null +++ b/include/dt-bindings/clock/qcom,ipq9574-nsscc.h @@ -0,0 +1,152 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) 2023, 2025 The Linux Foundation. All rights reserved. + */ + +#ifndef _DT_BINDINGS_CLOCK_IPQ_NSSCC_9574_H +#define _DT_BINDINGS_CLOCK_IPQ_NSSCC_9574_H + +#define NSS_CC_CE_APB_CLK 0 +#define NSS_CC_CE_AXI_CLK 1 +#define NSS_CC_CE_CLK_SRC 2 +#define NSS_CC_CFG_CLK_SRC 3 +#define NSS_CC_CLC_AXI_CLK 4 +#define NSS_CC_CLC_CLK_SRC 5 +#define NSS_CC_CRYPTO_CLK 6 +#define NSS_CC_CRYPTO_CLK_SRC 7 +#define NSS_CC_CRYPTO_PPE_CLK 8 +#define NSS_CC_HAQ_AHB_CLK 9 +#define NSS_CC_HAQ_AXI_CLK 10 +#define NSS_CC_HAQ_CLK_SRC 11 +#define NSS_CC_IMEM_AHB_CLK 12 +#define NSS_CC_IMEM_CLK_SRC 13 +#define NSS_CC_IMEM_QSB_CLK 14 +#define NSS_CC_INT_CFG_CLK_SRC 15 +#define NSS_CC_NSS_CSR_CLK 16 +#define NSS_CC_NSSNOC_CE_APB_CLK 17 +#define NSS_CC_NSSNOC_CE_AXI_CLK 18 +#define NSS_CC_NSSNOC_CLC_AXI_CLK 19 +#define NSS_CC_NSSNOC_CRYPTO_CLK 20 +#define NSS_CC_NSSNOC_HAQ_AHB_CLK 21 +#define NSS_CC_NSSNOC_HAQ_AXI_CLK 22 +#define NSS_CC_NSSNOC_IMEM_AHB_CLK 23 +#define NSS_CC_NSSNOC_IMEM_QSB_CLK 24 +#define NSS_CC_NSSNOC_NSS_CSR_CLK 25 +#define NSS_CC_NSSNOC_PPE_CFG_CLK 26 +#define NSS_CC_NSSNOC_PPE_CLK 27 +#define NSS_CC_NSSNOC_UBI32_AHB0_CLK 28 +#define NSS_CC_NSSNOC_UBI32_AXI0_CLK 29 +#define NSS_CC_NSSNOC_UBI32_INT0_AHB_CLK 30 +#define NSS_CC_NSSNOC_UBI32_NC_AXI0_1_CLK 31 +#define NSS_CC_NSSNOC_UBI32_NC_AXI0_CLK 32 +#define NSS_CC_PORT1_MAC_CLK 33 +#define NSS_CC_PORT1_RX_CLK 34 +#define NSS_CC_PORT1_RX_CLK_SRC 35 +#define NSS_CC_PORT1_RX_DIV_CLK_SRC 36 +#define NSS_CC_PORT1_TX_CLK 37 +#define NSS_CC_PORT1_TX_CLK_SRC 38 +#define NSS_CC_PORT1_TX_DIV_CLK_SRC 39 +#define NSS_CC_PORT2_MAC_CLK 40 +#define NSS_CC_PORT2_RX_CLK 41 +#define NSS_CC_PORT2_RX_CLK_SRC 42 +#define NSS_CC_PORT2_RX_DIV_CLK_SRC 43 +#define NSS_CC_PORT2_TX_CLK 44 +#define NSS_CC_PORT2_TX_CLK_SRC 45 +#define NSS_CC_PORT2_TX_DIV_CLK_SRC 46 +#define NSS_CC_PORT3_MAC_CLK 47 +#define NSS_CC_PORT3_RX_CLK 48 +#define NSS_CC_PORT3_RX_CLK_SRC 49 +#define NSS_CC_PORT3_RX_DIV_CLK_SRC 50 +#define NSS_CC_PORT3_TX_CLK 51 +#define NSS_CC_PORT3_TX_CLK_SRC 52 +#define NSS_CC_PORT3_TX_DIV_CLK_SRC 53 +#define NSS_CC_PORT4_MAC_CLK 54 +#define NSS_CC_PORT4_RX_CLK 55 +#define NSS_CC_PORT4_RX_CLK_SRC 56 +#define NSS_CC_PORT4_RX_DIV_CLK_SRC 57 +#define NSS_CC_PORT4_TX_CLK 58 +#define NSS_CC_PORT4_TX_CLK_SRC 59 +#define NSS_CC_PORT4_TX_DIV_CLK_SRC 60 +#define NSS_CC_PORT5_MAC_CLK 61 +#define NSS_CC_PORT5_RX_CLK 62 +#define NSS_CC_PORT5_RX_CLK_SRC 63 +#define NSS_CC_PORT5_RX_DIV_CLK_SRC 64 +#define NSS_CC_PORT5_TX_CLK 65 +#define NSS_CC_PORT5_TX_CLK_SRC 66 +#define NSS_CC_PORT5_TX_DIV_CLK_SRC 67 +#define NSS_CC_PORT6_MAC_CLK 68 +#define NSS_CC_PORT6_RX_CLK 69 +#define NSS_CC_PORT6_RX_CLK_SRC 70 +#define NSS_CC_PORT6_RX_DIV_CLK_SRC 71 +#define NSS_CC_PORT6_TX_CLK 72 +#define NSS_CC_PORT6_TX_CLK_SRC 73 +#define NSS_CC_PORT6_TX_DIV_CLK_SRC 74 +#define NSS_CC_PPE_CLK_SRC 75 +#define NSS_CC_PPE_EDMA_CFG_CLK 76 +#define NSS_CC_PPE_EDMA_CLK 77 +#define NSS_CC_PPE_SWITCH_BTQ_CLK 78 +#define NSS_CC_PPE_SWITCH_CFG_CLK 79 +#define NSS_CC_PPE_SWITCH_CLK 80 +#define NSS_CC_PPE_SWITCH_IPE_CLK 81 +#define NSS_CC_UBI0_CLK_SRC 82 +#define NSS_CC_UBI0_DIV_CLK_SRC 83 +#define NSS_CC_UBI1_CLK_SRC 84 +#define NSS_CC_UBI1_DIV_CLK_SRC 85 +#define NSS_CC_UBI2_CLK_SRC 86 +#define NSS_CC_UBI2_DIV_CLK_SRC 87 +#define NSS_CC_UBI32_AHB0_CLK 88 +#define NSS_CC_UBI32_AHB1_CLK 89 +#define NSS_CC_UBI32_AHB2_CLK 90 +#define NSS_CC_UBI32_AHB3_CLK 91 +#define NSS_CC_UBI32_AXI0_CLK 92 +#define NSS_CC_UBI32_AXI1_CLK 93 +#define NSS_CC_UBI32_AXI2_CLK 94 +#define NSS_CC_UBI32_AXI3_CLK 95 +#define NSS_CC_UBI32_CORE0_CLK 96 +#define NSS_CC_UBI32_CORE1_CLK 97 +#define NSS_CC_UBI32_CORE2_CLK 98 +#define NSS_CC_UBI32_CORE3_CLK 99 +#define NSS_CC_UBI32_INTR0_AHB_CLK 100 +#define NSS_CC_UBI32_INTR1_AHB_CLK 101 +#define NSS_CC_UBI32_INTR2_AHB_CLK 102 +#define NSS_CC_UBI32_INTR3_AHB_CLK 103 +#define NSS_CC_UBI32_NC_AXI0_CLK 104 +#define NSS_CC_UBI32_NC_AXI1_CLK 105 +#define NSS_CC_UBI32_NC_AXI2_CLK 106 +#define NSS_CC_UBI32_NC_AXI3_CLK 107 +#define NSS_CC_UBI32_UTCM0_CLK 108 +#define NSS_CC_UBI32_UTCM1_CLK 109 +#define NSS_CC_UBI32_UTCM2_CLK 110 +#define NSS_CC_UBI32_UTCM3_CLK 111 +#define NSS_CC_UBI3_CLK_SRC 112 +#define NSS_CC_UBI3_DIV_CLK_SRC 113 +#define NSS_CC_UBI_AXI_CLK_SRC 114 +#define NSS_CC_UBI_NC_AXI_BFDCD_CLK_SRC 115 +#define NSS_CC_UNIPHY_PORT1_RX_CLK 116 +#define NSS_CC_UNIPHY_PORT1_TX_CLK 117 +#define NSS_CC_UNIPHY_PORT2_RX_CLK 118 +#define NSS_CC_UNIPHY_PORT2_TX_CLK 119 +#define NSS_CC_UNIPHY_PORT3_RX_CLK 120 +#define NSS_CC_UNIPHY_PORT3_TX_CLK 121 +#define NSS_CC_UNIPHY_PORT4_RX_CLK 122 +#define NSS_CC_UNIPHY_PORT4_TX_CLK 123 +#define NSS_CC_UNIPHY_PORT5_RX_CLK 124 +#define NSS_CC_UNIPHY_PORT5_TX_CLK 125 +#define NSS_CC_UNIPHY_PORT6_RX_CLK 126 +#define NSS_CC_UNIPHY_PORT6_TX_CLK 127 +#define NSS_CC_XGMAC0_PTP_REF_CLK 128 +#define NSS_CC_XGMAC0_PTP_REF_DIV_CLK_SRC 129 +#define NSS_CC_XGMAC1_PTP_REF_CLK 130 +#define NSS_CC_XGMAC1_PTP_REF_DIV_CLK_SRC 131 +#define NSS_CC_XGMAC2_PTP_REF_CLK 132 +#define NSS_CC_XGMAC2_PTP_REF_DIV_CLK_SRC 133 +#define NSS_CC_XGMAC3_PTP_REF_CLK 134 +#define NSS_CC_XGMAC3_PTP_REF_DIV_CLK_SRC 135 +#define NSS_CC_XGMAC4_PTP_REF_CLK 136 +#define NSS_CC_XGMAC4_PTP_REF_DIV_CLK_SRC 137 +#define NSS_CC_XGMAC5_PTP_REF_CLK 138 +#define NSS_CC_XGMAC5_PTP_REF_DIV_CLK_SRC 139 +#define UBI32_PLL 140 +#define UBI32_PLL_MAIN 141 + +#endif diff --git a/include/dt-bindings/clock/qcom,milos-camcc.h b/include/dt-bindings/clock/qcom,milos-camcc.h new file mode 100644 index 000000000000..21925dca9a20 --- /dev/null +++ b/include/dt-bindings/clock/qcom,milos-camcc.h @@ -0,0 +1,131 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2025, Luca Weiss <luca.weiss@fairphone.com> + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_CAM_CC_MILOS_H +#define _DT_BINDINGS_CLK_QCOM_CAM_CC_MILOS_H + +/* CAM_CC clocks */ +#define CAM_CC_PLL0 0 +#define CAM_CC_PLL0_OUT_EVEN 1 +#define CAM_CC_PLL0_OUT_ODD 2 +#define CAM_CC_PLL1 3 +#define CAM_CC_PLL1_OUT_EVEN 4 +#define CAM_CC_PLL2 5 +#define CAM_CC_PLL2_OUT_EVEN 6 +#define CAM_CC_PLL3 7 +#define CAM_CC_PLL3_OUT_EVEN 8 +#define CAM_CC_PLL4 9 +#define CAM_CC_PLL4_OUT_EVEN 10 +#define CAM_CC_PLL5 11 +#define CAM_CC_PLL5_OUT_EVEN 12 +#define CAM_CC_PLL6 13 +#define CAM_CC_PLL6_OUT_EVEN 14 +#define CAM_CC_BPS_AHB_CLK 15 +#define CAM_CC_BPS_AREG_CLK 16 +#define CAM_CC_BPS_CLK 17 +#define CAM_CC_BPS_CLK_SRC 18 +#define CAM_CC_CAMNOC_ATB_CLK 19 +#define CAM_CC_CAMNOC_AXI_CLK_SRC 20 +#define CAM_CC_CAMNOC_AXI_HF_CLK 21 +#define CAM_CC_CAMNOC_AXI_SF_CLK 22 +#define CAM_CC_CAMNOC_NRT_AXI_CLK 23 +#define CAM_CC_CAMNOC_RT_AXI_CLK 24 +#define CAM_CC_CCI_0_CLK 25 +#define CAM_CC_CCI_0_CLK_SRC 26 +#define CAM_CC_CCI_1_CLK 27 +#define CAM_CC_CCI_1_CLK_SRC 28 +#define CAM_CC_CORE_AHB_CLK 29 +#define CAM_CC_CPAS_AHB_CLK 30 +#define CAM_CC_CPHY_RX_CLK_SRC 31 +#define CAM_CC_CRE_AHB_CLK 32 +#define CAM_CC_CRE_CLK 33 +#define CAM_CC_CRE_CLK_SRC 34 +#define CAM_CC_CSI0PHYTIMER_CLK 35 +#define CAM_CC_CSI0PHYTIMER_CLK_SRC 36 +#define CAM_CC_CSI1PHYTIMER_CLK 37 +#define CAM_CC_CSI1PHYTIMER_CLK_SRC 38 +#define CAM_CC_CSI2PHYTIMER_CLK 39 +#define CAM_CC_CSI2PHYTIMER_CLK_SRC 40 +#define CAM_CC_CSI3PHYTIMER_CLK 41 +#define CAM_CC_CSI3PHYTIMER_CLK_SRC 42 +#define CAM_CC_CSIPHY0_CLK 43 +#define CAM_CC_CSIPHY1_CLK 44 +#define CAM_CC_CSIPHY2_CLK 45 +#define CAM_CC_CSIPHY3_CLK 46 +#define CAM_CC_FAST_AHB_CLK_SRC 47 +#define CAM_CC_GDSC_CLK 48 +#define CAM_CC_ICP_ATB_CLK 49 +#define CAM_CC_ICP_CLK 50 +#define CAM_CC_ICP_CLK_SRC 51 +#define CAM_CC_ICP_CTI_CLK 52 +#define CAM_CC_ICP_TS_CLK 53 +#define CAM_CC_MCLK0_CLK 54 +#define CAM_CC_MCLK0_CLK_SRC 55 +#define CAM_CC_MCLK1_CLK 56 +#define CAM_CC_MCLK1_CLK_SRC 57 +#define CAM_CC_MCLK2_CLK 58 +#define CAM_CC_MCLK2_CLK_SRC 59 +#define CAM_CC_MCLK3_CLK 60 +#define CAM_CC_MCLK3_CLK_SRC 61 +#define CAM_CC_MCLK4_CLK 62 +#define CAM_CC_MCLK4_CLK_SRC 63 +#define CAM_CC_OPE_0_AHB_CLK 64 +#define CAM_CC_OPE_0_AREG_CLK 65 +#define CAM_CC_OPE_0_CLK 66 +#define CAM_CC_OPE_0_CLK_SRC 67 +#define CAM_CC_SLEEP_CLK 68 +#define CAM_CC_SLEEP_CLK_SRC 69 +#define CAM_CC_SLOW_AHB_CLK_SRC 70 +#define CAM_CC_SOC_AHB_CLK 71 +#define CAM_CC_SYS_TMR_CLK 72 +#define CAM_CC_TFE_0_AHB_CLK 73 +#define CAM_CC_TFE_0_CLK 74 +#define CAM_CC_TFE_0_CLK_SRC 75 +#define CAM_CC_TFE_0_CPHY_RX_CLK 76 +#define CAM_CC_TFE_0_CSID_CLK 77 +#define CAM_CC_TFE_0_CSID_CLK_SRC 78 +#define CAM_CC_TFE_1_AHB_CLK 79 +#define CAM_CC_TFE_1_CLK 80 +#define CAM_CC_TFE_1_CLK_SRC 81 +#define CAM_CC_TFE_1_CPHY_RX_CLK 82 +#define CAM_CC_TFE_1_CSID_CLK 83 +#define CAM_CC_TFE_1_CSID_CLK_SRC 84 +#define CAM_CC_TFE_2_AHB_CLK 85 +#define CAM_CC_TFE_2_CLK 86 +#define CAM_CC_TFE_2_CLK_SRC 87 +#define CAM_CC_TFE_2_CPHY_RX_CLK 88 +#define CAM_CC_TFE_2_CSID_CLK 89 +#define CAM_CC_TFE_2_CSID_CLK_SRC 90 +#define CAM_CC_TOP_SHIFT_CLK 91 +#define CAM_CC_XO_CLK_SRC 92 + +/* CAM_CC resets */ +#define CAM_CC_BPS_BCR 0 +#define CAM_CC_CAMNOC_BCR 1 +#define CAM_CC_CAMSS_TOP_BCR 2 +#define CAM_CC_CCI_0_BCR 3 +#define CAM_CC_CCI_1_BCR 4 +#define CAM_CC_CPAS_BCR 5 +#define CAM_CC_CRE_BCR 6 +#define CAM_CC_CSI0PHY_BCR 7 +#define CAM_CC_CSI1PHY_BCR 8 +#define CAM_CC_CSI2PHY_BCR 9 +#define CAM_CC_CSI3PHY_BCR 10 +#define CAM_CC_ICP_BCR 11 +#define CAM_CC_MCLK0_BCR 12 +#define CAM_CC_MCLK1_BCR 13 +#define CAM_CC_MCLK2_BCR 14 +#define CAM_CC_MCLK3_BCR 15 +#define CAM_CC_MCLK4_BCR 16 +#define CAM_CC_OPE_0_BCR 17 +#define CAM_CC_TFE_0_BCR 18 +#define CAM_CC_TFE_1_BCR 19 +#define CAM_CC_TFE_2_BCR 20 + +/* CAM_CC power domains */ +#define CAM_CC_CAMSS_TOP_GDSC 0 + +#endif diff --git a/include/dt-bindings/clock/qcom,milos-dispcc.h b/include/dt-bindings/clock/qcom,milos-dispcc.h new file mode 100644 index 000000000000..c70f23f32f0a --- /dev/null +++ b/include/dt-bindings/clock/qcom,milos-dispcc.h @@ -0,0 +1,61 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2025, Luca Weiss <luca.weiss@fairphone.com> + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_DISP_CC_MILOS_H +#define _DT_BINDINGS_CLK_QCOM_DISP_CC_MILOS_H + +/* DISP_CC clocks */ +#define DISP_CC_PLL0 0 +#define DISP_CC_MDSS_ACCU_CLK 1 +#define DISP_CC_MDSS_AHB1_CLK 2 +#define DISP_CC_MDSS_AHB_CLK 3 +#define DISP_CC_MDSS_AHB_CLK_SRC 4 +#define DISP_CC_MDSS_BYTE0_CLK 5 +#define DISP_CC_MDSS_BYTE0_CLK_SRC 6 +#define DISP_CC_MDSS_BYTE0_DIV_CLK_SRC 7 +#define DISP_CC_MDSS_BYTE0_INTF_CLK 8 +#define DISP_CC_MDSS_DPTX0_AUX_CLK 9 +#define DISP_CC_MDSS_DPTX0_AUX_CLK_SRC 10 +#define DISP_CC_MDSS_DPTX0_CRYPTO_CLK 11 +#define DISP_CC_MDSS_DPTX0_LINK_CLK 12 +#define DISP_CC_MDSS_DPTX0_LINK_CLK_SRC 13 +#define DISP_CC_MDSS_DPTX0_LINK_DIV_CLK_SRC 14 +#define DISP_CC_MDSS_DPTX0_LINK_INTF_CLK 15 +#define DISP_CC_MDSS_DPTX0_PIXEL0_CLK 16 +#define DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC 17 +#define DISP_CC_MDSS_DPTX0_PIXEL1_CLK 18 +#define DISP_CC_MDSS_DPTX0_PIXEL1_CLK_SRC 19 +#define DISP_CC_MDSS_DPTX0_USB_ROUTER_LINK_INTF_CLK 20 +#define DISP_CC_MDSS_ESC0_CLK 21 +#define DISP_CC_MDSS_ESC0_CLK_SRC 22 +#define DISP_CC_MDSS_MDP1_CLK 23 +#define DISP_CC_MDSS_MDP_CLK 24 +#define DISP_CC_MDSS_MDP_CLK_SRC 25 +#define DISP_CC_MDSS_MDP_LUT1_CLK 26 +#define DISP_CC_MDSS_MDP_LUT_CLK 27 +#define DISP_CC_MDSS_NON_GDSC_AHB_CLK 28 +#define DISP_CC_MDSS_PCLK0_CLK 29 +#define DISP_CC_MDSS_PCLK0_CLK_SRC 30 +#define DISP_CC_MDSS_RSCC_AHB_CLK 31 +#define DISP_CC_MDSS_RSCC_VSYNC_CLK 32 +#define DISP_CC_MDSS_VSYNC1_CLK 33 +#define DISP_CC_MDSS_VSYNC_CLK 34 +#define DISP_CC_MDSS_VSYNC_CLK_SRC 35 +#define DISP_CC_SLEEP_CLK 36 +#define DISP_CC_SLEEP_CLK_SRC 37 +#define DISP_CC_XO_CLK 38 +#define DISP_CC_XO_CLK_SRC 39 + +/* DISP_CC resets */ +#define DISP_CC_MDSS_CORE_BCR 0 +#define DISP_CC_MDSS_CORE_INT2_BCR 1 +#define DISP_CC_MDSS_RSCC_BCR 2 + +/* DISP_CC power domains */ +#define DISP_CC_MDSS_CORE_GDSC 0 +#define DISP_CC_MDSS_CORE_INT2_GDSC 1 + +#endif diff --git a/include/dt-bindings/clock/qcom,milos-gcc.h b/include/dt-bindings/clock/qcom,milos-gcc.h new file mode 100644 index 000000000000..a530ca39e1ef --- /dev/null +++ b/include/dt-bindings/clock/qcom,milos-gcc.h @@ -0,0 +1,210 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2025, Luca Weiss <luca.weiss@fairphone.com> + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_GCC_MILOS_H +#define _DT_BINDINGS_CLK_QCOM_GCC_MILOS_H + +/* GCC clocks */ +#define GCC_GPLL0 0 +#define GCC_GPLL0_OUT_EVEN 1 +#define GCC_GPLL2 2 +#define GCC_GPLL4 3 +#define GCC_GPLL6 4 +#define GCC_GPLL7 5 +#define GCC_GPLL9 6 +#define GCC_AGGRE_NOC_PCIE_AXI_CLK 7 +#define GCC_AGGRE_UFS_PHY_AXI_CLK 8 +#define GCC_AGGRE_UFS_PHY_AXI_HW_CTL_CLK 9 +#define GCC_AGGRE_USB3_PRIM_AXI_CLK 10 +#define GCC_BOOT_ROM_AHB_CLK 11 +#define GCC_CAMERA_AHB_CLK 12 +#define GCC_CAMERA_HF_AXI_CLK 13 +#define GCC_CAMERA_HF_XO_CLK 14 +#define GCC_CAMERA_SF_AXI_CLK 15 +#define GCC_CAMERA_SF_XO_CLK 16 +#define GCC_CFG_NOC_PCIE_ANOC_AHB_CLK 17 +#define GCC_CFG_NOC_USB3_PRIM_AXI_CLK 18 +#define GCC_CNOC_PCIE_SF_AXI_CLK 19 +#define GCC_DDRSS_GPU_AXI_CLK 20 +#define GCC_DDRSS_PCIE_SF_QTB_CLK 21 +#define GCC_DISP_AHB_CLK 22 +#define GCC_DISP_GPLL0_DIV_CLK_SRC 23 +#define GCC_DISP_HF_AXI_CLK 24 +#define GCC_DISP_XO_CLK 25 +#define GCC_GP1_CLK 26 +#define GCC_GP1_CLK_SRC 27 +#define GCC_GP2_CLK 28 +#define GCC_GP2_CLK_SRC 29 +#define GCC_GP3_CLK 30 +#define GCC_GP3_CLK_SRC 31 +#define GCC_GPU_CFG_AHB_CLK 32 +#define GCC_GPU_GPLL0_CLK_SRC 33 +#define GCC_GPU_GPLL0_DIV_CLK_SRC 34 +#define GCC_GPU_MEMNOC_GFX_CLK 35 +#define GCC_GPU_SNOC_DVM_GFX_CLK 36 +#define GCC_PCIE_0_AUX_CLK 37 +#define GCC_PCIE_0_AUX_CLK_SRC 38 +#define GCC_PCIE_0_CFG_AHB_CLK 39 +#define GCC_PCIE_0_MSTR_AXI_CLK 40 +#define GCC_PCIE_0_PHY_RCHNG_CLK 41 +#define GCC_PCIE_0_PHY_RCHNG_CLK_SRC 42 +#define GCC_PCIE_0_PIPE_CLK 43 +#define GCC_PCIE_0_PIPE_CLK_SRC 44 +#define GCC_PCIE_0_PIPE_DIV2_CLK 45 +#define GCC_PCIE_0_PIPE_DIV2_CLK_SRC 46 +#define GCC_PCIE_0_SLV_AXI_CLK 47 +#define GCC_PCIE_0_SLV_Q2A_AXI_CLK 48 +#define GCC_PCIE_1_AUX_CLK 49 +#define GCC_PCIE_1_AUX_CLK_SRC 50 +#define GCC_PCIE_1_CFG_AHB_CLK 51 +#define GCC_PCIE_1_MSTR_AXI_CLK 52 +#define GCC_PCIE_1_PHY_RCHNG_CLK 53 +#define GCC_PCIE_1_PHY_RCHNG_CLK_SRC 54 +#define GCC_PCIE_1_PIPE_CLK 55 +#define GCC_PCIE_1_PIPE_CLK_SRC 56 +#define GCC_PCIE_1_PIPE_DIV2_CLK 57 +#define GCC_PCIE_1_PIPE_DIV2_CLK_SRC 58 +#define GCC_PCIE_1_SLV_AXI_CLK 59 +#define GCC_PCIE_1_SLV_Q2A_AXI_CLK 60 +#define GCC_PCIE_RSCC_CFG_AHB_CLK 61 +#define GCC_PCIE_RSCC_XO_CLK 62 +#define GCC_PDM2_CLK 63 +#define GCC_PDM2_CLK_SRC 64 +#define GCC_PDM_AHB_CLK 65 +#define GCC_PDM_XO4_CLK 66 +#define GCC_QMIP_CAMERA_NRT_AHB_CLK 67 +#define GCC_QMIP_CAMERA_RT_AHB_CLK 68 +#define GCC_QMIP_DISP_AHB_CLK 69 +#define GCC_QMIP_GPU_AHB_CLK 70 +#define GCC_QMIP_PCIE_AHB_CLK 71 +#define GCC_QMIP_VIDEO_CV_CPU_AHB_CLK 72 +#define GCC_QMIP_VIDEO_CVP_AHB_CLK 73 +#define GCC_QMIP_VIDEO_V_CPU_AHB_CLK 74 +#define GCC_QMIP_VIDEO_VCODEC_AHB_CLK 75 +#define GCC_QUPV3_WRAP0_CORE_2X_CLK 76 +#define GCC_QUPV3_WRAP0_CORE_CLK 77 +#define GCC_QUPV3_WRAP0_QSPI_REF_CLK 78 +#define GCC_QUPV3_WRAP0_QSPI_REF_CLK_SRC 79 +#define GCC_QUPV3_WRAP0_S0_CLK 80 +#define GCC_QUPV3_WRAP0_S0_CLK_SRC 81 +#define GCC_QUPV3_WRAP0_S1_CLK 82 +#define GCC_QUPV3_WRAP0_S1_CLK_SRC 83 +#define GCC_QUPV3_WRAP0_S2_CLK 84 +#define GCC_QUPV3_WRAP0_S2_CLK_SRC 85 +#define GCC_QUPV3_WRAP0_S3_CLK 86 +#define GCC_QUPV3_WRAP0_S3_CLK_SRC 87 +#define GCC_QUPV3_WRAP0_S4_CLK 88 +#define GCC_QUPV3_WRAP0_S4_CLK_SRC 89 +#define GCC_QUPV3_WRAP0_S5_CLK 90 +#define GCC_QUPV3_WRAP0_S5_CLK_SRC 91 +#define GCC_QUPV3_WRAP0_S6_CLK 92 +#define GCC_QUPV3_WRAP0_S6_CLK_SRC 93 +#define GCC_QUPV3_WRAP1_CORE_2X_CLK 94 +#define GCC_QUPV3_WRAP1_CORE_CLK 95 +#define GCC_QUPV3_WRAP1_QSPI_REF_CLK 96 +#define GCC_QUPV3_WRAP1_QSPI_REF_CLK_SRC 97 +#define GCC_QUPV3_WRAP1_S0_CLK 98 +#define GCC_QUPV3_WRAP1_S0_CLK_SRC 99 +#define GCC_QUPV3_WRAP1_S1_CLK 100 +#define GCC_QUPV3_WRAP1_S1_CLK_SRC 101 +#define GCC_QUPV3_WRAP1_S2_CLK 102 +#define GCC_QUPV3_WRAP1_S2_CLK_SRC 103 +#define GCC_QUPV3_WRAP1_S3_CLK 104 +#define GCC_QUPV3_WRAP1_S3_CLK_SRC 105 +#define GCC_QUPV3_WRAP1_S4_CLK 106 +#define GCC_QUPV3_WRAP1_S4_CLK_SRC 107 +#define GCC_QUPV3_WRAP1_S5_CLK 108 +#define GCC_QUPV3_WRAP1_S5_CLK_SRC 109 +#define GCC_QUPV3_WRAP1_S6_CLK 110 +#define GCC_QUPV3_WRAP1_S6_CLK_SRC 111 +#define GCC_QUPV3_WRAP_0_M_AHB_CLK 112 +#define GCC_QUPV3_WRAP_0_S_AHB_CLK 113 +#define GCC_QUPV3_WRAP_1_M_AHB_CLK 114 +#define GCC_QUPV3_WRAP_1_S_AHB_CLK 115 +#define GCC_SDCC1_AHB_CLK 116 +#define GCC_SDCC1_APPS_CLK 117 +#define GCC_SDCC1_APPS_CLK_SRC 118 +#define GCC_SDCC1_ICE_CORE_CLK 119 +#define GCC_SDCC1_ICE_CORE_CLK_SRC 120 +#define GCC_SDCC2_AHB_CLK 121 +#define GCC_SDCC2_APPS_CLK 122 +#define GCC_SDCC2_APPS_CLK_SRC 123 +#define GCC_UFS_PHY_AHB_CLK 124 +#define GCC_UFS_PHY_AXI_CLK 125 +#define GCC_UFS_PHY_AXI_CLK_SRC 126 +#define GCC_UFS_PHY_AXI_HW_CTL_CLK 127 +#define GCC_UFS_PHY_ICE_CORE_CLK 128 +#define GCC_UFS_PHY_ICE_CORE_CLK_SRC 129 +#define GCC_UFS_PHY_ICE_CORE_HW_CTL_CLK 130 +#define GCC_UFS_PHY_PHY_AUX_CLK 131 +#define GCC_UFS_PHY_PHY_AUX_CLK_SRC 132 +#define GCC_UFS_PHY_PHY_AUX_HW_CTL_CLK 133 +#define GCC_UFS_PHY_RX_SYMBOL_0_CLK 134 +#define GCC_UFS_PHY_RX_SYMBOL_0_CLK_SRC 135 +#define GCC_UFS_PHY_RX_SYMBOL_1_CLK 136 +#define GCC_UFS_PHY_RX_SYMBOL_1_CLK_SRC 137 +#define GCC_UFS_PHY_TX_SYMBOL_0_CLK 138 +#define GCC_UFS_PHY_TX_SYMBOL_0_CLK_SRC 139 +#define GCC_UFS_PHY_UNIPRO_CORE_CLK 140 +#define GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC 141 +#define GCC_UFS_PHY_UNIPRO_CORE_HW_CTL_CLK 142 +#define GCC_USB30_PRIM_ATB_CLK 143 +#define GCC_USB30_PRIM_MASTER_CLK 144 +#define GCC_USB30_PRIM_MASTER_CLK_SRC 145 +#define GCC_USB30_PRIM_MOCK_UTMI_CLK 146 +#define GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC 147 +#define GCC_USB30_PRIM_MOCK_UTMI_POSTDIV_CLK_SRC 148 +#define GCC_USB30_PRIM_SLEEP_CLK 149 +#define GCC_USB3_PRIM_PHY_AUX_CLK 150 +#define GCC_USB3_PRIM_PHY_AUX_CLK_SRC 151 +#define GCC_USB3_PRIM_PHY_COM_AUX_CLK 152 +#define GCC_USB3_PRIM_PHY_PIPE_CLK 153 +#define GCC_USB3_PRIM_PHY_PIPE_CLK_SRC 154 +#define GCC_VIDEO_AHB_CLK 155 +#define GCC_VIDEO_AXI0_CLK 156 +#define GCC_VIDEO_XO_CLK 157 + +/* GCC resets */ +#define GCC_CAMERA_BCR 0 +#define GCC_DISPLAY_BCR 1 +#define GCC_GPU_BCR 2 +#define GCC_PCIE_0_BCR 3 +#define GCC_PCIE_0_LINK_DOWN_BCR 4 +#define GCC_PCIE_0_NOCSR_COM_PHY_BCR 5 +#define GCC_PCIE_0_PHY_BCR 6 +#define GCC_PCIE_0_PHY_NOCSR_COM_PHY_BCR 7 +#define GCC_PCIE_1_BCR 8 +#define GCC_PCIE_1_LINK_DOWN_BCR 9 +#define GCC_PCIE_1_NOCSR_COM_PHY_BCR 10 +#define GCC_PCIE_1_PHY_BCR 11 +#define GCC_PCIE_1_PHY_NOCSR_COM_PHY_BCR 12 +#define GCC_PCIE_RSCC_BCR 13 +#define GCC_PDM_BCR 14 +#define GCC_QUPV3_WRAPPER_0_BCR 15 +#define GCC_QUPV3_WRAPPER_1_BCR 16 +#define GCC_QUSB2PHY_PRIM_BCR 17 +#define GCC_QUSB2PHY_SEC_BCR 18 +#define GCC_SDCC1_BCR 19 +#define GCC_SDCC2_BCR 20 +#define GCC_UFS_PHY_BCR 21 +#define GCC_USB30_PRIM_BCR 22 +#define GCC_USB3_DP_PHY_PRIM_BCR 23 +#define GCC_USB3_PHY_PRIM_BCR 24 +#define GCC_USB3PHY_PHY_PRIM_BCR 25 +#define GCC_VIDEO_AXI0_CLK_ARES 26 +#define GCC_VIDEO_BCR 27 + +/* GCC power domains */ +#define PCIE_0_GDSC 0 +#define PCIE_0_PHY_GDSC 1 +#define PCIE_1_GDSC 2 +#define PCIE_1_PHY_GDSC 3 +#define UFS_PHY_GDSC 4 +#define UFS_MEM_PHY_GDSC 5 +#define USB30_PRIM_GDSC 6 +#define USB3_PHY_GDSC 7 + +#endif diff --git a/include/dt-bindings/clock/qcom,milos-gpucc.h b/include/dt-bindings/clock/qcom,milos-gpucc.h new file mode 100644 index 000000000000..6ff1925d409f --- /dev/null +++ b/include/dt-bindings/clock/qcom,milos-gpucc.h @@ -0,0 +1,56 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2025, Luca Weiss <luca.weiss@fairphone.com> + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_GPU_CC_MILOS_H +#define _DT_BINDINGS_CLK_QCOM_GPU_CC_MILOS_H + +/* GPU_CC clocks */ +#define GPU_CC_PLL0 0 +#define GPU_CC_PLL0_OUT_EVEN 1 +#define GPU_CC_AHB_CLK 2 +#define GPU_CC_CB_CLK 3 +#define GPU_CC_CX_ACCU_SHIFT_CLK 4 +#define GPU_CC_CX_FF_CLK 5 +#define GPU_CC_CX_GMU_CLK 6 +#define GPU_CC_CXO_AON_CLK 7 +#define GPU_CC_CXO_CLK 8 +#define GPU_CC_DEMET_CLK 9 +#define GPU_CC_DEMET_DIV_CLK_SRC 10 +#define GPU_CC_DPM_CLK 11 +#define GPU_CC_FF_CLK_SRC 12 +#define GPU_CC_FREQ_MEASURE_CLK 13 +#define GPU_CC_GMU_CLK_SRC 14 +#define GPU_CC_GX_ACCU_SHIFT_CLK 15 +#define GPU_CC_GX_ACD_AHB_FF_CLK 16 +#define GPU_CC_GX_AHB_FF_CLK 17 +#define GPU_CC_GX_GMU_CLK 18 +#define GPU_CC_GX_RCG_AHB_FF_CLK 19 +#define GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK 20 +#define GPU_CC_HUB_AON_CLK 21 +#define GPU_CC_HUB_CLK_SRC 22 +#define GPU_CC_HUB_CX_INT_CLK 23 +#define GPU_CC_HUB_DIV_CLK_SRC 24 +#define GPU_CC_MEMNOC_GFX_CLK 25 +#define GPU_CC_RSCC_HUB_AON_CLK 26 +#define GPU_CC_RSCC_XO_AON_CLK 27 +#define GPU_CC_SLEEP_CLK 28 +#define GPU_CC_XO_CLK_SRC 29 +#define GPU_CC_XO_DIV_CLK_SRC 30 + +/* GPU_CC resets */ +#define GPU_CC_CB_BCR 0 +#define GPU_CC_CX_BCR 1 +#define GPU_CC_FAST_HUB_BCR 2 +#define GPU_CC_FF_BCR 3 +#define GPU_CC_GMU_BCR 4 +#define GPU_CC_GX_BCR 5 +#define GPU_CC_RBCPR_BCR 6 +#define GPU_CC_XO_BCR 7 + +/* GPU_CC power domains */ +#define GPU_CC_CX_GDSC 0 + +#endif diff --git a/include/dt-bindings/clock/qcom,milos-videocc.h b/include/dt-bindings/clock/qcom,milos-videocc.h new file mode 100644 index 000000000000..3544db81ffae --- /dev/null +++ b/include/dt-bindings/clock/qcom,milos-videocc.h @@ -0,0 +1,36 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2025, Luca Weiss <luca.weiss@fairphone.com> + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_VIDEO_CC_MILOS_H +#define _DT_BINDINGS_CLK_QCOM_VIDEO_CC_MILOS_H + +/* VIDEO_CC clocks */ +#define VIDEO_CC_PLL0 0 +#define VIDEO_CC_AHB_CLK 1 +#define VIDEO_CC_AHB_CLK_SRC 2 +#define VIDEO_CC_MVS0_CLK 3 +#define VIDEO_CC_MVS0_CLK_SRC 4 +#define VIDEO_CC_MVS0_DIV_CLK_SRC 5 +#define VIDEO_CC_MVS0_SHIFT_CLK 6 +#define VIDEO_CC_MVS0C_CLK 7 +#define VIDEO_CC_MVS0C_DIV2_DIV_CLK_SRC 8 +#define VIDEO_CC_MVS0C_SHIFT_CLK 9 +#define VIDEO_CC_SLEEP_CLK 10 +#define VIDEO_CC_SLEEP_CLK_SRC 11 +#define VIDEO_CC_XO_CLK 12 +#define VIDEO_CC_XO_CLK_SRC 13 + +/* VIDEO_CC resets */ +#define VIDEO_CC_INTERFACE_BCR 0 +#define VIDEO_CC_MVS0_BCR 1 +#define VIDEO_CC_MVS0C_CLK_ARES 2 +#define VIDEO_CC_MVS0C_BCR 3 + +/* VIDEO_CC power domains */ +#define VIDEO_CC_MVS0_GDSC 0 +#define VIDEO_CC_MVS0C_GDSC 1 + +#endif diff --git a/include/dt-bindings/clock/qcom,qcs615-camcc.h b/include/dt-bindings/clock/qcom,qcs615-camcc.h new file mode 100644 index 000000000000..aec57dddc067 --- /dev/null +++ b/include/dt-bindings/clock/qcom,qcs615-camcc.h @@ -0,0 +1,110 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_CAM_CC_QCS615_H +#define _DT_BINDINGS_CLK_QCOM_CAM_CC_QCS615_H + +/* CAM_CC clocks */ +#define CAM_CC_BPS_AHB_CLK 0 +#define CAM_CC_BPS_AREG_CLK 1 +#define CAM_CC_BPS_AXI_CLK 2 +#define CAM_CC_BPS_CLK 3 +#define CAM_CC_BPS_CLK_SRC 4 +#define CAM_CC_CAMNOC_ATB_CLK 5 +#define CAM_CC_CAMNOC_AXI_CLK 6 +#define CAM_CC_CCI_CLK 7 +#define CAM_CC_CCI_CLK_SRC 8 +#define CAM_CC_CORE_AHB_CLK 9 +#define CAM_CC_CPAS_AHB_CLK 10 +#define CAM_CC_CPHY_RX_CLK_SRC 11 +#define CAM_CC_CSI0PHYTIMER_CLK 12 +#define CAM_CC_CSI0PHYTIMER_CLK_SRC 13 +#define CAM_CC_CSI1PHYTIMER_CLK 14 +#define CAM_CC_CSI1PHYTIMER_CLK_SRC 15 +#define CAM_CC_CSI2PHYTIMER_CLK 16 +#define CAM_CC_CSI2PHYTIMER_CLK_SRC 17 +#define CAM_CC_CSIPHY0_CLK 18 +#define CAM_CC_CSIPHY1_CLK 19 +#define CAM_CC_CSIPHY2_CLK 20 +#define CAM_CC_FAST_AHB_CLK_SRC 21 +#define CAM_CC_ICP_ATB_CLK 22 +#define CAM_CC_ICP_CLK 23 +#define CAM_CC_ICP_CLK_SRC 24 +#define CAM_CC_ICP_CTI_CLK 25 +#define CAM_CC_ICP_TS_CLK 26 +#define CAM_CC_IFE_0_AXI_CLK 27 +#define CAM_CC_IFE_0_CLK 28 +#define CAM_CC_IFE_0_CLK_SRC 29 +#define CAM_CC_IFE_0_CPHY_RX_CLK 30 +#define CAM_CC_IFE_0_CSID_CLK 31 +#define CAM_CC_IFE_0_CSID_CLK_SRC 32 +#define CAM_CC_IFE_0_DSP_CLK 33 +#define CAM_CC_IFE_1_AXI_CLK 34 +#define CAM_CC_IFE_1_CLK 35 +#define CAM_CC_IFE_1_CLK_SRC 36 +#define CAM_CC_IFE_1_CPHY_RX_CLK 37 +#define CAM_CC_IFE_1_CSID_CLK 38 +#define CAM_CC_IFE_1_CSID_CLK_SRC 39 +#define CAM_CC_IFE_1_DSP_CLK 40 +#define CAM_CC_IFE_LITE_CLK 41 +#define CAM_CC_IFE_LITE_CLK_SRC 42 +#define CAM_CC_IFE_LITE_CPHY_RX_CLK 43 +#define CAM_CC_IFE_LITE_CSID_CLK 44 +#define CAM_CC_IFE_LITE_CSID_CLK_SRC 45 +#define CAM_CC_IPE_0_AHB_CLK 46 +#define CAM_CC_IPE_0_AREG_CLK 47 +#define CAM_CC_IPE_0_AXI_CLK 48 +#define CAM_CC_IPE_0_CLK 49 +#define CAM_CC_IPE_0_CLK_SRC 50 +#define CAM_CC_JPEG_CLK 51 +#define CAM_CC_JPEG_CLK_SRC 52 +#define CAM_CC_LRME_CLK 53 +#define CAM_CC_LRME_CLK_SRC 54 +#define CAM_CC_MCLK0_CLK 55 +#define CAM_CC_MCLK0_CLK_SRC 56 +#define CAM_CC_MCLK1_CLK 57 +#define CAM_CC_MCLK1_CLK_SRC 58 +#define CAM_CC_MCLK2_CLK 59 +#define CAM_CC_MCLK2_CLK_SRC 60 +#define CAM_CC_MCLK3_CLK 61 +#define CAM_CC_MCLK3_CLK_SRC 62 +#define CAM_CC_PLL0 63 +#define CAM_CC_PLL1 64 +#define CAM_CC_PLL2 65 +#define CAM_CC_PLL2_OUT_AUX2 66 +#define CAM_CC_PLL3 67 +#define CAM_CC_SLOW_AHB_CLK_SRC 68 +#define CAM_CC_SOC_AHB_CLK 69 +#define CAM_CC_SYS_TMR_CLK 70 + +/* CAM_CC power domains */ +#define BPS_GDSC 0 +#define IFE_0_GDSC 1 +#define IFE_1_GDSC 2 +#define IPE_0_GDSC 3 +#define TITAN_TOP_GDSC 4 + +/* CAM_CC resets */ +#define CAM_CC_BPS_BCR 0 +#define CAM_CC_CAMNOC_BCR 1 +#define CAM_CC_CCI_BCR 2 +#define CAM_CC_CPAS_BCR 3 +#define CAM_CC_CSI0PHY_BCR 4 +#define CAM_CC_CSI1PHY_BCR 5 +#define CAM_CC_CSI2PHY_BCR 6 +#define CAM_CC_ICP_BCR 7 +#define CAM_CC_IFE_0_BCR 8 +#define CAM_CC_IFE_1_BCR 9 +#define CAM_CC_IFE_LITE_BCR 10 +#define CAM_CC_IPE_0_BCR 11 +#define CAM_CC_JPEG_BCR 12 +#define CAM_CC_LRME_BCR 13 +#define CAM_CC_MCLK0_BCR 14 +#define CAM_CC_MCLK1_BCR 15 +#define CAM_CC_MCLK2_BCR 16 +#define CAM_CC_MCLK3_BCR 17 +#define CAM_CC_TITAN_TOP_BCR 18 + +#endif diff --git a/include/dt-bindings/clock/qcom,qcs615-dispcc.h b/include/dt-bindings/clock/qcom,qcs615-dispcc.h new file mode 100644 index 000000000000..9a29945c5762 --- /dev/null +++ b/include/dt-bindings/clock/qcom,qcs615-dispcc.h @@ -0,0 +1,52 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_DISP_CC_QCS615_H +#define _DT_BINDINGS_CLK_QCOM_DISP_CC_QCS615_H + +/* DISP_CC clocks */ +#define DISP_CC_MDSS_AHB_CLK 0 +#define DISP_CC_MDSS_AHB_CLK_SRC 1 +#define DISP_CC_MDSS_BYTE0_CLK 2 +#define DISP_CC_MDSS_BYTE0_CLK_SRC 3 +#define DISP_CC_MDSS_BYTE0_DIV_CLK_SRC 4 +#define DISP_CC_MDSS_BYTE0_INTF_CLK 5 +#define DISP_CC_MDSS_DP_AUX_CLK 6 +#define DISP_CC_MDSS_DP_AUX_CLK_SRC 7 +#define DISP_CC_MDSS_DP_CRYPTO_CLK 8 +#define DISP_CC_MDSS_DP_CRYPTO_CLK_SRC 9 +#define DISP_CC_MDSS_DP_LINK_CLK 10 +#define DISP_CC_MDSS_DP_LINK_CLK_SRC 11 +#define DISP_CC_MDSS_DP_LINK_DIV_CLK_SRC 12 +#define DISP_CC_MDSS_DP_LINK_INTF_CLK 13 +#define DISP_CC_MDSS_DP_PIXEL1_CLK 14 +#define DISP_CC_MDSS_DP_PIXEL1_CLK_SRC 15 +#define DISP_CC_MDSS_DP_PIXEL_CLK 16 +#define DISP_CC_MDSS_DP_PIXEL_CLK_SRC 17 +#define DISP_CC_MDSS_ESC0_CLK 18 +#define DISP_CC_MDSS_ESC0_CLK_SRC 19 +#define DISP_CC_MDSS_MDP_CLK 20 +#define DISP_CC_MDSS_MDP_CLK_SRC 21 +#define DISP_CC_MDSS_MDP_LUT_CLK 22 +#define DISP_CC_MDSS_NON_GDSC_AHB_CLK 23 +#define DISP_CC_MDSS_PCLK0_CLK 24 +#define DISP_CC_MDSS_PCLK0_CLK_SRC 25 +#define DISP_CC_MDSS_ROT_CLK 26 +#define DISP_CC_MDSS_ROT_CLK_SRC 27 +#define DISP_CC_MDSS_RSCC_AHB_CLK 28 +#define DISP_CC_MDSS_RSCC_VSYNC_CLK 29 +#define DISP_CC_MDSS_VSYNC_CLK 30 +#define DISP_CC_MDSS_VSYNC_CLK_SRC 31 +#define DISP_CC_PLL0 32 +#define DISP_CC_XO_CLK 33 + +/* DISP_CC power domains */ +#define MDSS_CORE_GDSC 0 + +/* DISP_CC resets */ +#define DISP_CC_MDSS_CORE_BCR 0 +#define DISP_CC_MDSS_RSCC_BCR 1 + +#endif diff --git a/include/dt-bindings/clock/qcom,qcs615-gpucc.h b/include/dt-bindings/clock/qcom,qcs615-gpucc.h new file mode 100644 index 000000000000..6d8394b90d59 --- /dev/null +++ b/include/dt-bindings/clock/qcom,qcs615-gpucc.h @@ -0,0 +1,39 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_GPU_CC_QCS615_H +#define _DT_BINDINGS_CLK_QCOM_GPU_CC_QCS615_H + +/* GPU_CC clocks */ +#define CRC_DIV_PLL0 0 +#define CRC_DIV_PLL1 1 +#define GPU_CC_PLL0 2 +#define GPU_CC_PLL1 3 +#define GPU_CC_CRC_AHB_CLK 4 +#define GPU_CC_CX_GFX3D_CLK 5 +#define GPU_CC_CX_GFX3D_SLV_CLK 6 +#define GPU_CC_CX_GMU_CLK 7 +#define GPU_CC_CX_SNOC_DVM_CLK 8 +#define GPU_CC_CXO_AON_CLK 9 +#define GPU_CC_CXO_CLK 10 +#define GPU_CC_GMU_CLK_SRC 11 +#define GPU_CC_GX_GFX3D_CLK 12 +#define GPU_CC_GX_GFX3D_CLK_SRC 13 +#define GPU_CC_GX_GMU_CLK 14 +#define GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK 15 +#define GPU_CC_SLEEP_CLK 16 + +/* GPU_CC power domains */ +#define CX_GDSC 0 +#define GX_GDSC 1 + +/* GPU_CC resets */ +#define GPU_CC_CX_BCR 0 +#define GPU_CC_GFX3D_AON_BCR 1 +#define GPU_CC_GMU_BCR 2 +#define GPU_CC_GX_BCR 3 +#define GPU_CC_XO_BCR 4 + +#endif diff --git a/include/dt-bindings/clock/qcom,qcs615-videocc.h b/include/dt-bindings/clock/qcom,qcs615-videocc.h new file mode 100644 index 000000000000..0ca3efb21103 --- /dev/null +++ b/include/dt-bindings/clock/qcom,qcs615-videocc.h @@ -0,0 +1,30 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_VIDEO_CC_QCS615_H +#define _DT_BINDINGS_CLK_QCOM_VIDEO_CC_QCS615_H + +/* VIDEO_CC clocks */ +#define VIDEO_CC_SLEEP_CLK 0 +#define VIDEO_CC_SLEEP_CLK_SRC 1 +#define VIDEO_CC_VCODEC0_AXI_CLK 2 +#define VIDEO_CC_VCODEC0_CORE_CLK 3 +#define VIDEO_CC_VENUS_AHB_CLK 4 +#define VIDEO_CC_VENUS_CLK_SRC 5 +#define VIDEO_CC_VENUS_CTL_AXI_CLK 6 +#define VIDEO_CC_VENUS_CTL_CORE_CLK 7 +#define VIDEO_CC_XO_CLK 8 +#define VIDEO_PLL0 9 + +/* VIDEO_CC power domains */ +#define VCODEC0_GDSC 0 +#define VENUS_GDSC 1 + +/* VIDEO_CC resets */ +#define VIDEO_CC_INTERFACE_BCR 0 +#define VIDEO_CC_VCODEC0_BCR 1 +#define VIDEO_CC_VENUS_BCR 2 + +#endif diff --git a/include/dt-bindings/clock/qcom,qcs8300-camcc.h b/include/dt-bindings/clock/qcom,qcs8300-camcc.h new file mode 100644 index 000000000000..fc535c847859 --- /dev/null +++ b/include/dt-bindings/clock/qcom,qcs8300-camcc.h @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_QCS8300_CAM_CC_H +#define _DT_BINDINGS_CLK_QCOM_QCS8300_CAM_CC_H + +#include "qcom,sa8775p-camcc.h" + +/* QCS8300 introduces below new clocks compared to SA8775P */ + +/* CAM_CC clocks */ +#define CAM_CC_TITAN_TOP_ACCU_SHIFT_CLK 86 + +#endif diff --git a/include/dt-bindings/clock/qcom,qcs8300-gpucc.h b/include/dt-bindings/clock/qcom,qcs8300-gpucc.h new file mode 100644 index 000000000000..afa187467b4c --- /dev/null +++ b/include/dt-bindings/clock/qcom,qcs8300-gpucc.h @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_GPUCC_QCS8300_H +#define _DT_BINDINGS_CLK_QCOM_GPUCC_QCS8300_H + +#include "qcom,sa8775p-gpucc.h" + +/* QCS8300 introduces below new clocks compared to SA8775P */ + +/* GPU_CC clocks */ +#define GPU_CC_CX_ACCU_SHIFT_CLK 23 +#define GPU_CC_GX_ACCU_SHIFT_CLK 24 + +#endif diff --git a/include/dt-bindings/clock/qcom,rpmcc.h b/include/dt-bindings/clock/qcom,rpmcc.h index 46309c9953b2..1477a75e7f6d 100644 --- a/include/dt-bindings/clock/qcom,rpmcc.h +++ b/include/dt-bindings/clock/qcom,rpmcc.h @@ -170,5 +170,9 @@ #define RPM_SMD_BIMC_FREQ_LOG 124 #define RPM_SMD_LN_BB_CLK_PIN 125 #define RPM_SMD_LN_BB_A_CLK_PIN 126 +#define RPM_SMD_BB_CLK3 127 +#define RPM_SMD_BB_CLK3_A 128 +#define RPM_SMD_BB_CLK3_PIN 129 +#define RPM_SMD_BB_CLK3_A_PIN 130 #endif diff --git a/include/dt-bindings/clock/qcom,sc8180x-camcc.h b/include/dt-bindings/clock/qcom,sc8180x-camcc.h new file mode 100644 index 000000000000..3e57b80f65e8 --- /dev/null +++ b/include/dt-bindings/clock/qcom,sc8180x-camcc.h @@ -0,0 +1,181 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) 2025, Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_CAM_CC_SC8180X_H +#define _DT_BINDINGS_CLK_QCOM_CAM_CC_SC8180X_H + +/* CAM_CC clocks */ +#define CAM_CC_BPS_AHB_CLK 0 +#define CAM_CC_BPS_AREG_CLK 1 +#define CAM_CC_BPS_AXI_CLK 2 +#define CAM_CC_BPS_CLK 3 +#define CAM_CC_BPS_CLK_SRC 4 +#define CAM_CC_CAMNOC_AXI_CLK 5 +#define CAM_CC_CAMNOC_AXI_CLK_SRC 6 +#define CAM_CC_CAMNOC_DCD_XO_CLK 7 +#define CAM_CC_CCI_0_CLK 8 +#define CAM_CC_CCI_0_CLK_SRC 9 +#define CAM_CC_CCI_1_CLK 10 +#define CAM_CC_CCI_1_CLK_SRC 11 +#define CAM_CC_CCI_2_CLK 12 +#define CAM_CC_CCI_2_CLK_SRC 13 +#define CAM_CC_CCI_3_CLK 14 +#define CAM_CC_CCI_3_CLK_SRC 15 +#define CAM_CC_CORE_AHB_CLK 16 +#define CAM_CC_CPAS_AHB_CLK 17 +#define CAM_CC_CPHY_RX_CLK_SRC 18 +#define CAM_CC_CSI0PHYTIMER_CLK 19 +#define CAM_CC_CSI0PHYTIMER_CLK_SRC 20 +#define CAM_CC_CSI1PHYTIMER_CLK 21 +#define CAM_CC_CSI1PHYTIMER_CLK_SRC 22 +#define CAM_CC_CSI2PHYTIMER_CLK 23 +#define CAM_CC_CSI2PHYTIMER_CLK_SRC 24 +#define CAM_CC_CSI3PHYTIMER_CLK 25 +#define CAM_CC_CSI3PHYTIMER_CLK_SRC 26 +#define CAM_CC_CSIPHY0_CLK 27 +#define CAM_CC_CSIPHY1_CLK 28 +#define CAM_CC_CSIPHY2_CLK 29 +#define CAM_CC_CSIPHY3_CLK 30 +#define CAM_CC_FAST_AHB_CLK_SRC 31 +#define CAM_CC_FD_CORE_CLK 32 +#define CAM_CC_FD_CORE_CLK_SRC 33 +#define CAM_CC_FD_CORE_UAR_CLK 34 +#define CAM_CC_ICP_AHB_CLK 35 +#define CAM_CC_ICP_CLK 36 +#define CAM_CC_ICP_CLK_SRC 37 +#define CAM_CC_IFE_0_AXI_CLK 38 +#define CAM_CC_IFE_0_CLK 39 +#define CAM_CC_IFE_0_CLK_SRC 40 +#define CAM_CC_IFE_0_CPHY_RX_CLK 41 +#define CAM_CC_IFE_0_CSID_CLK 42 +#define CAM_CC_IFE_0_CSID_CLK_SRC 43 +#define CAM_CC_IFE_0_DSP_CLK 44 +#define CAM_CC_IFE_1_AXI_CLK 45 +#define CAM_CC_IFE_1_CLK 46 +#define CAM_CC_IFE_1_CLK_SRC 47 +#define CAM_CC_IFE_1_CPHY_RX_CLK 48 +#define CAM_CC_IFE_1_CSID_CLK 49 +#define CAM_CC_IFE_1_CSID_CLK_SRC 50 +#define CAM_CC_IFE_1_DSP_CLK 51 +#define CAM_CC_IFE_2_AXI_CLK 52 +#define CAM_CC_IFE_2_CLK 53 +#define CAM_CC_IFE_2_CLK_SRC 54 +#define CAM_CC_IFE_2_CPHY_RX_CLK 55 +#define CAM_CC_IFE_2_CSID_CLK 56 +#define CAM_CC_IFE_2_CSID_CLK_SRC 57 +#define CAM_CC_IFE_2_DSP_CLK 58 +#define CAM_CC_IFE_3_AXI_CLK 59 +#define CAM_CC_IFE_3_CLK 60 +#define CAM_CC_IFE_3_CLK_SRC 61 +#define CAM_CC_IFE_3_CPHY_RX_CLK 62 +#define CAM_CC_IFE_3_CSID_CLK 63 +#define CAM_CC_IFE_3_CSID_CLK_SRC 64 +#define CAM_CC_IFE_3_DSP_CLK 65 +#define CAM_CC_IFE_LITE_0_CLK 66 +#define CAM_CC_IFE_LITE_0_CLK_SRC 67 +#define CAM_CC_IFE_LITE_0_CPHY_RX_CLK 68 +#define CAM_CC_IFE_LITE_0_CSID_CLK 69 +#define CAM_CC_IFE_LITE_0_CSID_CLK_SRC 70 +#define CAM_CC_IFE_LITE_1_CLK 71 +#define CAM_CC_IFE_LITE_1_CLK_SRC 72 +#define CAM_CC_IFE_LITE_1_CPHY_RX_CLK 73 +#define CAM_CC_IFE_LITE_1_CSID_CLK 74 +#define CAM_CC_IFE_LITE_1_CSID_CLK_SRC 75 +#define CAM_CC_IFE_LITE_2_CLK 76 +#define CAM_CC_IFE_LITE_2_CLK_SRC 77 +#define CAM_CC_IFE_LITE_2_CPHY_RX_CLK 78 +#define CAM_CC_IFE_LITE_2_CSID_CLK 79 +#define CAM_CC_IFE_LITE_2_CSID_CLK_SRC 80 +#define CAM_CC_IFE_LITE_3_CLK 81 +#define CAM_CC_IFE_LITE_3_CLK_SRC 82 +#define CAM_CC_IFE_LITE_3_CPHY_RX_CLK 83 +#define CAM_CC_IFE_LITE_3_CSID_CLK 84 +#define CAM_CC_IFE_LITE_3_CSID_CLK_SRC 85 +#define CAM_CC_IPE_0_AHB_CLK 86 +#define CAM_CC_IPE_0_AREG_CLK 87 +#define CAM_CC_IPE_0_AXI_CLK 88 +#define CAM_CC_IPE_0_CLK 89 +#define CAM_CC_IPE_0_CLK_SRC 90 +#define CAM_CC_IPE_1_AHB_CLK 91 +#define CAM_CC_IPE_1_AREG_CLK 92 +#define CAM_CC_IPE_1_AXI_CLK 93 +#define CAM_CC_IPE_1_CLK 94 +#define CAM_CC_JPEG_CLK 95 +#define CAM_CC_JPEG_CLK_SRC 96 +#define CAM_CC_LRME_CLK 97 +#define CAM_CC_LRME_CLK_SRC 98 +#define CAM_CC_MCLK0_CLK 99 +#define CAM_CC_MCLK0_CLK_SRC 100 +#define CAM_CC_MCLK1_CLK 101 +#define CAM_CC_MCLK1_CLK_SRC 102 +#define CAM_CC_MCLK2_CLK 103 +#define CAM_CC_MCLK2_CLK_SRC 104 +#define CAM_CC_MCLK3_CLK 105 +#define CAM_CC_MCLK3_CLK_SRC 106 +#define CAM_CC_MCLK4_CLK 107 +#define CAM_CC_MCLK4_CLK_SRC 108 +#define CAM_CC_MCLK5_CLK 109 +#define CAM_CC_MCLK5_CLK_SRC 110 +#define CAM_CC_MCLK6_CLK 111 +#define CAM_CC_MCLK6_CLK_SRC 112 +#define CAM_CC_MCLK7_CLK 113 +#define CAM_CC_MCLK7_CLK_SRC 114 +#define CAM_CC_PLL0 115 +#define CAM_CC_PLL0_OUT_EVEN 116 +#define CAM_CC_PLL0_OUT_ODD 117 +#define CAM_CC_PLL1 118 +#define CAM_CC_PLL2 119 +#define CAM_CC_PLL2_OUT_MAIN 120 +#define CAM_CC_PLL3 121 +#define CAM_CC_PLL4 122 +#define CAM_CC_PLL5 123 +#define CAM_CC_PLL6 124 +#define CAM_CC_SLOW_AHB_CLK_SRC 125 +#define CAM_CC_XO_CLK_SRC 126 + + +/* CAM_CC power domains */ +#define BPS_GDSC 0 +#define IFE_0_GDSC 1 +#define IFE_1_GDSC 2 +#define IFE_2_GDSC 3 +#define IFE_3_GDSC 4 +#define IPE_0_GDSC 5 +#define IPE_1_GDSC 6 +#define TITAN_TOP_GDSC 7 + +/* CAM_CC resets */ +#define CAM_CC_BPS_BCR 0 +#define CAM_CC_CAMNOC_BCR 1 +#define CAM_CC_CCI_BCR 2 +#define CAM_CC_CPAS_BCR 3 +#define CAM_CC_CSI0PHY_BCR 4 +#define CAM_CC_CSI1PHY_BCR 5 +#define CAM_CC_CSI2PHY_BCR 6 +#define CAM_CC_CSI3PHY_BCR 7 +#define CAM_CC_FD_BCR 8 +#define CAM_CC_ICP_BCR 9 +#define CAM_CC_IFE_0_BCR 10 +#define CAM_CC_IFE_1_BCR 11 +#define CAM_CC_IFE_2_BCR 12 +#define CAM_CC_IFE_3_BCR 13 +#define CAM_CC_IFE_LITE_0_BCR 14 +#define CAM_CC_IFE_LITE_1_BCR 15 +#define CAM_CC_IFE_LITE_2_BCR 16 +#define CAM_CC_IFE_LITE_3_BCR 17 +#define CAM_CC_IPE_0_BCR 18 +#define CAM_CC_IPE_1_BCR 19 +#define CAM_CC_JPEG_BCR 20 +#define CAM_CC_LRME_BCR 21 +#define CAM_CC_MCLK0_BCR 22 +#define CAM_CC_MCLK1_BCR 23 +#define CAM_CC_MCLK2_BCR 24 +#define CAM_CC_MCLK3_BCR 25 +#define CAM_CC_MCLK4_BCR 26 +#define CAM_CC_MCLK5_BCR 27 +#define CAM_CC_MCLK6_BCR 28 +#define CAM_CC_MCLK7_BCR 29 + +#endif diff --git a/include/dt-bindings/clock/qcom,sm6350-videocc.h b/include/dt-bindings/clock/qcom,sm6350-videocc.h new file mode 100644 index 000000000000..2af7f91fa023 --- /dev/null +++ b/include/dt-bindings/clock/qcom,sm6350-videocc.h @@ -0,0 +1,27 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) 2021, The Linux Foundation. All rights reserved. + * Copyright (c) 2021, Konrad Dybcio <konrad.dybcio@somainline.org> + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_VIDEO_CC_SM6350_H +#define _DT_BINDINGS_CLK_QCOM_VIDEO_CC_SM6350_H + +/* VIDEO_CC clocks */ +#define VIDEO_PLL0 0 +#define VIDEO_PLL0_OUT_EVEN 1 +#define VIDEO_CC_IRIS_AHB_CLK 2 +#define VIDEO_CC_IRIS_CLK_SRC 3 +#define VIDEO_CC_MVS0_AXI_CLK 4 +#define VIDEO_CC_MVS0_CORE_CLK 5 +#define VIDEO_CC_MVSC_CORE_CLK 6 +#define VIDEO_CC_MVSC_CTL_AXI_CLK 7 +#define VIDEO_CC_SLEEP_CLK 8 +#define VIDEO_CC_SLEEP_CLK_SRC 9 +#define VIDEO_CC_VENUS_AHB_CLK 10 + +/* GDSCs */ +#define MVSC_GDSC 0 +#define MVS0_GDSC 1 + +#endif diff --git a/include/dt-bindings/clock/qcom,x1e80100-gcc.h b/include/dt-bindings/clock/qcom,x1e80100-gcc.h index 24ba9e2a5cf6..710c340f24a5 100644 --- a/include/dt-bindings/clock/qcom,x1e80100-gcc.h +++ b/include/dt-bindings/clock/qcom,x1e80100-gcc.h @@ -482,4 +482,6 @@ #define GCC_USB_1_PHY_BCR 85 #define GCC_USB_2_PHY_BCR 86 #define GCC_VIDEO_BCR 87 +#define GCC_VIDEO_AXI0_CLK_ARES 88 +#define GCC_VIDEO_AXI1_CLK_ARES 89 #endif diff --git a/include/dt-bindings/clock/r9a07g043-cpg.h b/include/dt-bindings/clock/r9a07g043-cpg.h index 131993343777..e1f65f1928cf 100644 --- a/include/dt-bindings/clock/r9a07g043-cpg.h +++ b/include/dt-bindings/clock/r9a07g043-cpg.h @@ -200,57 +200,4 @@ #define R9A07G043_AX45MP_CORE0_RESETN 78 /* RZ/Five Only */ #define R9A07G043_IAX45_RESETN 79 /* RZ/Five Only */ -/* Power domain IDs. */ -#define R9A07G043_PD_ALWAYS_ON 0 -#define R9A07G043_PD_GIC 1 /* RZ/G2UL Only */ -#define R9A07G043_PD_IA55 2 /* RZ/G2UL Only */ -#define R9A07G043_PD_MHU 3 /* RZ/G2UL Only */ -#define R9A07G043_PD_CORESIGHT 4 /* RZ/G2UL Only */ -#define R9A07G043_PD_SYC 5 /* RZ/G2UL Only */ -#define R9A07G043_PD_DMAC 6 -#define R9A07G043_PD_GTM0 7 -#define R9A07G043_PD_GTM1 8 -#define R9A07G043_PD_GTM2 9 -#define R9A07G043_PD_MTU 10 -#define R9A07G043_PD_POE3 11 -#define R9A07G043_PD_WDT0 12 -#define R9A07G043_PD_SPI 13 -#define R9A07G043_PD_SDHI0 14 -#define R9A07G043_PD_SDHI1 15 -#define R9A07G043_PD_ISU 16 /* RZ/G2UL Only */ -#define R9A07G043_PD_CRU 17 /* RZ/G2UL Only */ -#define R9A07G043_PD_LCDC 18 /* RZ/G2UL Only */ -#define R9A07G043_PD_SSI0 19 -#define R9A07G043_PD_SSI1 20 -#define R9A07G043_PD_SSI2 21 -#define R9A07G043_PD_SSI3 22 -#define R9A07G043_PD_SRC 23 -#define R9A07G043_PD_USB0 24 -#define R9A07G043_PD_USB1 25 -#define R9A07G043_PD_USB_PHY 26 -#define R9A07G043_PD_ETHER0 27 -#define R9A07G043_PD_ETHER1 28 -#define R9A07G043_PD_I2C0 29 -#define R9A07G043_PD_I2C1 30 -#define R9A07G043_PD_I2C2 31 -#define R9A07G043_PD_I2C3 32 -#define R9A07G043_PD_SCIF0 33 -#define R9A07G043_PD_SCIF1 34 -#define R9A07G043_PD_SCIF2 35 -#define R9A07G043_PD_SCIF3 36 -#define R9A07G043_PD_SCIF4 37 -#define R9A07G043_PD_SCI0 38 -#define R9A07G043_PD_SCI1 39 -#define R9A07G043_PD_IRDA 40 -#define R9A07G043_PD_RSPI0 41 -#define R9A07G043_PD_RSPI1 42 -#define R9A07G043_PD_RSPI2 43 -#define R9A07G043_PD_CANFD 44 -#define R9A07G043_PD_ADC 45 -#define R9A07G043_PD_TSU 46 -#define R9A07G043_PD_PLIC 47 /* RZ/Five Only */ -#define R9A07G043_PD_IAX45 48 /* RZ/Five Only */ -#define R9A07G043_PD_NCEPLDM 49 /* RZ/Five Only */ -#define R9A07G043_PD_NCEPLMT 50 /* RZ/Five Only */ - #endif /* __DT_BINDINGS_CLOCK_R9A07G043_CPG_H__ */ diff --git a/include/dt-bindings/clock/r9a07g044-cpg.h b/include/dt-bindings/clock/r9a07g044-cpg.h index e209f96f92b7..0bb17ff1a01a 100644 --- a/include/dt-bindings/clock/r9a07g044-cpg.h +++ b/include/dt-bindings/clock/r9a07g044-cpg.h @@ -217,62 +217,4 @@ #define R9A07G044_ADC_ADRST_N 82 #define R9A07G044_TSU_PRESETN 83 -/* Power domain IDs. */ -#define R9A07G044_PD_ALWAYS_ON 0 -#define R9A07G044_PD_GIC 1 -#define R9A07G044_PD_IA55 2 -#define R9A07G044_PD_MHU 3 -#define R9A07G044_PD_CORESIGHT 4 -#define R9A07G044_PD_SYC 5 -#define R9A07G044_PD_DMAC 6 -#define R9A07G044_PD_GTM0 7 -#define R9A07G044_PD_GTM1 8 -#define R9A07G044_PD_GTM2 9 -#define R9A07G044_PD_MTU 10 -#define R9A07G044_PD_POE3 11 -#define R9A07G044_PD_GPT 12 -#define R9A07G044_PD_POEGA 13 -#define R9A07G044_PD_POEGB 14 -#define R9A07G044_PD_POEGC 15 -#define R9A07G044_PD_POEGD 16 -#define R9A07G044_PD_WDT0 17 -#define R9A07G044_PD_WDT1 18 -#define R9A07G044_PD_SPI 19 -#define R9A07G044_PD_SDHI0 20 -#define R9A07G044_PD_SDHI1 21 -#define R9A07G044_PD_3DGE 22 -#define R9A07G044_PD_ISU 23 -#define R9A07G044_PD_VCPL4 24 -#define R9A07G044_PD_CRU 25 -#define R9A07G044_PD_MIPI_DSI 26 -#define R9A07G044_PD_LCDC 27 -#define R9A07G044_PD_SSI0 28 -#define R9A07G044_PD_SSI1 29 -#define R9A07G044_PD_SSI2 30 -#define R9A07G044_PD_SSI3 31 -#define R9A07G044_PD_SRC 32 -#define R9A07G044_PD_USB0 33 -#define R9A07G044_PD_USB1 34 -#define R9A07G044_PD_USB_PHY 35 -#define R9A07G044_PD_ETHER0 36 -#define R9A07G044_PD_ETHER1 37 -#define R9A07G044_PD_I2C0 38 -#define R9A07G044_PD_I2C1 39 -#define R9A07G044_PD_I2C2 40 -#define R9A07G044_PD_I2C3 41 -#define R9A07G044_PD_SCIF0 42 -#define R9A07G044_PD_SCIF1 43 -#define R9A07G044_PD_SCIF2 44 -#define R9A07G044_PD_SCIF3 45 -#define R9A07G044_PD_SCIF4 46 -#define R9A07G044_PD_SCI0 47 -#define R9A07G044_PD_SCI1 48 -#define R9A07G044_PD_IRDA 49 -#define R9A07G044_PD_RSPI0 50 -#define R9A07G044_PD_RSPI1 51 -#define R9A07G044_PD_RSPI2 52 -#define R9A07G044_PD_CANFD 53 -#define R9A07G044_PD_ADC 54 -#define R9A07G044_PD_TSU 55 - #endif /* __DT_BINDINGS_CLOCK_R9A07G044_CPG_H__ */ diff --git a/include/dt-bindings/clock/r9a07g054-cpg.h b/include/dt-bindings/clock/r9a07g054-cpg.h index 2c99f89397c4..43f4dbda872c 100644 --- a/include/dt-bindings/clock/r9a07g054-cpg.h +++ b/include/dt-bindings/clock/r9a07g054-cpg.h @@ -226,62 +226,4 @@ #define R9A07G054_TSU_PRESETN 83 #define R9A07G054_STPAI_ARESETN 84 -/* Power domain IDs. */ -#define R9A07G054_PD_ALWAYS_ON 0 -#define R9A07G054_PD_GIC 1 -#define R9A07G054_PD_IA55 2 -#define R9A07G054_PD_MHU 3 -#define R9A07G054_PD_CORESIGHT 4 -#define R9A07G054_PD_SYC 5 -#define R9A07G054_PD_DMAC 6 -#define R9A07G054_PD_GTM0 7 -#define R9A07G054_PD_GTM1 8 -#define R9A07G054_PD_GTM2 9 -#define R9A07G054_PD_MTU 10 -#define R9A07G054_PD_POE3 11 -#define R9A07G054_PD_GPT 12 -#define R9A07G054_PD_POEGA 13 -#define R9A07G054_PD_POEGB 14 -#define R9A07G054_PD_POEGC 15 -#define R9A07G054_PD_POEGD 16 -#define R9A07G054_PD_WDT0 17 -#define R9A07G054_PD_WDT1 18 -#define R9A07G054_PD_SPI 19 -#define R9A07G054_PD_SDHI0 20 -#define R9A07G054_PD_SDHI1 21 -#define R9A07G054_PD_3DGE 22 -#define R9A07G054_PD_ISU 23 -#define R9A07G054_PD_VCPL4 24 -#define R9A07G054_PD_CRU 25 -#define R9A07G054_PD_MIPI_DSI 26 -#define R9A07G054_PD_LCDC 27 -#define R9A07G054_PD_SSI0 28 -#define R9A07G054_PD_SSI1 29 -#define R9A07G054_PD_SSI2 30 -#define R9A07G054_PD_SSI3 31 -#define R9A07G054_PD_SRC 32 -#define R9A07G054_PD_USB0 33 -#define R9A07G054_PD_USB1 34 -#define R9A07G054_PD_USB_PHY 35 -#define R9A07G054_PD_ETHER0 36 -#define R9A07G054_PD_ETHER1 37 -#define R9A07G054_PD_I2C0 38 -#define R9A07G054_PD_I2C1 39 -#define R9A07G054_PD_I2C2 40 -#define R9A07G054_PD_I2C3 41 -#define R9A07G054_PD_SCIF0 42 -#define R9A07G054_PD_SCIF1 43 -#define R9A07G054_PD_SCIF2 44 -#define R9A07G054_PD_SCIF3 45 -#define R9A07G054_PD_SCIF4 46 -#define R9A07G054_PD_SCI0 47 -#define R9A07G054_PD_SCI1 48 -#define R9A07G054_PD_IRDA 49 -#define R9A07G054_PD_RSPI0 50 -#define R9A07G054_PD_RSPI1 51 -#define R9A07G054_PD_RSPI2 52 -#define R9A07G054_PD_CANFD 53 -#define R9A07G054_PD_ADC 54 -#define R9A07G054_PD_TSU 55 - #endif /* __DT_BINDINGS_CLOCK_R9A07G054_CPG_H__ */ diff --git a/include/dt-bindings/clock/r9a08g045-cpg.h b/include/dt-bindings/clock/r9a08g045-cpg.h index 311521fe4b59..410725b778a8 100644 --- a/include/dt-bindings/clock/r9a08g045-cpg.h +++ b/include/dt-bindings/clock/r9a08g045-cpg.h @@ -239,75 +239,4 @@ #define R9A08G045_I3C_PRESETN 92 #define R9A08G045_VBAT_BRESETN 93 -/* Power domain IDs. */ -#define R9A08G045_PD_ALWAYS_ON 0 -#define R9A08G045_PD_GIC 1 -#define R9A08G045_PD_IA55 2 -#define R9A08G045_PD_MHU 3 -#define R9A08G045_PD_CORESIGHT 4 -#define R9A08G045_PD_SYC 5 -#define R9A08G045_PD_DMAC 6 -#define R9A08G045_PD_GTM0 7 -#define R9A08G045_PD_GTM1 8 -#define R9A08G045_PD_GTM2 9 -#define R9A08G045_PD_GTM3 10 -#define R9A08G045_PD_GTM4 11 -#define R9A08G045_PD_GTM5 12 -#define R9A08G045_PD_GTM6 13 -#define R9A08G045_PD_GTM7 14 -#define R9A08G045_PD_MTU 15 -#define R9A08G045_PD_POE3 16 -#define R9A08G045_PD_GPT 17 -#define R9A08G045_PD_POEGA 18 -#define R9A08G045_PD_POEGB 19 -#define R9A08G045_PD_POEGC 20 -#define R9A08G045_PD_POEGD 21 -#define R9A08G045_PD_WDT0 22 -#define R9A08G045_PD_XSPI 23 -#define R9A08G045_PD_SDHI0 24 -#define R9A08G045_PD_SDHI1 25 -#define R9A08G045_PD_SDHI2 26 -#define R9A08G045_PD_SSI0 27 -#define R9A08G045_PD_SSI1 28 -#define R9A08G045_PD_SSI2 29 -#define R9A08G045_PD_SSI3 30 -#define R9A08G045_PD_SRC 31 -#define R9A08G045_PD_USB0 32 -#define R9A08G045_PD_USB1 33 -#define R9A08G045_PD_USB_PHY 34 -#define R9A08G045_PD_ETHER0 35 -#define R9A08G045_PD_ETHER1 36 -#define R9A08G045_PD_I2C0 37 -#define R9A08G045_PD_I2C1 38 -#define R9A08G045_PD_I2C2 39 -#define R9A08G045_PD_I2C3 40 -#define R9A08G045_PD_SCIF0 41 -#define R9A08G045_PD_SCIF1 42 -#define R9A08G045_PD_SCIF2 43 -#define R9A08G045_PD_SCIF3 44 -#define R9A08G045_PD_SCIF4 45 -#define R9A08G045_PD_SCIF5 46 -#define R9A08G045_PD_SCI0 47 -#define R9A08G045_PD_SCI1 48 -#define R9A08G045_PD_IRDA 49 -#define R9A08G045_PD_RSPI0 50 -#define R9A08G045_PD_RSPI1 51 -#define R9A08G045_PD_RSPI2 52 -#define R9A08G045_PD_RSPI3 53 -#define R9A08G045_PD_RSPI4 54 -#define R9A08G045_PD_CANFD 55 -#define R9A08G045_PD_ADC 56 -#define R9A08G045_PD_TSU 57 -#define R9A08G045_PD_OCTA 58 -#define R9A08G045_PD_PDM 59 -#define R9A08G045_PD_PCI 60 -#define R9A08G045_PD_SPDIF 61 -#define R9A08G045_PD_I3C 62 -#define R9A08G045_PD_VBAT 63 - -#define R9A08G045_PD_DDR 64 -#define R9A08G045_PD_TZCDDR 65 -#define R9A08G045_PD_OTFDE_DDR 66 -#define R9A08G045_PD_RTC 67 - #endif /* __DT_BINDINGS_CLOCK_R9A08G045_CPG_H__ */ diff --git a/include/dt-bindings/clock/raspberrypi,rp1-clocks.h b/include/dt-bindings/clock/raspberrypi,rp1-clocks.h new file mode 100644 index 000000000000..248efb895f35 --- /dev/null +++ b/include/dt-bindings/clock/raspberrypi,rp1-clocks.h @@ -0,0 +1,61 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (C) 2021 Raspberry Pi Ltd. + */ + +#ifndef __DT_BINDINGS_CLOCK_RASPBERRYPI_RP1 +#define __DT_BINDINGS_CLOCK_RASPBERRYPI_RP1 + +#define RP1_PLL_SYS_CORE 0 +#define RP1_PLL_AUDIO_CORE 1 +#define RP1_PLL_VIDEO_CORE 2 + +#define RP1_PLL_SYS 3 +#define RP1_PLL_AUDIO 4 +#define RP1_PLL_VIDEO 5 + +#define RP1_PLL_SYS_PRI_PH 6 +#define RP1_PLL_SYS_SEC_PH 7 +#define RP1_PLL_AUDIO_PRI_PH 8 + +#define RP1_PLL_SYS_SEC 9 +#define RP1_PLL_AUDIO_SEC 10 +#define RP1_PLL_VIDEO_SEC 11 + +#define RP1_CLK_SYS 12 +#define RP1_CLK_SLOW_SYS 13 +#define RP1_CLK_DMA 14 +#define RP1_CLK_UART 15 +#define RP1_CLK_ETH 16 +#define RP1_CLK_PWM0 17 +#define RP1_CLK_PWM1 18 +#define RP1_CLK_AUDIO_IN 19 +#define RP1_CLK_AUDIO_OUT 20 +#define RP1_CLK_I2S 21 +#define RP1_CLK_MIPI0_CFG 22 +#define RP1_CLK_MIPI1_CFG 23 +#define RP1_CLK_PCIE_AUX 24 +#define RP1_CLK_USBH0_MICROFRAME 25 +#define RP1_CLK_USBH1_MICROFRAME 26 +#define RP1_CLK_USBH0_SUSPEND 27 +#define RP1_CLK_USBH1_SUSPEND 28 +#define RP1_CLK_ETH_TSU 29 +#define RP1_CLK_ADC 30 +#define RP1_CLK_SDIO_TIMER 31 +#define RP1_CLK_SDIO_ALT_SRC 32 +#define RP1_CLK_GP0 33 +#define RP1_CLK_GP1 34 +#define RP1_CLK_GP2 35 +#define RP1_CLK_GP3 36 +#define RP1_CLK_GP4 37 +#define RP1_CLK_GP5 38 +#define RP1_CLK_VEC 39 +#define RP1_CLK_DPI 40 +#define RP1_CLK_MIPI0_DPI 41 +#define RP1_CLK_MIPI1_DPI 42 + +/* Extra PLL output channels - RP1B0 only */ +#define RP1_PLL_VIDEO_PRI_PH 43 +#define RP1_PLL_AUDIO_TERN 44 + +#endif diff --git a/include/dt-bindings/clock/renesas,r9a09g047-cpg.h b/include/dt-bindings/clock/renesas,r9a09g047-cpg.h index 1d031bf6bf03..a27132f9a6c8 100644 --- a/include/dt-bindings/clock/renesas,r9a09g047-cpg.h +++ b/include/dt-bindings/clock/renesas,r9a09g047-cpg.h @@ -17,5 +17,8 @@ #define R9A09G047_CM33_CLK0 6 #define R9A09G047_CST_0_SWCLKTCK 7 #define R9A09G047_IOTOP_0_SHCLK 8 +#define R9A09G047_SPI_CLK_SPI 9 +#define R9A09G047_GBETH_0_CLK_PTP_REF_I 10 +#define R9A09G047_GBETH_1_CLK_PTP_REF_I 11 #endif /* __DT_BINDINGS_CLOCK_RENESAS_R9A09G047_CPG_H__ */ diff --git a/include/dt-bindings/clock/renesas,r9a09g056-cpg.h b/include/dt-bindings/clock/renesas,r9a09g056-cpg.h new file mode 100644 index 000000000000..a9af5af9e3a1 --- /dev/null +++ b/include/dt-bindings/clock/renesas,r9a09g056-cpg.h @@ -0,0 +1,25 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) + * + * Copyright (C) 2025 Renesas Electronics Corp. + */ +#ifndef __DT_BINDINGS_CLOCK_RENESAS_R9A09G056_CPG_H__ +#define __DT_BINDINGS_CLOCK_RENESAS_R9A09G056_CPG_H__ + +#include <dt-bindings/clock/renesas-cpg-mssr.h> + +/* Core Clock list */ +#define R9A09G056_SYS_0_PCLK 0 +#define R9A09G056_CA55_0_CORE_CLK0 1 +#define R9A09G056_CA55_0_CORE_CLK1 2 +#define R9A09G056_CA55_0_CORE_CLK2 3 +#define R9A09G056_CA55_0_CORE_CLK3 4 +#define R9A09G056_CA55_0_PERIPHCLK 5 +#define R9A09G056_CM33_CLK0 6 +#define R9A09G056_CST_0_SWCLKTCK 7 +#define R9A09G056_IOTOP_0_SHCLK 8 +#define R9A09G056_USB2_0_CLK_CORE0 9 +#define R9A09G056_GBETH_0_CLK_PTP_REF_I 10 +#define R9A09G056_GBETH_1_CLK_PTP_REF_I 11 +#define R9A09G056_SPI_CLK_SPI 12 + +#endif /* __DT_BINDINGS_CLOCK_RENESAS_R9A09G056_CPG_H__ */ diff --git a/include/dt-bindings/clock/renesas,r9a09g057-cpg.h b/include/dt-bindings/clock/renesas,r9a09g057-cpg.h index 541e6d719bd6..5346a898ab60 100644 --- a/include/dt-bindings/clock/renesas,r9a09g057-cpg.h +++ b/include/dt-bindings/clock/renesas,r9a09g057-cpg.h @@ -17,5 +17,10 @@ #define R9A09G057_CM33_CLK0 6 #define R9A09G057_CST_0_SWCLKTCK 7 #define R9A09G057_IOTOP_0_SHCLK 8 +#define R9A09G057_USB2_0_CLK_CORE0 9 +#define R9A09G057_USB2_0_CLK_CORE1 10 +#define R9A09G057_GBETH_0_CLK_PTP_REF_I 11 +#define R9A09G057_GBETH_1_CLK_PTP_REF_I 12 +#define R9A09G057_SPI_CLK_SPI 13 #endif /* __DT_BINDINGS_CLOCK_RENESAS_R9A09G057_CPG_H__ */ diff --git a/include/dt-bindings/clock/renesas,r9a09g077-cpg-mssr.h b/include/dt-bindings/clock/renesas,r9a09g077-cpg-mssr.h new file mode 100644 index 000000000000..7ecc4f0b235a --- /dev/null +++ b/include/dt-bindings/clock/renesas,r9a09g077-cpg-mssr.h @@ -0,0 +1,29 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) + * + * Copyright (C) 2025 Renesas Electronics Corp. + */ + +#ifndef __DT_BINDINGS_CLOCK_RENESAS_R9A09G077_CPG_H__ +#define __DT_BINDINGS_CLOCK_RENESAS_R9A09G077_CPG_H__ + +#include <dt-bindings/clock/renesas-cpg-mssr.h> + +/* R9A09G077 CPG Core Clocks */ +#define R9A09G077_CLK_CA55C0 0 +#define R9A09G077_CLK_CA55C1 1 +#define R9A09G077_CLK_CA55C2 2 +#define R9A09G077_CLK_CA55C3 3 +#define R9A09G077_CLK_CA55S 4 +#define R9A09G077_CLK_CR52_CPU0 5 +#define R9A09G077_CLK_CR52_CPU1 6 +#define R9A09G077_CLK_CKIO 7 +#define R9A09G077_CLK_PCLKAH 8 +#define R9A09G077_CLK_PCLKAM 9 +#define R9A09G077_CLK_PCLKAL 10 +#define R9A09G077_CLK_PCLKGPTL 11 +#define R9A09G077_CLK_PCLKH 12 +#define R9A09G077_CLK_PCLKM 13 +#define R9A09G077_CLK_PCLKL 14 +#define R9A09G077_SDHI_CLKHS 15 + +#endif /* __DT_BINDINGS_CLOCK_RENESAS_R9A09G077_CPG_H__ */ diff --git a/include/dt-bindings/clock/renesas,r9a09g087-cpg-mssr.h b/include/dt-bindings/clock/renesas,r9a09g087-cpg-mssr.h new file mode 100644 index 000000000000..925e57703925 --- /dev/null +++ b/include/dt-bindings/clock/renesas,r9a09g087-cpg-mssr.h @@ -0,0 +1,29 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) + * + * Copyright (C) 2025 Renesas Electronics Corp. + */ + +#ifndef __DT_BINDINGS_CLOCK_RENESAS_R9A09G087_CPG_H__ +#define __DT_BINDINGS_CLOCK_RENESAS_R9A09G087_CPG_H__ + +#include <dt-bindings/clock/renesas-cpg-mssr.h> + +/* R9A09G087 CPG Core Clocks */ +#define R9A09G087_CLK_CA55C0 0 +#define R9A09G087_CLK_CA55C1 1 +#define R9A09G087_CLK_CA55C2 2 +#define R9A09G087_CLK_CA55C3 3 +#define R9A09G087_CLK_CA55S 4 +#define R9A09G087_CLK_CR52_CPU0 5 +#define R9A09G087_CLK_CR52_CPU1 6 +#define R9A09G087_CLK_CKIO 7 +#define R9A09G087_CLK_PCLKAH 8 +#define R9A09G087_CLK_PCLKAM 9 +#define R9A09G087_CLK_PCLKAL 10 +#define R9A09G087_CLK_PCLKGPTL 11 +#define R9A09G087_CLK_PCLKH 12 +#define R9A09G087_CLK_PCLKM 13 +#define R9A09G087_CLK_PCLKL 14 +#define R9A09G087_SDHI_CLKHS 15 + +#endif /* __DT_BINDINGS_CLOCK_RENESAS_R9A09G087_CPG_H__ */ diff --git a/include/dt-bindings/clock/rk3036-cru.h b/include/dt-bindings/clock/rk3036-cru.h index 99cc617e1e54..5cbc0e2b08ff 100644 --- a/include/dt-bindings/clock/rk3036-cru.h +++ b/include/dt-bindings/clock/rk3036-cru.h @@ -47,6 +47,7 @@ #define SCLK_MACREF 152 #define SCLK_MACPLL 153 #define SCLK_SFC 160 +#define SCLK_USB480M 161 /* aclk gates */ #define ACLK_DMAC2 194 diff --git a/include/dt-bindings/clock/rk3188-cru-common.h b/include/dt-bindings/clock/rk3188-cru-common.h index 01e14ab252a7..dd988cc9d582 100644 --- a/include/dt-bindings/clock/rk3188-cru-common.h +++ b/include/dt-bindings/clock/rk3188-cru-common.h @@ -103,6 +103,8 @@ #define PCLK_PERI 351 #define PCLK_DDRUPCTL 352 #define PCLK_PUBL 353 +#define PCLK_CIF0 354 +#define PCLK_CIF1 355 /* hclk gates */ #define HCLK_SDMMC 448 diff --git a/include/dt-bindings/clock/rockchip,rk3528-cru.h b/include/dt-bindings/clock/rockchip,rk3528-cru.h new file mode 100644 index 000000000000..0245a53fc334 --- /dev/null +++ b/include/dt-bindings/clock/rockchip,rk3528-cru.h @@ -0,0 +1,459 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */ +/* + * Copyright (c) 2022 Rockchip Electronics Co. Ltd. + * Copyright (c) 2024 Yao Zi <ziyao@disroot.org> + * Author: Joseph Chen <chenjh@rock-chips.com> + */ + +#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3528_H +#define _DT_BINDINGS_CLK_ROCKCHIP_RK3528_H + +/* cru-clocks indices */ +#define PLL_APLL 0 +#define PLL_CPLL 1 +#define PLL_GPLL 2 +#define PLL_PPLL 3 +#define PLL_DPLL 4 +#define ARMCLK 5 +#define XIN_OSC0_HALF 6 +#define CLK_MATRIX_50M_SRC 7 +#define CLK_MATRIX_100M_SRC 8 +#define CLK_MATRIX_150M_SRC 9 +#define CLK_MATRIX_200M_SRC 10 +#define CLK_MATRIX_250M_SRC 11 +#define CLK_MATRIX_300M_SRC 12 +#define CLK_MATRIX_339M_SRC 13 +#define CLK_MATRIX_400M_SRC 14 +#define CLK_MATRIX_500M_SRC 15 +#define CLK_MATRIX_600M_SRC 16 +#define CLK_UART0_SRC 17 +#define CLK_UART0_FRAC 18 +#define SCLK_UART0 19 +#define CLK_UART1_SRC 20 +#define CLK_UART1_FRAC 21 +#define SCLK_UART1 22 +#define CLK_UART2_SRC 23 +#define CLK_UART2_FRAC 24 +#define SCLK_UART2 25 +#define CLK_UART3_SRC 26 +#define CLK_UART3_FRAC 27 +#define SCLK_UART3 28 +#define CLK_UART4_SRC 29 +#define CLK_UART4_FRAC 30 +#define SCLK_UART4 31 +#define CLK_UART5_SRC 32 +#define CLK_UART5_FRAC 33 +#define SCLK_UART5 34 +#define CLK_UART6_SRC 35 +#define CLK_UART6_FRAC 36 +#define SCLK_UART6 37 +#define CLK_UART7_SRC 38 +#define CLK_UART7_FRAC 39 +#define SCLK_UART7 40 +#define CLK_I2S0_2CH_SRC 41 +#define CLK_I2S0_2CH_FRAC 42 +#define MCLK_I2S0_2CH_SAI_SRC 43 +#define CLK_I2S3_8CH_SRC 44 +#define CLK_I2S3_8CH_FRAC 45 +#define MCLK_I2S3_8CH_SAI_SRC 46 +#define CLK_I2S1_8CH_SRC 47 +#define CLK_I2S1_8CH_FRAC 48 +#define MCLK_I2S1_8CH_SAI_SRC 49 +#define CLK_I2S2_2CH_SRC 50 +#define CLK_I2S2_2CH_FRAC 51 +#define MCLK_I2S2_2CH_SAI_SRC 52 +#define CLK_SPDIF_SRC 53 +#define CLK_SPDIF_FRAC 54 +#define MCLK_SPDIF_SRC 55 +#define DCLK_VOP_SRC0 56 +#define DCLK_VOP_SRC1 57 +#define CLK_HSM 58 +#define CLK_CORE_SRC_ACS 59 +#define CLK_CORE_SRC_PVTMUX 60 +#define CLK_CORE_SRC 61 +#define CLK_CORE 62 +#define ACLK_M_CORE_BIU 63 +#define CLK_CORE_PVTPLL_SRC 64 +#define PCLK_DBG 65 +#define SWCLKTCK 66 +#define CLK_SCANHS_CORE 67 +#define CLK_SCANHS_ACLKM_CORE 68 +#define CLK_SCANHS_PCLK_DBG 69 +#define CLK_SCANHS_PCLK_CPU_BIU 70 +#define PCLK_CPU_ROOT 71 +#define PCLK_CORE_GRF 72 +#define PCLK_DAPLITE_BIU 73 +#define PCLK_CPU_BIU 74 +#define CLK_REF_PVTPLL_CORE 75 +#define ACLK_BUS_VOPGL_ROOT 76 +#define ACLK_BUS_VOPGL_BIU 77 +#define ACLK_BUS_H_ROOT 78 +#define ACLK_BUS_H_BIU 79 +#define ACLK_BUS_ROOT 80 +#define HCLK_BUS_ROOT 81 +#define PCLK_BUS_ROOT 82 +#define ACLK_BUS_M_ROOT 83 +#define ACLK_SYSMEM_BIU 84 +#define CLK_TIMER_ROOT 85 +#define ACLK_BUS_BIU 86 +#define HCLK_BUS_BIU 87 +#define PCLK_BUS_BIU 88 +#define PCLK_DFT2APB 89 +#define PCLK_BUS_GRF 90 +#define ACLK_BUS_M_BIU 91 +#define ACLK_GIC 92 +#define ACLK_SPINLOCK 93 +#define ACLK_DMAC 94 +#define PCLK_TIMER 95 +#define CLK_TIMER0 96 +#define CLK_TIMER1 97 +#define CLK_TIMER2 98 +#define CLK_TIMER3 99 +#define CLK_TIMER4 100 +#define CLK_TIMER5 101 +#define PCLK_JDBCK_DAP 102 +#define CLK_JDBCK_DAP 103 +#define PCLK_WDT_NS 104 +#define TCLK_WDT_NS 105 +#define HCLK_TRNG_NS 106 +#define PCLK_UART0 107 +#define PCLK_DMA2DDR 108 +#define ACLK_DMA2DDR 109 +#define PCLK_PWM0 110 +#define CLK_PWM0 111 +#define CLK_CAPTURE_PWM0 112 +#define PCLK_PWM1 113 +#define CLK_PWM1 114 +#define CLK_CAPTURE_PWM1 115 +#define PCLK_SCR 116 +#define ACLK_DCF 117 +#define PCLK_INTMUX 118 +#define CLK_PPLL_I 119 +#define CLK_PPLL_MUX 120 +#define CLK_PPLL_100M_MATRIX 121 +#define CLK_PPLL_50M_MATRIX 122 +#define CLK_REF_PCIE_INNER_PHY 123 +#define CLK_REF_PCIE_100M_PHY 124 +#define ACLK_VPU_L_ROOT 125 +#define CLK_GMAC1_VPU_25M 126 +#define CLK_PPLL_125M_MATRIX 127 +#define ACLK_VPU_ROOT 128 +#define HCLK_VPU_ROOT 129 +#define PCLK_VPU_ROOT 130 +#define ACLK_VPU_BIU 131 +#define HCLK_VPU_BIU 132 +#define PCLK_VPU_BIU 133 +#define ACLK_VPU 134 +#define HCLK_VPU 135 +#define PCLK_CRU_PCIE 136 +#define PCLK_VPU_GRF 137 +#define HCLK_SFC 138 +#define SCLK_SFC 139 +#define CCLK_SRC_EMMC 140 +#define HCLK_EMMC 141 +#define ACLK_EMMC 142 +#define BCLK_EMMC 143 +#define TCLK_EMMC 144 +#define PCLK_GPIO1 145 +#define DBCLK_GPIO1 146 +#define ACLK_VPU_L_BIU 147 +#define PCLK_VPU_IOC 148 +#define HCLK_SAI_I2S0 149 +#define MCLK_SAI_I2S0 150 +#define HCLK_SAI_I2S2 151 +#define MCLK_SAI_I2S2 152 +#define PCLK_ACODEC 153 +#define MCLK_ACODEC_TX 154 +#define PCLK_GPIO3 155 +#define DBCLK_GPIO3 156 +#define PCLK_SPI1 157 +#define CLK_SPI1 158 +#define SCLK_IN_SPI1 159 +#define PCLK_UART2 160 +#define PCLK_UART5 161 +#define PCLK_UART6 162 +#define PCLK_UART7 163 +#define PCLK_I2C3 164 +#define CLK_I2C3 165 +#define PCLK_I2C5 166 +#define CLK_I2C5 167 +#define PCLK_I2C6 168 +#define CLK_I2C6 169 +#define ACLK_MAC_VPU 170 +#define PCLK_MAC_VPU 171 +#define CLK_GMAC1_RMII_VPU 172 +#define CLK_GMAC1_SRC_VPU 173 +#define PCLK_PCIE 174 +#define CLK_PCIE_AUX 175 +#define ACLK_PCIE 176 +#define HCLK_PCIE_SLV 177 +#define HCLK_PCIE_DBI 178 +#define PCLK_PCIE_PHY 179 +#define PCLK_PIPE_GRF 180 +#define CLK_PIPE_USB3OTG_COMBO 181 +#define CLK_UTMI_USB3OTG 182 +#define CLK_PCIE_PIPE_PHY 183 +#define CCLK_SRC_SDIO0 184 +#define HCLK_SDIO0 185 +#define CCLK_SRC_SDIO1 186 +#define HCLK_SDIO1 187 +#define CLK_TS_0 188 +#define CLK_TS_1 189 +#define PCLK_CAN2 190 +#define CLK_CAN2 191 +#define PCLK_CAN3 192 +#define CLK_CAN3 193 +#define PCLK_SARADC 194 +#define CLK_SARADC 195 +#define PCLK_TSADC 196 +#define CLK_TSADC 197 +#define CLK_TSADC_TSEN 198 +#define ACLK_USB3OTG 199 +#define CLK_REF_USB3OTG 200 +#define CLK_SUSPEND_USB3OTG 201 +#define ACLK_GPU_ROOT 202 +#define PCLK_GPU_ROOT 203 +#define ACLK_GPU_BIU 204 +#define PCLK_GPU_BIU 205 +#define ACLK_GPU 206 +#define CLK_GPU_PVTPLL_SRC 207 +#define ACLK_GPU_MALI 208 +#define HCLK_RKVENC_ROOT 209 +#define ACLK_RKVENC_ROOT 210 +#define PCLK_RKVENC_ROOT 211 +#define HCLK_RKVENC_BIU 212 +#define ACLK_RKVENC_BIU 213 +#define PCLK_RKVENC_BIU 214 +#define HCLK_RKVENC 215 +#define ACLK_RKVENC 216 +#define CLK_CORE_RKVENC 217 +#define HCLK_SAI_I2S1 218 +#define MCLK_SAI_I2S1 219 +#define PCLK_I2C1 220 +#define CLK_I2C1 221 +#define PCLK_I2C0 222 +#define CLK_I2C0 223 +#define CLK_UART_JTAG 224 +#define PCLK_SPI0 225 +#define CLK_SPI0 226 +#define SCLK_IN_SPI0 227 +#define PCLK_GPIO4 228 +#define DBCLK_GPIO4 229 +#define PCLK_RKVENC_IOC 230 +#define HCLK_SPDIF 231 +#define MCLK_SPDIF 232 +#define HCLK_PDM 233 +#define MCLK_PDM 234 +#define PCLK_UART1 235 +#define PCLK_UART3 236 +#define PCLK_RKVENC_GRF 237 +#define PCLK_CAN0 238 +#define CLK_CAN0 239 +#define PCLK_CAN1 240 +#define CLK_CAN1 241 +#define ACLK_VO_ROOT 242 +#define HCLK_VO_ROOT 243 +#define PCLK_VO_ROOT 244 +#define ACLK_VO_BIU 245 +#define HCLK_VO_BIU 246 +#define PCLK_VO_BIU 247 +#define HCLK_RGA2E 248 +#define ACLK_RGA2E 249 +#define CLK_CORE_RGA2E 250 +#define HCLK_VDPP 251 +#define ACLK_VDPP 252 +#define CLK_CORE_VDPP 253 +#define PCLK_VO_GRF 254 +#define PCLK_CRU 255 +#define ACLK_VOP_ROOT 256 +#define ACLK_VOP_BIU 257 +#define HCLK_VOP 258 +#define DCLK_VOP0 259 +#define DCLK_VOP1 260 +#define ACLK_VOP 261 +#define PCLK_HDMI 262 +#define CLK_SFR_HDMI 263 +#define CLK_CEC_HDMI 264 +#define CLK_SPDIF_HDMI 265 +#define CLK_HDMIPHY_TMDSSRC 266 +#define CLK_HDMIPHY_PREP 267 +#define PCLK_HDMIPHY 268 +#define HCLK_HDCP_KEY 269 +#define ACLK_HDCP 270 +#define HCLK_HDCP 271 +#define PCLK_HDCP 272 +#define HCLK_CVBS 273 +#define DCLK_CVBS 274 +#define DCLK_4X_CVBS 275 +#define ACLK_JPEG_DECODER 276 +#define HCLK_JPEG_DECODER 277 +#define ACLK_VO_L_ROOT 278 +#define ACLK_VO_L_BIU 279 +#define ACLK_MAC_VO 280 +#define PCLK_MAC_VO 281 +#define CLK_GMAC0_SRC 282 +#define CLK_GMAC0_RMII_50M 283 +#define CLK_GMAC0_TX 284 +#define CLK_GMAC0_RX 285 +#define ACLK_JPEG_ROOT 286 +#define ACLK_JPEG_BIU 287 +#define HCLK_SAI_I2S3 288 +#define MCLK_SAI_I2S3 289 +#define CLK_MACPHY 290 +#define PCLK_VCDCPHY 291 +#define PCLK_GPIO2 292 +#define DBCLK_GPIO2 293 +#define PCLK_VO_IOC 294 +#define CCLK_SRC_SDMMC0 295 +#define HCLK_SDMMC0 296 +#define PCLK_OTPC_NS 297 +#define CLK_SBPI_OTPC_NS 298 +#define CLK_USER_OTPC_NS 299 +#define CLK_HDMIHDP0 300 +#define HCLK_USBHOST 301 +#define HCLK_USBHOST_ARB 302 +#define CLK_USBHOST_OHCI 303 +#define CLK_USBHOST_UTMI 304 +#define PCLK_UART4 305 +#define PCLK_I2C4 306 +#define CLK_I2C4 307 +#define PCLK_I2C7 308 +#define CLK_I2C7 309 +#define PCLK_USBPHY 310 +#define CLK_REF_USBPHY 311 +#define HCLK_RKVDEC_ROOT 312 +#define ACLK_RKVDEC_ROOT_NDFT 313 +#define PCLK_DDRPHY_CRU 314 +#define HCLK_RKVDEC_BIU 315 +#define ACLK_RKVDEC_BIU 316 +#define ACLK_RKVDEC 317 +#define HCLK_RKVDEC 318 +#define CLK_HEVC_CA_RKVDEC 319 +#define ACLK_RKVDEC_PVTMUX_ROOT 320 +#define CLK_RKVDEC_PVTPLL_SRC 321 +#define PCLK_DDR_ROOT 322 +#define PCLK_DDR_BIU 323 +#define PCLK_DDRC 324 +#define PCLK_DDRMON 325 +#define CLK_TIMER_DDRMON 326 +#define PCLK_MSCH_BIU 327 +#define PCLK_DDR_GRF 328 +#define PCLK_DDR_HWLP 329 +#define PCLK_DDRPHY 330 +#define CLK_MSCH_BIU 331 +#define ACLK_DDR_UPCTL 332 +#define CLK_DDR_UPCTL 333 +#define CLK_DDRMON 334 +#define ACLK_DDR_SCRAMBLE 335 +#define ACLK_SPLIT 336 +#define CLK_DDRC_SRC 337 +#define CLK_DDR_PHY 338 +#define PCLK_OTPC_S 339 +#define CLK_SBPI_OTPC_S 340 +#define CLK_USER_OTPC_S 341 +#define PCLK_KEYREADER 342 +#define PCLK_BUS_SGRF 343 +#define PCLK_STIMER 344 +#define CLK_STIMER0 345 +#define CLK_STIMER1 346 +#define PCLK_WDT_S 347 +#define TCLK_WDT_S 348 +#define HCLK_TRNG_S 349 +#define HCLK_BOOTROM 350 +#define PCLK_DCF 351 +#define ACLK_SYSMEM 352 +#define HCLK_TSP 353 +#define ACLK_TSP 354 +#define CLK_CORE_TSP 355 +#define CLK_OTPC_ARB 356 +#define PCLK_OTP_MASK 357 +#define CLK_PMC_OTP 358 +#define PCLK_PMU_ROOT 359 +#define HCLK_PMU_ROOT 360 +#define PCLK_I2C2 361 +#define CLK_I2C2 362 +#define HCLK_PMU_BIU 363 +#define PCLK_PMU_BIU 364 +#define FCLK_MCU 365 +#define RTC_CLK_MCU 366 +#define PCLK_OSCCHK 367 +#define CLK_PMU_MCU_JTAG 368 +#define PCLK_PMU 369 +#define PCLK_GPIO0 370 +#define DBCLK_GPIO0 371 +#define XIN_OSC0_DIV 372 +#define CLK_DEEPSLOW 373 +#define CLK_DDR_FAIL_SAFE 374 +#define PCLK_PMU_HP_TIMER 375 +#define CLK_PMU_HP_TIMER 376 +#define CLK_PMU_32K_HP_TIMER 377 +#define PCLK_PMU_IOC 378 +#define PCLK_PMU_CRU 379 +#define PCLK_PMU_GRF 380 +#define PCLK_PMU_WDT 381 +#define TCLK_PMU_WDT 382 +#define PCLK_PMU_MAILBOX 383 +#define PCLK_SCRKEYGEN 384 +#define CLK_SCRKEYGEN 385 +#define CLK_PVTM_OSCCHK 386 +#define CLK_REFOUT 387 +#define CLK_PVTM_PMU 388 +#define PCLK_PVTM_PMU 389 +#define PCLK_PMU_SGRF 390 +#define HCLK_PMU_SRAM 391 +#define CLK_UART0 392 +#define CLK_UART1 393 +#define CLK_UART2 394 +#define CLK_UART3 395 +#define CLK_UART4 396 +#define CLK_UART5 397 +#define CLK_UART6 398 +#define CLK_UART7 399 +#define MCLK_I2S0_2CH_SAI_SRC_PRE 400 +#define MCLK_I2S1_8CH_SAI_SRC_PRE 401 +#define MCLK_I2S2_2CH_SAI_SRC_PRE 402 +#define MCLK_I2S3_8CH_SAI_SRC_PRE 403 +#define MCLK_SDPDIF_SRC_PRE 404 +#define SCLK_SDMMC_DRV 405 +#define SCLK_SDMMC_SAMPLE 406 +#define SCLK_SDIO0_DRV 407 +#define SCLK_SDIO0_SAMPLE 408 +#define SCLK_SDIO1_DRV 409 +#define SCLK_SDIO1_SAMPLE 410 + +/* scmi-clocks indices */ +#define SCMI_PCLK_KEYREADER 0 +#define SCMI_HCLK_KLAD 1 +#define SCMI_PCLK_KLAD 2 +#define SCMI_HCLK_TRNG_S 3 +#define SCMI_HCLK_CRYPTO_S 4 +#define SCMI_PCLK_WDT_S 5 +#define SCMI_TCLK_WDT_S 6 +#define SCMI_PCLK_STIMER 7 +#define SCMI_CLK_STIMER0 8 +#define SCMI_CLK_STIMER1 9 +#define SCMI_PCLK_OTP_MASK 10 +#define SCMI_PCLK_OTPC_S 11 +#define SCMI_CLK_SBPI_OTPC_S 12 +#define SCMI_CLK_USER_OTPC_S 13 +#define SCMI_CLK_PMC_OTP 14 +#define SCMI_CLK_OTPC_ARB 15 +#define SCMI_CLK_CORE_TSP 16 +#define SCMI_ACLK_TSP 17 +#define SCMI_HCLK_TSP 18 +#define SCMI_PCLK_DCF 19 +#define SCMI_CLK_DDR 20 +#define SCMI_CLK_CPU 21 +#define SCMI_CLK_GPU 22 +#define SCMI_CORE_CRYPTO 23 +#define SCMI_ACLK_CRYPTO 24 +#define SCMI_PKA_CRYPTO 25 +#define SCMI_HCLK_CRYPTO 26 +#define SCMI_CORE_CRYPTO_S 27 +#define SCMI_ACLK_CRYPTO_S 28 +#define SCMI_PKA_CRYPTO_S 29 +#define SCMI_CORE_KLAD 30 +#define SCMI_ACLK_KLAD 31 +#define SCMI_HCLK_TRNG 32 + +#endif // _DT_BINDINGS_CLK_ROCKCHIP_RK3528_H diff --git a/include/dt-bindings/clock/rockchip,rk3562-cru.h b/include/dt-bindings/clock/rockchip,rk3562-cru.h new file mode 100644 index 000000000000..a5b0b153209c --- /dev/null +++ b/include/dt-bindings/clock/rockchip,rk3562-cru.h @@ -0,0 +1,379 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) 2022-2025 Rockchip Electronics Co., Ltd. + * Author: Finley Xiao <finley.xiao@rock-chips.com> + */ + +#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3562_H +#define _DT_BINDINGS_CLK_ROCKCHIP_RK3562_H + +/* cru-clocks indices */ + +/* cru plls */ +#define PLL_DMPLL0 0 +#define PLL_APLL 1 +#define PLL_GPLL 2 +#define PLL_VPLL 3 +#define PLL_HPLL 4 +#define PLL_CPLL 5 +#define PLL_DPLL 6 +#define PLL_DMPLL1 7 + +/* cru clocks */ +#define ARMCLK 8 +#define CLK_GPU 9 +#define ACLK_RKNN 10 +#define CLK_DDR 11 +#define CLK_MATRIX_50M_SRC 12 +#define CLK_MATRIX_100M_SRC 13 +#define CLK_MATRIX_125M_SRC 14 +#define CLK_MATRIX_200M_SRC 15 +#define CLK_MATRIX_300M_SRC 16 +#define ACLK_TOP 17 +#define ACLK_TOP_VIO 18 +#define CLK_CAM0_OUT2IO 19 +#define CLK_CAM1_OUT2IO 20 +#define CLK_CAM2_OUT2IO 21 +#define CLK_CAM3_OUT2IO 22 +#define ACLK_BUS 23 +#define HCLK_BUS 24 +#define PCLK_BUS 25 +#define PCLK_I2C1 26 +#define PCLK_I2C2 27 +#define PCLK_I2C3 28 +#define PCLK_I2C4 29 +#define PCLK_I2C5 30 +#define CLK_I2C 31 +#define CLK_I2C1 32 +#define CLK_I2C2 33 +#define CLK_I2C3 34 +#define CLK_I2C4 35 +#define CLK_I2C5 36 +#define DCLK_BUS_GPIO 37 +#define DCLK_BUS_GPIO3 38 +#define DCLK_BUS_GPIO4 39 +#define PCLK_TIMER 40 +#define CLK_TIMER0 41 +#define CLK_TIMER1 42 +#define CLK_TIMER2 43 +#define CLK_TIMER3 44 +#define CLK_TIMER4 45 +#define CLK_TIMER5 46 +#define PCLK_STIMER 47 +#define CLK_STIMER0 48 +#define CLK_STIMER1 49 +#define PCLK_WDTNS 50 +#define CLK_WDTNS 51 +#define PCLK_GRF 52 +#define PCLK_SGRF 53 +#define PCLK_MAILBOX 54 +#define PCLK_INTC 55 +#define ACLK_BUS_GIC400 56 +#define ACLK_BUS_SPINLOCK 57 +#define ACLK_DCF 58 +#define PCLK_DCF 59 +#define FCLK_BUS_CM0_CORE 60 +#define CLK_BUS_CM0_RTC 61 +#define HCLK_ICACHE 62 +#define HCLK_DCACHE 63 +#define PCLK_TSADC 64 +#define CLK_TSADC 65 +#define CLK_TSADC_TSEN 66 +#define PCLK_DFT2APB 67 +#define CLK_SARADC_VCCIO156 68 +#define PCLK_GMAC 69 +#define ACLK_GMAC 70 +#define CLK_GMAC_125M_CRU_I 71 +#define CLK_GMAC_50M_CRU_I 72 +#define CLK_GMAC_50M_O 73 +#define CLK_GMAC_ETH_OUT2IO 74 +#define PCLK_APB2ASB_VCCIO156 75 +#define PCLK_TO_VCCIO156 76 +#define PCLK_DSIPHY 77 +#define PCLK_DSITX 78 +#define PCLK_CPU_EMA_DET 79 +#define PCLK_HASH 80 +#define PCLK_TOPCRU 81 +#define PCLK_ASB2APB_VCCIO156 82 +#define PCLK_IOC_VCCIO156 83 +#define PCLK_GPIO3_VCCIO156 84 +#define PCLK_GPIO4_VCCIO156 85 +#define PCLK_SARADC_VCCIO156 86 +#define PCLK_MAC100 87 +#define ACLK_MAC100 89 +#define CLK_MAC100_50M_MATRIX 90 +#define HCLK_CORE 91 +#define PCLK_DDR 92 +#define CLK_MSCH_BRG_BIU 93 +#define PCLK_DDR_HWLP 94 +#define PCLK_DDR_UPCTL 95 +#define PCLK_DDR_PHY 96 +#define PCLK_DDR_DFICTL 97 +#define PCLK_DDR_DMA2DDR 98 +#define PCLK_DDR_MON 99 +#define TMCLK_DDR_MON 100 +#define PCLK_DDR_GRF 101 +#define PCLK_DDR_CRU 102 +#define PCLK_SUBDDR_CRU 103 +#define CLK_GPU_PRE 104 +#define ACLK_GPU_PRE 105 +#define CLK_GPU_BRG 107 +#define CLK_NPU_PRE 108 +#define HCLK_NPU_PRE 109 +#define HCLK_RKNN 111 +#define ACLK_PERI 112 +#define HCLK_PERI 113 +#define PCLK_PERI 114 +#define PCLK_PERICRU 115 +#define HCLK_SAI0 116 +#define CLK_SAI0_SRC 117 +#define CLK_SAI0_FRAC 118 +#define CLK_SAI0 119 +#define MCLK_SAI0 120 +#define MCLK_SAI0_OUT2IO 121 +#define HCLK_SAI1 122 +#define CLK_SAI1_SRC 123 +#define CLK_SAI1_FRAC 124 +#define CLK_SAI1 125 +#define MCLK_SAI1 126 +#define MCLK_SAI1_OUT2IO 127 +#define HCLK_SAI2 128 +#define CLK_SAI2_SRC 129 +#define CLK_SAI2_FRAC 130 +#define CLK_SAI2 131 +#define MCLK_SAI2 132 +#define MCLK_SAI2_OUT2IO 133 +#define HCLK_DSM 134 +#define CLK_DSM 135 +#define HCLK_PDM 136 +#define MCLK_PDM 137 +#define HCLK_SPDIF 138 +#define CLK_SPDIF_SRC 139 +#define CLK_SPDIF_FRAC 140 +#define CLK_SPDIF 141 +#define MCLK_SPDIF 142 +#define HCLK_SDMMC0 143 +#define CCLK_SDMMC0 144 +#define HCLK_SDMMC1 145 +#define CCLK_SDMMC1 146 +#define SCLK_SDMMC0_DRV 147 +#define SCLK_SDMMC0_SAMPLE 148 +#define SCLK_SDMMC1_DRV 149 +#define SCLK_SDMMC1_SAMPLE 150 +#define HCLK_EMMC 151 +#define ACLK_EMMC 152 +#define CCLK_EMMC 153 +#define BCLK_EMMC 154 +#define TMCLK_EMMC 155 +#define SCLK_SFC 156 +#define HCLK_SFC 157 +#define HCLK_USB2HOST 158 +#define HCLK_USB2HOST_ARB 159 +#define PCLK_SPI1 160 +#define CLK_SPI1 161 +#define SCLK_IN_SPI1 162 +#define PCLK_SPI2 163 +#define CLK_SPI2 164 +#define SCLK_IN_SPI2 165 +#define PCLK_UART1 166 +#define PCLK_UART2 167 +#define PCLK_UART3 168 +#define PCLK_UART4 169 +#define PCLK_UART5 170 +#define PCLK_UART6 171 +#define PCLK_UART7 172 +#define PCLK_UART8 173 +#define PCLK_UART9 174 +#define CLK_UART1_SRC 175 +#define CLK_UART1_FRAC 176 +#define CLK_UART1 177 +#define SCLK_UART1 178 +#define CLK_UART2_SRC 179 +#define CLK_UART2_FRAC 180 +#define CLK_UART2 181 +#define SCLK_UART2 182 +#define CLK_UART3_SRC 183 +#define CLK_UART3_FRAC 184 +#define CLK_UART3 185 +#define SCLK_UART3 186 +#define CLK_UART4_SRC 187 +#define CLK_UART4_FRAC 188 +#define CLK_UART4 189 +#define SCLK_UART4 190 +#define CLK_UART5_SRC 191 +#define CLK_UART5_FRAC 192 +#define CLK_UART5 193 +#define SCLK_UART5 194 +#define CLK_UART6_SRC 195 +#define CLK_UART6_FRAC 196 +#define CLK_UART6 197 +#define SCLK_UART6 198 +#define CLK_UART7_SRC 199 +#define CLK_UART7_FRAC 200 +#define CLK_UART7 201 +#define SCLK_UART7 202 +#define CLK_UART8_SRC 203 +#define CLK_UART8_FRAC 204 +#define CLK_UART8 205 +#define SCLK_UART8 206 +#define CLK_UART9_SRC 207 +#define CLK_UART9_FRAC 208 +#define CLK_UART9 209 +#define SCLK_UART9 210 +#define PCLK_PWM1_PERI 211 +#define CLK_PWM1_PERI 212 +#define CLK_CAPTURE_PWM1_PERI 213 +#define PCLK_PWM2_PERI 214 +#define CLK_PWM2_PERI 215 +#define CLK_CAPTURE_PWM2_PERI 216 +#define PCLK_PWM3_PERI 217 +#define CLK_PWM3_PERI 218 +#define CLK_CAPTURE_PWM3_PERI 219 +#define PCLK_CAN0 220 +#define CLK_CAN0 221 +#define PCLK_CAN1 222 +#define CLK_CAN1 223 +#define ACLK_CRYPTO 224 +#define HCLK_CRYPTO 225 +#define PCLK_CRYPTO 226 +#define CLK_CORE_CRYPTO 227 +#define CLK_PKA_CRYPTO 228 +#define HCLK_KLAD 229 +#define PCLK_KEY_READER 230 +#define HCLK_RK_RNG_NS 231 +#define HCLK_RK_RNG_S 232 +#define HCLK_TRNG_NS 233 +#define HCLK_TRNG_S 234 +#define HCLK_CRYPTO_S 235 +#define PCLK_PERI_WDT 236 +#define TCLK_PERI_WDT 237 +#define ACLK_SYSMEM 238 +#define HCLK_BOOTROM 239 +#define PCLK_PERI_GRF 240 +#define ACLK_DMAC 241 +#define ACLK_RKDMAC 242 +#define PCLK_OTPC_NS 243 +#define CLK_SBPI_OTPC_NS 244 +#define CLK_USER_OTPC_NS 245 +#define PCLK_OTPC_S 246 +#define CLK_SBPI_OTPC_S 247 +#define CLK_USER_OTPC_S 248 +#define CLK_OTPC_ARB 249 +#define PCLK_OTPPHY 250 +#define PCLK_USB2PHY 251 +#define PCLK_PIPEPHY 252 +#define PCLK_SARADC 253 +#define CLK_SARADC 254 +#define PCLK_IOC_VCCIO234 255 +#define PCLK_PERI_GPIO1 256 +#define PCLK_PERI_GPIO2 257 +#define DCLK_PERI_GPIO 258 +#define DCLK_PERI_GPIO1 259 +#define DCLK_PERI_GPIO2 260 +#define ACLK_PHP 261 +#define PCLK_PHP 262 +#define ACLK_PCIE20_MST 263 +#define ACLK_PCIE20_SLV 264 +#define ACLK_PCIE20_DBI 265 +#define PCLK_PCIE20 266 +#define CLK_PCIE20_AUX 267 +#define ACLK_USB3OTG 268 +#define CLK_USB3OTG_SUSPEND 269 +#define CLK_USB3OTG_REF 270 +#define CLK_PIPEPHY_REF_FUNC 271 +#define CLK_200M_PMU 272 +#define CLK_RTC_32K 273 +#define CLK_RTC32K_FRAC 274 +#define BUSCLK_PDPMU0 275 +#define PCLK_PMU0_CRU 276 +#define PCLK_PMU0_PMU 277 +#define CLK_PMU0_PMU 278 +#define PCLK_PMU0_HP_TIMER 279 +#define CLK_PMU0_HP_TIMER 280 +#define CLK_PMU0_32K_HP_TIMER 281 +#define PCLK_PMU0_PVTM 282 +#define CLK_PMU0_PVTM 283 +#define PCLK_IOC_PMUIO 284 +#define PCLK_PMU0_GPIO0 285 +#define DBCLK_PMU0_GPIO0 286 +#define PCLK_PMU0_GRF 287 +#define PCLK_PMU0_SGRF 288 +#define CLK_DDR_FAIL_SAFE 289 +#define PCLK_PMU0_SCRKEYGEN 290 +#define PCLK_PMU1_CRU 291 +#define HCLK_PMU1_MEM 292 +#define PCLK_PMU0_I2C0 293 +#define CLK_PMU0_I2C0 294 +#define PCLK_PMU1_UART0 295 +#define CLK_PMU1_UART0_SRC 296 +#define CLK_PMU1_UART0_FRAC 297 +#define CLK_PMU1_UART0 298 +#define SCLK_PMU1_UART0 299 +#define PCLK_PMU1_SPI0 300 +#define CLK_PMU1_SPI0 301 +#define SCLK_IN_PMU1_SPI0 302 +#define PCLK_PMU1_PWM0 303 +#define CLK_PMU1_PWM0 304 +#define CLK_CAPTURE_PMU1_PWM0 305 +#define CLK_PMU1_WIFI 306 +#define FCLK_PMU1_CM0_CORE 307 +#define CLK_PMU1_CM0_RTC 308 +#define PCLK_PMU1_WDTNS 309 +#define CLK_PMU1_WDTNS 310 +#define PCLK_PMU1_MAILBOX 311 +#define CLK_PIPEPHY_DIV 312 +#define CLK_PIPEPHY_XIN24M 313 +#define CLK_PIPEPHY_REF 314 +#define CLK_24M_SSCSRC 315 +#define CLK_USB2PHY_XIN24M 316 +#define CLK_USB2PHY_REF 317 +#define CLK_MIPIDSIPHY_XIN24M 318 +#define CLK_MIPIDSIPHY_REF 319 +#define ACLK_RGA_PRE 320 +#define HCLK_RGA_PRE 321 +#define ACLK_RGA 322 +#define HCLK_RGA 323 +#define CLK_RGA_CORE 324 +#define ACLK_JDEC 325 +#define HCLK_JDEC 326 +#define ACLK_VDPU_PRE 327 +#define CLK_RKVDEC_HEVC_CA 328 +#define HCLK_VDPU_PRE 329 +#define ACLK_RKVDEC 330 +#define HCLK_RKVDEC 331 +#define CLK_RKVENC_CORE 332 +#define ACLK_VEPU_PRE 333 +#define HCLK_VEPU_PRE 334 +#define ACLK_RKVENC 335 +#define HCLK_RKVENC 336 +#define ACLK_VI 337 +#define HCLK_VI 338 +#define PCLK_VI 339 +#define ACLK_ISP 340 +#define HCLK_ISP 341 +#define CLK_ISP 342 +#define ACLK_VICAP 343 +#define HCLK_VICAP 344 +#define DCLK_VICAP 345 +#define CSIRX0_CLK_DATA 346 +#define CSIRX1_CLK_DATA 347 +#define CSIRX2_CLK_DATA 348 +#define CSIRX3_CLK_DATA 349 +#define PCLK_CSIHOST0 350 +#define PCLK_CSIHOST1 351 +#define PCLK_CSIHOST2 352 +#define PCLK_CSIHOST3 353 +#define PCLK_CSIPHY0 354 +#define PCLK_CSIPHY1 355 +#define ACLK_VO_PRE 356 +#define HCLK_VO_PRE 357 +#define ACLK_VOP 358 +#define HCLK_VOP 359 +#define DCLK_VOP 360 +#define DCLK_VOP1 361 +#define ACLK_CRYPTO_S 362 +#define PCLK_CRYPTO_S 363 +#define CLK_CORE_CRYPTO_S 364 +#define CLK_PKA_CRYPTO_S 365 + +#endif diff --git a/include/dt-bindings/clock/rockchip,rk3576-cru.h b/include/dt-bindings/clock/rockchip,rk3576-cru.h index 25aed298ac2c..ded5ce42e62a 100644 --- a/include/dt-bindings/clock/rockchip,rk3576-cru.h +++ b/include/dt-bindings/clock/rockchip,rk3576-cru.h @@ -589,4 +589,19 @@ #define PCLK_EDP_S 569 #define ACLK_KLAD 570 +/* SCMI clocks, use these when changing clocks through SCMI */ +#define SCMI_ARMCLK_L 10 +#define SCMI_ARMCLK_B 11 +#define SCMI_CLK_GPU 456 + +/* IOC-controlled output clocks */ +#define CLK_SAI0_MCLKOUT_TO_IO 571 +#define CLK_SAI1_MCLKOUT_TO_IO 572 +#define CLK_SAI2_MCLKOUT_TO_IO 573 +#define CLK_SAI3_MCLKOUT_TO_IO 574 +#define CLK_SAI4_MCLKOUT_TO_IO 575 +#define CLK_SAI4_MCLKOUT_TO_IO 575 +#define CLK_FSPI0_TO_IO 576 +#define CLK_FSPI1_TO_IO 577 + #endif diff --git a/include/dt-bindings/clock/samsung,exynos2200-cmu.h b/include/dt-bindings/clock/samsung,exynos2200-cmu.h new file mode 100644 index 000000000000..310552be0c8c --- /dev/null +++ b/include/dt-bindings/clock/samsung,exynos2200-cmu.h @@ -0,0 +1,431 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) 2025 Ivaylo Ivanov <ivo.ivanov.ivanov1@gmail.com> + * Author: Ivaylo Ivanov <ivo.ivanov.ivanov1@gmail.com> + * + * Device Tree binding constants for Exynos2200 clock controller. + */ + +#ifndef _DT_BINDINGS_CLOCK_EXYNOS2200_H +#define _DT_BINDINGS_CLOCK_EXYNOS2200_H + +/* CMU_TOP */ +#define CLK_FOUT_SHARED0_PLL 1 +#define CLK_FOUT_SHARED1_PLL 2 +#define CLK_FOUT_SHARED2_PLL 3 +#define CLK_FOUT_SHARED3_PLL 4 +#define CLK_FOUT_SHARED4_PLL 5 +#define CLK_FOUT_MMC_PLL 6 +#define CLK_FOUT_SHARED_MIF_PLL 7 + +#define CLK_MOUT_CMU_CP_MPLL_CLK_D2_USER 8 +#define CLK_MOUT_CMU_CP_MPLL_CLK_USER 9 +#define CLK_MOUT_CMU_AUD_AUDIF0 10 +#define CLK_MOUT_CMU_AUD_AUDIF1 11 +#define CLK_MOUT_CMU_AUD_CPU 12 +#define CLK_MOUT_CMU_CPUCL0_DBG_NOC 13 +#define CLK_MOUT_CMU_CPUCL0_SWITCH 14 +#define CLK_MOUT_CMU_CPUCL1_SWITCH 15 +#define CLK_MOUT_CMU_CPUCL2_SWITCH 16 +#define CLK_MOUT_CMU_DNC_NOC 17 +#define CLK_MOUT_CMU_DPUB_NOC 18 +#define CLK_MOUT_CMU_DPUF_NOC 19 +#define CLK_MOUT_CMU_DSP_NOC 20 +#define CLK_MOUT_CMU_DSU_SWITCH 21 +#define CLK_MOUT_CMU_G3D_SWITCH 22 +#define CLK_MOUT_CMU_GNPU_NOC 23 +#define CLK_MOUT_CMU_UFS_MMC_CARD 24 +#define CLK_MOUT_CMU_M2M_NOC 25 +#define CLK_MOUT_CMU_NOCL0_NOC 26 +#define CLK_MOUT_CMU_NOCL1A_NOC 27 +#define CLK_MOUT_CMU_NOCL1B_NOC0 28 +#define CLK_MOUT_CMU_NOCL1C_NOC 29 +#define CLK_MOUT_CMU_SDMA_NOC 30 +#define CLK_MOUT_CMU_CP_HISPEEDY_CLK 31 +#define CLK_MOUT_CMU_CP_SHARED0_CLK 32 +#define CLK_MOUT_CMU_CP_SHARED2_CLK 33 +#define CLK_MOUT_CMU_MUX_ALIVE_NOC 34 +#define CLK_MOUT_CMU_MUX_AUD_AUDIF0 35 +#define CLK_MOUT_CMU_MUX_AUD_AUDIF1 36 +#define CLK_MOUT_CMU_MUX_AUD_CPU 37 +#define CLK_MOUT_CMU_MUX_AUD_NOC 38 +#define CLK_MOUT_CMU_MUX_BRP_NOC 39 +#define CLK_MOUT_CMU_MUX_CIS_CLK0 40 +#define CLK_MOUT_CMU_MUX_CIS_CLK1 41 +#define CLK_MOUT_CMU_MUX_CIS_CLK2 42 +#define CLK_MOUT_CMU_MUX_CIS_CLK3 43 +#define CLK_MOUT_CMU_MUX_CIS_CLK4 44 +#define CLK_MOUT_CMU_MUX_CIS_CLK5 45 +#define CLK_MOUT_CMU_MUX_CIS_CLK6 46 +#define CLK_MOUT_CMU_MUX_CIS_CLK7 47 +#define CLK_MOUT_CMU_MUX_CMU_BOOST 48 +#define CLK_MOUT_CMU_MUX_CMU_BOOST_CAM 49 +#define CLK_MOUT_CMU_MUX_CMU_BOOST_CPU 50 +#define CLK_MOUT_CMU_MUX_CMU_BOOST_MIF 51 +#define CLK_MOUT_CMU_MUX_CPUCL0_DBG_NOC 52 +#define CLK_MOUT_CMU_MUX_CPUCL0_NOCP 53 +#define CLK_MOUT_CMU_MUX_CPUCL0_SWITCH 54 +#define CLK_MOUT_CMU_MUX_CPUCL1_SWITCH 55 +#define CLK_MOUT_CMU_MUX_CPUCL2_SWITCH 56 +#define CLK_MOUT_CMU_MUX_CSIS_DCPHY 57 +#define CLK_MOUT_CMU_MUX_CSIS_NOC 58 +#define CLK_MOUT_CMU_MUX_CSIS_OIS_MCU 59 +#define CLK_MOUT_CMU_MUX_CSTAT_NOC 60 +#define CLK_MOUT_CMU_MUX_DNC_NOC 61 +#define CLK_MOUT_CMU_MUX_DPUB 62 +#define CLK_MOUT_CMU_MUX_DPUB_ALT 63 +#define CLK_MOUT_CMU_MUX_DPUB_DSIM 64 +#define CLK_MOUT_CMU_MUX_DPUF 65 +#define CLK_MOUT_CMU_MUX_DPUF_ALT 66 +#define CLK_MOUT_CMU_MUX_DSP_NOC 67 +#define CLK_MOUT_CMU_MUX_DSU_SWITCH 68 +#define CLK_MOUT_CMU_MUX_G3D_NOCP 69 +#define CLK_MOUT_CMU_MUX_G3D_SWITCH 70 +#define CLK_MOUT_CMU_MUX_GNPU_NOC 71 +#define CLK_MOUT_CMU_MUX_HSI0_DPGTC 72 +#define CLK_MOUT_CMU_MUX_HSI0_DPOSC 73 +#define CLK_MOUT_CMU_MUX_HSI0_NOC 74 +#define CLK_MOUT_CMU_MUX_HSI0_USB32DRD 75 +#define CLK_MOUT_CMU_MUX_UFS_MMC_CARD 76 +#define CLK_MOUT_CMU_MUX_HSI1_NOC 77 +#define CLK_MOUT_CMU_MUX_HSI1_PCIE 78 +#define CLK_MOUT_CMU_MUX_UFS_UFS_EMBD 79 +#define CLK_MOUT_CMU_MUX_LME_LME 80 +#define CLK_MOUT_CMU_MUX_LME_NOC 81 +#define CLK_MOUT_CMU_MUX_M2M_NOC 82 +#define CLK_MOUT_CMU_MUX_MCSC_MCSC 83 +#define CLK_MOUT_CMU_MUX_MCSC_NOC 84 +#define CLK_MOUT_CMU_MUX_MFC0_MFC0 85 +#define CLK_MOUT_CMU_MUX_MFC0_WFD 86 +#define CLK_MOUT_CMU_MUX_MFC1_MFC1 87 +#define CLK_MOUT_CMU_MUX_MIF_NOCP 88 +#define CLK_MOUT_CMU_MUX_MIF_SWITCH 89 +#define CLK_MOUT_CMU_MUX_NOCL0_NOC 90 +#define CLK_MOUT_CMU_MUX_NOCL1A_NOC 91 +#define CLK_MOUT_CMU_MUX_NOCL1B_NOC0 92 +#define CLK_MOUT_CMU_MUX_NOCL1B_NOC1 93 +#define CLK_MOUT_CMU_MUX_NOCL1C_NOC 94 +#define CLK_MOUT_CMU_MUX_PERIC0_IP0 95 +#define CLK_MOUT_CMU_MUX_PERIC0_IP1 96 +#define CLK_MOUT_CMU_MUX_PERIC0_NOC 97 +#define CLK_MOUT_CMU_MUX_PERIC1_IP0 98 +#define CLK_MOUT_CMU_MUX_PERIC1_IP1 99 +#define CLK_MOUT_CMU_MUX_PERIC1_NOC 100 +#define CLK_MOUT_CMU_MUX_PERIC2_IP0 101 +#define CLK_MOUT_CMU_MUX_PERIC2_IP1 102 +#define CLK_MOUT_CMU_MUX_PERIC2_NOC 103 +#define CLK_MOUT_CMU_MUX_PERIS_GIC 104 +#define CLK_MOUT_CMU_MUX_PERIS_NOC 105 +#define CLK_MOUT_CMU_MUX_SDMA_NOC 106 +#define CLK_MOUT_CMU_MUX_SSP_NOC 107 +#define CLK_MOUT_CMU_MUX_VTS_DMIC 108 +#define CLK_MOUT_CMU_MUX_YUVP_NOC 109 +#define CLK_MOUT_CMU_MUX_CMU_CMUREF 110 +#define CLK_MOUT_CMU_MUX_CP_HISPEEDY_CLK 111 +#define CLK_MOUT_CMU_MUX_CP_SHARED0_CLK 112 +#define CLK_MOUT_CMU_MUX_CP_SHARED1_CLK 113 +#define CLK_MOUT_CMU_MUX_CP_SHARED2_CLK 114 +#define CLK_MOUT_CMU_M2M_FRC 115 +#define CLK_MOUT_CMU_MCSC_MCSC 116 +#define CLK_MOUT_CMU_MCSC_NOC 117 +#define CLK_MOUT_CMU_MUX_M2M_FRC 118 +#define CLK_MOUT_CMU_MUX_UFS_NOC 119 + +#define CLK_DOUT_CMU_ALIVE_NOC 120 +#define CLK_DOUT_CMU_AUD_NOC 121 +#define CLK_DOUT_CMU_BRP_NOC 122 +#define CLK_DOUT_CMU_CMU_BOOST 123 +#define CLK_DOUT_CMU_CMU_BOOST_CAM 124 +#define CLK_DOUT_CMU_CMU_BOOST_CPU 125 +#define CLK_DOUT_CMU_CMU_BOOST_MIF 126 +#define CLK_DOUT_CMU_CPUCL0_NOCP 127 +#define CLK_DOUT_CMU_CSIS_DCPHY 128 +#define CLK_DOUT_CMU_CSIS_NOC 129 +#define CLK_DOUT_CMU_CSIS_OIS_MCU 130 +#define CLK_DOUT_CMU_CSTAT_NOC 131 +#define CLK_DOUT_CMU_DPUB_DSIM 132 +#define CLK_DOUT_CMU_LME_LME 133 +#define CLK_DOUT_CMU_G3D_NOCP 134 +#define CLK_DOUT_CMU_HSI0_DPGTC 135 +#define CLK_DOUT_CMU_HSI0_DPOSC 136 +#define CLK_DOUT_CMU_HSI0_NOC 137 +#define CLK_DOUT_CMU_HSI0_USB32DRD 138 +#define CLK_DOUT_CMU_HSI1_NOC 139 +#define CLK_DOUT_CMU_HSI1_PCIE 140 +#define CLK_DOUT_CMU_UFS_UFS_EMBD 141 +#define CLK_DOUT_CMU_LME_NOC 142 +#define CLK_DOUT_CMU_MFC0_MFC0 143 +#define CLK_DOUT_CMU_MFC0_WFD 144 +#define CLK_DOUT_CMU_MFC1_MFC1 145 +#define CLK_DOUT_CMU_MIF_NOCP 146 +#define CLK_DOUT_CMU_NOCL1B_NOC1 147 +#define CLK_DOUT_CMU_PERIC0_IP0 148 +#define CLK_DOUT_CMU_PERIC0_IP1 149 +#define CLK_DOUT_CMU_PERIC0_NOC 150 +#define CLK_DOUT_CMU_PERIC1_IP0 151 +#define CLK_DOUT_CMU_PERIC1_IP1 152 +#define CLK_DOUT_CMU_PERIC1_NOC 153 +#define CLK_DOUT_CMU_PERIC2_IP0 154 +#define CLK_DOUT_CMU_PERIC2_IP1 155 +#define CLK_DOUT_CMU_PERIC2_NOC 156 +#define CLK_DOUT_CMU_PERIS_GIC 157 +#define CLK_DOUT_CMU_PERIS_NOC 158 +#define CLK_DOUT_CMU_SSP_NOC 159 +#define CLK_DOUT_CMU_VTS_DMIC 160 +#define CLK_DOUT_CMU_YUVP_NOC 161 +#define CLK_DOUT_CMU_CP_SHARED1_CLK 162 +#define CLK_DOUT_CMU_DIV_AUD_AUDIF0 163 +#define CLK_DOUT_CMU_DIV_AUD_AUDIF0_SM 164 +#define CLK_DOUT_CMU_DIV_AUD_AUDIF1 165 +#define CLK_DOUT_CMU_DIV_AUD_AUDIF1_SM 166 +#define CLK_DOUT_CMU_DIV_AUD_CPU 167 +#define CLK_DOUT_CMU_DIV_AUD_CPU_SM 168 +#define CLK_DOUT_CMU_DIV_CIS_CLK0 169 +#define CLK_DOUT_CMU_DIV_CIS_CLK1 170 +#define CLK_DOUT_CMU_DIV_CIS_CLK2 171 +#define CLK_DOUT_CMU_DIV_CIS_CLK3 172 +#define CLK_DOUT_CMU_DIV_CIS_CLK4 173 +#define CLK_DOUT_CMU_DIV_CIS_CLK5 174 +#define CLK_DOUT_CMU_DIV_CIS_CLK6 175 +#define CLK_DOUT_CMU_DIV_CIS_CLK7 176 +#define CLK_DOUT_CMU_DIV_CPUCL0_DBG_NOC 177 +#define CLK_DOUT_CMU_DIV_CPUCL0_DBG_NOC_SM 178 +#define CLK_DOUT_CMU_DIV_CPUCL0_SWITCH 179 +#define CLK_DOUT_CMU_DIV_CPUCL0_SWITCH_SM 180 +#define CLK_DOUT_CMU_DIV_CPUCL1_SWITCH 181 +#define CLK_DOUT_CMU_DIV_CPUCL1_SWITCH_SM 182 +#define CLK_DOUT_CMU_DIV_CPUCL2_SWITCH 183 +#define CLK_DOUT_CMU_DIV_CPUCL2_SWITCH_SM 184 +#define CLK_DOUT_CMU_DIV_DNC_NOC 185 +#define CLK_DOUT_CMU_DIV_DNC_NOC_SM 186 +#define CLK_DOUT_CMU_DIV_DPUB 187 +#define CLK_DOUT_CMU_DIV_DPUB_ALT 188 +#define CLK_DOUT_CMU_DIV_DPUF 189 +#define CLK_DOUT_CMU_DIV_DPUF_ALT 190 +#define CLK_DOUT_CMU_DIV_DSP_NOC 191 +#define CLK_DOUT_CMU_DIV_DSP_NOC_SM 192 +#define CLK_DOUT_CMU_DIV_DSU_SWITCH 193 +#define CLK_DOUT_CMU_DIV_DSU_SWITCH_SM 194 +#define CLK_DOUT_CMU_DIV_G3D_SWITCH 195 +#define CLK_DOUT_CMU_DIV_G3D_SWITCH_SM 196 +#define CLK_DOUT_CMU_DIV_GNPU_NOC 197 +#define CLK_DOUT_CMU_DIV_GNPU_NOC_SM 198 +#define CLK_DOUT_CMU_DIV_UFS_MMC_CARD 199 +#define CLK_DOUT_CMU_DIV_UFS_MMC_CARD_SM 200 +#define CLK_DOUT_CMU_DIV_M2M_NOC 201 +#define CLK_DOUT_CMU_DIV_M2M_NOC_SM 202 +#define CLK_DOUT_CMU_DIV_NOCL0_NOC 203 +#define CLK_DOUT_CMU_DIV_NOCL0_NOC_SM 204 +#define CLK_DOUT_CMU_DIV_NOCL1A_NOC 205 +#define CLK_DOUT_CMU_DIV_NOCL1A_NOC_SM 206 +#define CLK_DOUT_CMU_DIV_NOCL1B_NOC0 207 +#define CLK_DOUT_CMU_DIV_NOCL1B_NOC0_SM 208 +#define CLK_DOUT_CMU_DIV_NOCL1C_NOC 209 +#define CLK_DOUT_CMU_DIV_NOCL1C_NOC_SM 210 +#define CLK_DOUT_CMU_DIV_SDMA_NOC 211 +#define CLK_DOUT_CMU_DIV_SDMA_NOC_SM 212 +#define CLK_DOUT_CMU_DIV_CP_HISPEEDY_CLK 213 +#define CLK_DOUT_CMU_DIV_CP_HISPEEDY_CLK_SM 214 +#define CLK_DOUT_CMU_DIV_CP_SHARED0_CLK 215 +#define CLK_DOUT_CMU_DIV_CP_SHARED0_CLK_SM 216 +#define CLK_DOUT_CMU_DIV_CP_SHARED2_CLK 217 +#define CLK_DOUT_CMU_DIV_CP_SHARED2_CLK_SM 218 +#define CLK_DOUT_CMU_UFS_NOC 219 +#define CLK_DOUT_CMU_DIV_M2M_FRC 220 +#define CLK_DOUT_CMU_DIV_M2M_FRC_SM 221 +#define CLK_DOUT_CMU_DIV_MCSC_MCSC 222 +#define CLK_DOUT_CMU_DIV_MCSC_MCSC_SM 223 +#define CLK_DOUT_CMU_DIV_MCSC_NOC 224 +#define CLK_DOUT_CMU_DIV_MCSC_NOC_SM 225 +#define CLK_DOUT_SHARED0_DIV1 226 +#define CLK_DOUT_SHARED0_DIV2 227 +#define CLK_DOUT_SHARED0_DIV4 228 +#define CLK_DOUT_SHARED1_DIV1 229 +#define CLK_DOUT_SHARED1_DIV2 230 +#define CLK_DOUT_SHARED1_DIV4 231 +#define CLK_DOUT_SHARED2_DIV1 232 +#define CLK_DOUT_SHARED2_DIV2 233 +#define CLK_DOUT_SHARED2_DIV4 234 +#define CLK_DOUT_SHARED3_DIV1 235 +#define CLK_DOUT_SHARED3_DIV2 236 +#define CLK_DOUT_SHARED3_DIV4 237 +#define CLK_DOUT_SHARED4_DIV1 238 +#define CLK_DOUT_SHARED4_DIV2 239 +#define CLK_DOUT_SHARED4_DIV4 240 +#define CLK_DOUT_SHARED_MIF_DIV1 241 +#define CLK_DOUT_SHARED_MIF_DIV2 242 +#define CLK_DOUT_SHARED_MIF_DIV4 243 +#define CLK_DOUT_TCXO_DIV3 244 +#define CLK_DOUT_TCXO_DIV4 245 + +/* CMU_ALIVE */ +#define CLK_MOUT_ALIVE_NOC_USER 1 +#define CLK_MOUT_ALIVE_RCO_SPMI_USER 2 +#define CLK_MOUT_RCO_ALIVE_USER 3 +#define CLK_MOUT_ALIVE_CHUB_PERI 4 +#define CLK_MOUT_ALIVE_CMGP_NOC 5 +#define CLK_MOUT_ALIVE_CMGP_PERI 6 +#define CLK_MOUT_ALIVE_DBGCORE_NOC 7 +#define CLK_MOUT_ALIVE_DNC_NOC 8 +#define CLK_MOUT_ALIVE_CHUBVTS_NOC 9 +#define CLK_MOUT_ALIVE_GNPU_NOC 10 +#define CLK_MOUT_ALIVE_GNSS_NOC 11 +#define CLK_MOUT_ALIVE_SDMA_NOC 12 +#define CLK_MOUT_ALIVE_UFD_NOC 13 +#define CLK_MOUT_ALIVE_DBGCORE_UART 14 +#define CLK_MOUT_ALIVE_NOC 15 +#define CLK_MOUT_ALIVE_PMU_SUB 16 +#define CLK_MOUT_ALIVE_SPMI 17 +#define CLK_MOUT_ALIVE_TIMER 18 +#define CLK_MOUT_ALIVE_CSIS_NOC 19 +#define CLK_MOUT_ALIVE_DSP_NOC 20 + +#define CLK_DOUT_ALIVE_CHUB_PERI 21 +#define CLK_DOUT_ALIVE_CMGP_NOC 22 +#define CLK_DOUT_ALIVE_CMGP_PERI 23 +#define CLK_DOUT_ALIVE_DBGCORE_NOC 24 +#define CLK_DOUT_ALIVE_DNC_NOC 25 +#define CLK_DOUT_ALIVE_CHUBVTS_NOC 26 +#define CLK_DOUT_ALIVE_GNPU_NOC 27 +#define CLK_DOUT_ALIVE_SDMA_NOC 28 +#define CLK_DOUT_ALIVE_UFD_NOC 29 +#define CLK_DOUT_ALIVE_DBGCORE_UART 30 +#define CLK_DOUT_ALIVE_NOC 31 +#define CLK_DOUT_ALIVE_PMU_SUB 32 +#define CLK_DOUT_ALIVE_SPMI 33 +#define CLK_DOUT_ALIVE_CSIS_NOC 34 +#define CLK_DOUT_ALIVE_DSP_NOC 35 + +/* CMU_PERIS */ +#define CLK_MOUT_PERIS_GIC_USER 1 +#define CLK_MOUT_PERIS_NOC_USER 2 +#define CLK_MOUT_PERIS_GIC 3 + +#define CLK_DOUT_PERIS_OTP 4 +#define CLK_DOUT_PERIS_DDD_CTRL 5 + +/* CMU_CMGP */ +#define CLK_MOUT_CMGP_CLKALIVE_NOC_USER 1 +#define CLK_MOUT_CMGP_CLKALIVE_PERI_USER 2 +#define CLK_MOUT_CMGP_I2C 3 +#define CLK_MOUT_CMGP_SPI_I2C0 4 +#define CLK_MOUT_CMGP_SPI_I2C1 5 +#define CLK_MOUT_CMGP_SPI_MS_CTRL 6 +#define CLK_MOUT_CMGP_USI0 7 +#define CLK_MOUT_CMGP_USI1 8 +#define CLK_MOUT_CMGP_USI2 9 +#define CLK_MOUT_CMGP_USI3 10 +#define CLK_MOUT_CMGP_USI4 11 +#define CLK_MOUT_CMGP_USI5 12 +#define CLK_MOUT_CMGP_USI6 13 + +#define CLK_DOUT_CMGP_I2C 14 +#define CLK_DOUT_CMGP_SPI_I2C0 15 +#define CLK_DOUT_CMGP_SPI_I2C1 16 +#define CLK_DOUT_CMGP_SPI_MS_CTRL 17 +#define CLK_DOUT_CMGP_USI0 18 +#define CLK_DOUT_CMGP_USI1 19 +#define CLK_DOUT_CMGP_USI2 20 +#define CLK_DOUT_CMGP_USI3 21 +#define CLK_DOUT_CMGP_USI4 22 +#define CLK_DOUT_CMGP_USI5 23 +#define CLK_DOUT_CMGP_USI6 24 + +/* CMU_HSI0 */ +#define CLK_MOUT_CLKCMU_HSI0_DPGTC_USER 1 +#define CLK_MOUT_CLKCMU_HSI0_DPOSC_USER 2 +#define CLK_MOUT_CLKCMU_HSI0_NOC_USER 3 +#define CLK_MOUT_CLKCMU_HSI0_USB32DRD_USER 4 +#define CLK_MOUT_HSI0_NOC 5 +#define CLK_MOUT_HSI0_RTCCLK 6 +#define CLK_MOUT_HSI0_USB32DRD 7 + +#define CLK_DOUT_DIV_CLK_HSI0_EUSB 8 + +/* CMU_PERIC0 */ +#define CLK_MOUT_PERIC0_IP0_USER 1 +#define CLK_MOUT_PERIC0_IP1_USER 2 +#define CLK_MOUT_PERIC0_NOC_USER 3 +#define CLK_MOUT_PERIC0_I2C 4 +#define CLK_MOUT_PERIC0_USI04 5 + +#define CLK_DOUT_PERIC0_I2C 6 +#define CLK_DOUT_PERIC0_USI04 7 + +/* CMU_PERIC1 */ +#define CLK_MOUT_PERIC1_IP0_USER 1 +#define CLK_MOUT_PERIC1_IP1_USER 2 +#define CLK_MOUT_PERIC1_NOC_USER 3 +#define CLK_MOUT_PERIC1_I2C 4 +#define CLK_MOUT_PERIC1_SPI_MS_CTRL 5 +#define CLK_MOUT_PERIC1_UART_BT 6 +#define CLK_MOUT_PERIC1_USI07 7 +#define CLK_MOUT_PERIC1_USI07_SPI_I2C 8 +#define CLK_MOUT_PERIC1_USI08 9 +#define CLK_MOUT_PERIC1_USI08_SPI_I2C 10 +#define CLK_MOUT_PERIC1_USI09 11 +#define CLK_MOUT_PERIC1_USI10 12 + +#define CLK_DOUT_PERIC1_I2C 13 +#define CLK_DOUT_PERIC1_SPI_MS_CTRL 14 +#define CLK_DOUT_PERIC1_UART_BT 15 +#define CLK_DOUT_PERIC1_USI07 16 +#define CLK_DOUT_PERIC1_USI07_SPI_I2C 17 +#define CLK_DOUT_PERIC1_USI08 18 +#define CLK_DOUT_PERIC1_USI08_SPI_I2C 19 +#define CLK_DOUT_PERIC1_USI09 20 +#define CLK_DOUT_PERIC1_USI10 21 + +/* CMU_PERIC2 */ +#define CLK_MOUT_PERIC2_IP0_USER 1 +#define CLK_MOUT_PERIC2_IP1_USER 2 +#define CLK_MOUT_PERIC2_NOC_USER 3 +#define CLK_MOUT_PERIC2_I2C 4 +#define CLK_MOUT_PERIC2_SPI_MS_CTRL 5 +#define CLK_MOUT_PERIC2_UART_DBG 6 +#define CLK_MOUT_PERIC2_USI00 7 +#define CLK_MOUT_PERIC2_USI00_SPI_I2C 8 +#define CLK_MOUT_PERIC2_USI01 9 +#define CLK_MOUT_PERIC2_USI01_SPI_I2C 10 +#define CLK_MOUT_PERIC2_USI02 11 +#define CLK_MOUT_PERIC2_USI03 12 +#define CLK_MOUT_PERIC2_USI05 13 +#define CLK_MOUT_PERIC2_USI06 14 +#define CLK_MOUT_PERIC2_USI11 15 + +#define CLK_DOUT_PERIC2_I2C 16 +#define CLK_DOUT_PERIC2_SPI_MS_CTRL 17 +#define CLK_DOUT_PERIC2_UART_DBG 18 +#define CLK_DOUT_PERIC2_USI00 19 +#define CLK_DOUT_PERIC2_USI00_SPI_I2C 20 +#define CLK_DOUT_PERIC2_USI01 21 +#define CLK_DOUT_PERIC2_USI01_SPI_I2C 22 +#define CLK_DOUT_PERIC2_USI02 23 +#define CLK_DOUT_PERIC2_USI03 24 +#define CLK_DOUT_PERIC2_USI05 25 +#define CLK_DOUT_PERIC2_USI06 26 +#define CLK_DOUT_PERIC2_USI11 27 + +/* CMU_UFS */ +#define CLK_MOUT_UFS_MMC_CARD_USER 1 +#define CLK_MOUT_UFS_NOC_USER 2 +#define CLK_MOUT_UFS_UFS_EMBD_USER 3 + +/* CMU_VTS */ +#define CLK_MOUT_CLKALIVE_VTS_NOC_USER 1 +#define CLK_MOUT_CLKALIVE_VTS_RCO_USER 2 +#define CLK_MOUT_CLKCMU_VTS_DMIC_USER 3 +#define CLK_MOUT_CLKVTS_AUD_DMIC1 4 +#define CLK_MOUT_CLKVTS_NOC 5 +#define CLK_MOUT_CLKVTS_DMIC_PAD 6 + +#define CLK_DOUT_CLKVTS_AUD_DMIC0 7 +#define CLK_DOUT_CLKVTS_AUD_DMIC1 8 +#define CLK_DOUT_CLKVTS_CPU 9 +#define CLK_DOUT_CLKVTS_DMIC_IF 10 +#define CLK_DOUT_CLKVTS_DMIC_IF_DIV2 11 +#define CLK_DOUT_CLKVTS_NOC 12 +#define CLK_DOUT_CLKVTS_SERIAL_LIF 13 +#define CLK_DOUT_CLKVTS_SERIAL_LIF_CORE 14 + +#endif diff --git a/include/dt-bindings/clock/samsung,exynos7870-cmu.h b/include/dt-bindings/clock/samsung,exynos7870-cmu.h new file mode 100644 index 000000000000..57d04bbe342d --- /dev/null +++ b/include/dt-bindings/clock/samsung,exynos7870-cmu.h @@ -0,0 +1,324 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (C) 2015 Samsung Electronics Co., Ltd. + * Author: Kaustabh Chakraborty <kauschluss@disroot.org> + * + * Device Tree binding constants for Exynos7870 clock controller. + */ + +#ifndef _DT_BINDINGS_CLOCK_EXYNOS7870_H +#define _DT_BINDINGS_CLOCK_EXYNOS7870_H + +/* CMU_MIF */ +#define CLK_DOUT_MIF_APB 1 +#define CLK_DOUT_MIF_BUSD 2 +#define CLK_DOUT_MIF_CMU_DISPAUD_BUS 3 +#define CLK_DOUT_MIF_CMU_DISPAUD_DECON_ECLK 4 +#define CLK_DOUT_MIF_CMU_DISPAUD_DECON_VCLK 5 +#define CLK_DOUT_MIF_CMU_FSYS_BUS 6 +#define CLK_DOUT_MIF_CMU_FSYS_MMC0 7 +#define CLK_DOUT_MIF_CMU_FSYS_MMC1 8 +#define CLK_DOUT_MIF_CMU_FSYS_MMC2 9 +#define CLK_DOUT_MIF_CMU_FSYS_USB20DRD_REFCLK 10 +#define CLK_DOUT_MIF_CMU_G3D_SWITCH 11 +#define CLK_DOUT_MIF_CMU_ISP_CAM 12 +#define CLK_DOUT_MIF_CMU_ISP_ISP 13 +#define CLK_DOUT_MIF_CMU_ISP_SENSOR0 14 +#define CLK_DOUT_MIF_CMU_ISP_SENSOR1 15 +#define CLK_DOUT_MIF_CMU_ISP_SENSOR2 16 +#define CLK_DOUT_MIF_CMU_ISP_VRA 17 +#define CLK_DOUT_MIF_CMU_MFCMSCL_MFC 18 +#define CLK_DOUT_MIF_CMU_MFCMSCL_MSCL 19 +#define CLK_DOUT_MIF_CMU_PERI_BUS 20 +#define CLK_DOUT_MIF_CMU_PERI_SPI0 21 +#define CLK_DOUT_MIF_CMU_PERI_SPI1 22 +#define CLK_DOUT_MIF_CMU_PERI_SPI2 23 +#define CLK_DOUT_MIF_CMU_PERI_SPI3 24 +#define CLK_DOUT_MIF_CMU_PERI_SPI4 25 +#define CLK_DOUT_MIF_CMU_PERI_UART0 26 +#define CLK_DOUT_MIF_CMU_PERI_UART1 27 +#define CLK_DOUT_MIF_CMU_PERI_UART2 28 +#define CLK_DOUT_MIF_HSI2C 29 +#define CLK_FOUT_MIF_BUS_PLL 30 +#define CLK_FOUT_MIF_MEDIA_PLL 31 +#define CLK_FOUT_MIF_MEM_PLL 32 +#define CLK_GOUT_MIF_CMU_DISPAUD_BUS 33 +#define CLK_GOUT_MIF_CMU_DISPAUD_DECON_ECLK 34 +#define CLK_GOUT_MIF_CMU_DISPAUD_DECON_VCLK 35 +#define CLK_GOUT_MIF_CMU_FSYS_BUS 36 +#define CLK_GOUT_MIF_CMU_FSYS_MMC0 37 +#define CLK_GOUT_MIF_CMU_FSYS_MMC1 38 +#define CLK_GOUT_MIF_CMU_FSYS_MMC2 39 +#define CLK_GOUT_MIF_CMU_FSYS_USB20DRD_REFCLK 40 +#define CLK_GOUT_MIF_CMU_G3D_SWITCH 41 +#define CLK_GOUT_MIF_CMU_ISP_CAM 42 +#define CLK_GOUT_MIF_CMU_ISP_ISP 43 +#define CLK_GOUT_MIF_CMU_ISP_SENSOR0 44 +#define CLK_GOUT_MIF_CMU_ISP_SENSOR1 45 +#define CLK_GOUT_MIF_CMU_ISP_SENSOR2 46 +#define CLK_GOUT_MIF_CMU_ISP_VRA 47 +#define CLK_GOUT_MIF_CMU_MFCMSCL_MFC 48 +#define CLK_GOUT_MIF_CMU_MFCMSCL_MSCL 49 +#define CLK_GOUT_MIF_CMU_PERI_BUS 50 +#define CLK_GOUT_MIF_CMU_PERI_SPI0 51 +#define CLK_GOUT_MIF_CMU_PERI_SPI1 52 +#define CLK_GOUT_MIF_CMU_PERI_SPI2 53 +#define CLK_GOUT_MIF_CMU_PERI_SPI3 54 +#define CLK_GOUT_MIF_CMU_PERI_SPI4 55 +#define CLK_GOUT_MIF_CMU_PERI_UART0 56 +#define CLK_GOUT_MIF_CMU_PERI_UART1 57 +#define CLK_GOUT_MIF_CMU_PERI_UART2 58 +#define CLK_GOUT_MIF_CP_PCLK_HSI2C 59 +#define CLK_GOUT_MIF_CP_PCLK_HSI2C_BAT_0 60 +#define CLK_GOUT_MIF_CP_PCLK_HSI2C_BAT_1 61 +#define CLK_GOUT_MIF_HSI2C_AP_PCLKM 62 +#define CLK_GOUT_MIF_HSI2C_AP_PCLKS 63 +#define CLK_GOUT_MIF_HSI2C_CP_PCLKM 64 +#define CLK_GOUT_MIF_HSI2C_CP_PCLKS 65 +#define CLK_GOUT_MIF_HSI2C_IPCLK 66 +#define CLK_GOUT_MIF_HSI2C_ITCLK 67 +#define CLK_GOUT_MIF_MUX_BUSD 68 +#define CLK_GOUT_MIF_MUX_BUS_PLL 69 +#define CLK_GOUT_MIF_MUX_BUS_PLL_CON 70 +#define CLK_GOUT_MIF_MUX_CMU_DISPAUD_BUS 71 +#define CLK_GOUT_MIF_MUX_CMU_DISPAUD_DECON_ECLK 72 +#define CLK_GOUT_MIF_MUX_CMU_DISPAUD_DECON_VCLK 73 +#define CLK_GOUT_MIF_MUX_CMU_FSYS_BUS 74 +#define CLK_GOUT_MIF_MUX_CMU_FSYS_MMC0 75 +#define CLK_GOUT_MIF_MUX_CMU_FSYS_MMC1 76 +#define CLK_GOUT_MIF_MUX_CMU_FSYS_MMC2 77 +#define CLK_GOUT_MIF_MUX_CMU_FSYS_USB20DRD_REFCLK 78 +#define CLK_GOUT_MIF_MUX_CMU_ISP_CAM 79 +#define CLK_GOUT_MIF_MUX_CMU_ISP_ISP 80 +#define CLK_GOUT_MIF_MUX_CMU_ISP_SENSOR0 81 +#define CLK_GOUT_MIF_MUX_CMU_ISP_SENSOR1 82 +#define CLK_GOUT_MIF_MUX_CMU_ISP_SENSOR2 83 +#define CLK_GOUT_MIF_MUX_CMU_ISP_VRA 84 +#define CLK_GOUT_MIF_MUX_CMU_MFCMSCL_MFC 85 +#define CLK_GOUT_MIF_MUX_CMU_MFCMSCL_MSCL 86 +#define CLK_GOUT_MIF_MUX_CMU_PERI_BUS 87 +#define CLK_GOUT_MIF_MUX_CMU_PERI_SPI0 88 +#define CLK_GOUT_MIF_MUX_CMU_PERI_SPI1 89 +#define CLK_GOUT_MIF_MUX_CMU_PERI_SPI2 90 +#define CLK_GOUT_MIF_MUX_CMU_PERI_SPI3 91 +#define CLK_GOUT_MIF_MUX_CMU_PERI_SPI4 92 +#define CLK_GOUT_MIF_MUX_CMU_PERI_UART0 93 +#define CLK_GOUT_MIF_MUX_CMU_PERI_UART1 94 +#define CLK_GOUT_MIF_MUX_CMU_PERI_UART2 95 +#define CLK_GOUT_MIF_MUX_MEDIA_PLL 96 +#define CLK_GOUT_MIF_MUX_MEDIA_PLL_CON 97 +#define CLK_GOUT_MIF_MUX_MEM_PLL 98 +#define CLK_GOUT_MIF_MUX_MEM_PLL_CON 99 +#define CLK_GOUT_MIF_WRAP_ADC_IF_OSC_SYS 100 +#define CLK_GOUT_MIF_WRAP_ADC_IF_PCLK_S0 101 +#define CLK_GOUT_MIF_WRAP_ADC_IF_PCLK_S1 102 +#define CLK_MOUT_MIF_BUSD 103 +#define CLK_MOUT_MIF_CMU_DISPAUD_BUS 104 +#define CLK_MOUT_MIF_CMU_DISPAUD_DECON_ECLK 105 +#define CLK_MOUT_MIF_CMU_DISPAUD_DECON_VCLK 106 +#define CLK_MOUT_MIF_CMU_FSYS_BUS 107 +#define CLK_MOUT_MIF_CMU_FSYS_MMC0 108 +#define CLK_MOUT_MIF_CMU_FSYS_MMC1 109 +#define CLK_MOUT_MIF_CMU_FSYS_MMC2 110 +#define CLK_MOUT_MIF_CMU_FSYS_USB20DRD_REFCLK 111 +#define CLK_MOUT_MIF_CMU_ISP_CAM 112 +#define CLK_MOUT_MIF_CMU_ISP_ISP 113 +#define CLK_MOUT_MIF_CMU_ISP_SENSOR0 114 +#define CLK_MOUT_MIF_CMU_ISP_SENSOR1 115 +#define CLK_MOUT_MIF_CMU_ISP_SENSOR2 116 +#define CLK_MOUT_MIF_CMU_ISP_VRA 117 +#define CLK_MOUT_MIF_CMU_MFCMSCL_MFC 118 +#define CLK_MOUT_MIF_CMU_MFCMSCL_MSCL 119 +#define CLK_MOUT_MIF_CMU_PERI_BUS 120 +#define CLK_MOUT_MIF_CMU_PERI_SPI0 121 +#define CLK_MOUT_MIF_CMU_PERI_SPI1 122 +#define CLK_MOUT_MIF_CMU_PERI_SPI2 123 +#define CLK_MOUT_MIF_CMU_PERI_SPI3 124 +#define CLK_MOUT_MIF_CMU_PERI_SPI4 125 +#define CLK_MOUT_MIF_CMU_PERI_UART0 126 +#define CLK_MOUT_MIF_CMU_PERI_UART1 127 +#define CLK_MOUT_MIF_CMU_PERI_UART2 128 +#define MIF_NR_CLK 129 + +/* CMU_DISPAUD */ +#define CLK_DOUT_DISPAUD_APB 1 +#define CLK_DOUT_DISPAUD_DECON_ECLK 2 +#define CLK_DOUT_DISPAUD_DECON_VCLK 3 +#define CLK_DOUT_DISPAUD_MI2S 4 +#define CLK_DOUT_DISPAUD_MIXER 5 +#define CLK_FOUT_DISPAUD_AUD_PLL 6 +#define CLK_FOUT_DISPAUD_PLL 7 +#define CLK_GOUT_DISPAUD_APB_AUD 8 +#define CLK_GOUT_DISPAUD_APB_AUD_AMP 9 +#define CLK_GOUT_DISPAUD_APB_DISP 10 +#define CLK_GOUT_DISPAUD_BUS 11 +#define CLK_GOUT_DISPAUD_BUS_DISP 12 +#define CLK_GOUT_DISPAUD_BUS_PPMU 13 +#define CLK_GOUT_DISPAUD_CON_AUD_I2S_BCLK_BT_IN 14 +#define CLK_GOUT_DISPAUD_CON_AUD_I2S_BCLK_FM_IN 15 +#define CLK_GOUT_DISPAUD_CON_CP2AUD_BCK 16 +#define CLK_GOUT_DISPAUD_CON_EXT2AUD_BCK_GPIO_I2S 17 +#define CLK_GOUT_DISPAUD_DECON_ECLK 18 +#define CLK_GOUT_DISPAUD_DECON_VCLK 19 +#define CLK_GOUT_DISPAUD_MI2S_AMP_I2SCODCLKI 20 +#define CLK_GOUT_DISPAUD_MI2S_AUD_I2SCODCLKI 21 +#define CLK_GOUT_DISPAUD_MIXER_AUD_SYSCLK 22 +#define CLK_GOUT_DISPAUD_MUX_AUD_PLL 23 +#define CLK_GOUT_DISPAUD_MUX_AUD_PLL_CON 24 +#define CLK_GOUT_DISPAUD_MUX_BUS_USER 25 +#define CLK_GOUT_DISPAUD_MUX_DECON_ECLK 26 +#define CLK_GOUT_DISPAUD_MUX_DECON_ECLK_USER 27 +#define CLK_GOUT_DISPAUD_MUX_DECON_VCLK 28 +#define CLK_GOUT_DISPAUD_MUX_DECON_VCLK_USER 29 +#define CLK_GOUT_DISPAUD_MUX_MI2S 30 +#define CLK_GOUT_DISPAUD_MUX_MIPIPHY_RXCLKESC0_USER 31 +#define CLK_GOUT_DISPAUD_MUX_MIPIPHY_RXCLKESC0_USER_CON 32 +#define CLK_GOUT_DISPAUD_MUX_MIPIPHY_TXBYTECLKHS_USER 33 +#define CLK_GOUT_DISPAUD_MUX_MIPIPHY_TXBYTECLKHS_USER_CON 34 +#define CLK_GOUT_DISPAUD_MUX_PLL 35 +#define CLK_GOUT_DISPAUD_MUX_PLL_CON 36 +#define CLK_MOUT_DISPAUD_BUS_USER 37 +#define CLK_MOUT_DISPAUD_DECON_ECLK 38 +#define CLK_MOUT_DISPAUD_DECON_ECLK_USER 39 +#define CLK_MOUT_DISPAUD_DECON_VCLK 40 +#define CLK_MOUT_DISPAUD_DECON_VCLK_USER 41 +#define CLK_MOUT_DISPAUD_MI2S 42 +#define DISPAUD_NR_CLK 43 + +/* CMU_FSYS */ +#define CLK_FOUT_FSYS_USB_PLL 1 +#define CLK_GOUT_FSYS_BUSP3_HCLK 2 +#define CLK_GOUT_FSYS_MMC0_ACLK 3 +#define CLK_GOUT_FSYS_MMC1_ACLK 4 +#define CLK_GOUT_FSYS_MMC2_ACLK 5 +#define CLK_GOUT_FSYS_MUX_USB20DRD_PHYCLOCK_USER 6 +#define CLK_GOUT_FSYS_MUX_USB20DRD_PHYCLOCK_USER_CON 7 +#define CLK_GOUT_FSYS_MUX_USB_PLL 8 +#define CLK_GOUT_FSYS_MUX_USB_PLL_CON 9 +#define CLK_GOUT_FSYS_PDMA0_ACLK_PDMA0 10 +#define CLK_GOUT_FSYS_PPMU_ACLK 11 +#define CLK_GOUT_FSYS_PPMU_PCLK 12 +#define CLK_GOUT_FSYS_SROMC_HCLK 13 +#define CLK_GOUT_FSYS_UPSIZER_BUS1_ACLK 14 +#define CLK_GOUT_FSYS_USB20DRD_ACLK_HSDRD 15 +#define CLK_GOUT_FSYS_USB20DRD_HCLK_USB20_CTRL 16 +#define CLK_GOUT_FSYS_USB20DRD_HSDRD_REF_CLK 17 +#define FSYS_NR_CLK 18 + +/* CMU_G3D */ +#define CLK_DOUT_G3D_APB 1 +#define CLK_DOUT_G3D_BUS 2 +#define CLK_FOUT_G3D_PLL 3 +#define CLK_GOUT_G3D_ASYNCS_D0_CLK 4 +#define CLK_GOUT_G3D_ASYNC_PCLKM 5 +#define CLK_GOUT_G3D_CLK 6 +#define CLK_GOUT_G3D_MUX 7 +#define CLK_GOUT_G3D_MUX_PLL 8 +#define CLK_GOUT_G3D_MUX_PLL_CON 9 +#define CLK_GOUT_G3D_MUX_SWITCH_USER 10 +#define CLK_GOUT_G3D_PPMU_ACLK 11 +#define CLK_GOUT_G3D_PPMU_PCLK 12 +#define CLK_GOUT_G3D_QE_ACLK 13 +#define CLK_GOUT_G3D_QE_PCLK 14 +#define CLK_GOUT_G3D_SYSREG_PCLK 15 +#define CLK_MOUT_G3D 16 +#define CLK_MOUT_G3D_SWITCH_USER 17 +#define G3D_NR_CLK 18 + +/* CMU_ISP */ +#define CLK_DOUT_ISP_APB 1 +#define CLK_DOUT_ISP_CAM_HALF 2 +#define CLK_FOUT_ISP_PLL 3 +#define CLK_GOUT_ISP_CAM 4 +#define CLK_GOUT_ISP_CAM_HALF 5 +#define CLK_GOUT_ISP_ISPD 6 +#define CLK_GOUT_ISP_ISPD_PPMU 7 +#define CLK_GOUT_ISP_MUX_CAM 8 +#define CLK_GOUT_ISP_MUX_CAM_USER 9 +#define CLK_GOUT_ISP_MUX_ISP 10 +#define CLK_GOUT_ISP_MUX_ISPD 11 +#define CLK_GOUT_ISP_MUX_PLL 12 +#define CLK_GOUT_ISP_MUX_PLL_CON 13 +#define CLK_GOUT_ISP_MUX_RXBYTECLKHS0_SENSOR0_USER 14 +#define CLK_GOUT_ISP_MUX_RXBYTECLKHS0_SENSOR0_USER_CON 15 +#define CLK_GOUT_ISP_MUX_RXBYTECLKHS0_SENSOR1_USER 16 +#define CLK_GOUT_ISP_MUX_RXBYTECLKHS0_SENSOR1_USER_CON 17 +#define CLK_GOUT_ISP_MUX_USER 18 +#define CLK_GOUT_ISP_MUX_VRA 19 +#define CLK_GOUT_ISP_MUX_VRA_USER 20 +#define CLK_GOUT_ISP_VRA 21 +#define CLK_MOUT_ISP_CAM 22 +#define CLK_MOUT_ISP_CAM_USER 23 +#define CLK_MOUT_ISP_ISP 24 +#define CLK_MOUT_ISP_ISPD 25 +#define CLK_MOUT_ISP_USER 26 +#define CLK_MOUT_ISP_VRA 27 +#define CLK_MOUT_ISP_VRA_USER 28 +#define ISP_NR_CLK 29 + +/* CMU_MFCMSCL */ +#define CLK_DOUT_MFCMSCL_APB 1 +#define CLK_GOUT_MFCMSCL_MFC 2 +#define CLK_GOUT_MFCMSCL_MSCL 3 +#define CLK_GOUT_MFCMSCL_MSCL_BI 4 +#define CLK_GOUT_MFCMSCL_MSCL_D 5 +#define CLK_GOUT_MFCMSCL_MSCL_JPEG 6 +#define CLK_GOUT_MFCMSCL_MSCL_POLY 7 +#define CLK_GOUT_MFCMSCL_MSCL_PPMU 8 +#define CLK_GOUT_MFCMSCL_MUX_MFC_USER 9 +#define CLK_GOUT_MFCMSCL_MUX_MSCL_USER 10 +#define CLK_MOUT_MFCMSCL_MFC_USER 11 +#define CLK_MOUT_MFCMSCL_MSCL_USER 12 +#define MFCMSCL_NR_CLK 13 + +/* CMU_PERI */ +#define CLK_GOUT_PERI_BUSP1_PERIC0_HCLK 1 +#define CLK_GOUT_PERI_GPIO2_PCLK 2 +#define CLK_GOUT_PERI_GPIO5_PCLK 3 +#define CLK_GOUT_PERI_GPIO6_PCLK 4 +#define CLK_GOUT_PERI_GPIO7_PCLK 5 +#define CLK_GOUT_PERI_HSI2C1_IPCLK 6 +#define CLK_GOUT_PERI_HSI2C2_IPCLK 7 +#define CLK_GOUT_PERI_HSI2C3_IPCLK 8 +#define CLK_GOUT_PERI_HSI2C4_IPCLK 9 +#define CLK_GOUT_PERI_HSI2C5_IPCLK 10 +#define CLK_GOUT_PERI_HSI2C6_IPCLK 11 +#define CLK_GOUT_PERI_I2C0_PCLK 12 +#define CLK_GOUT_PERI_I2C1_PCLK 13 +#define CLK_GOUT_PERI_I2C2_PCLK 14 +#define CLK_GOUT_PERI_I2C3_PCLK 15 +#define CLK_GOUT_PERI_I2C4_PCLK 16 +#define CLK_GOUT_PERI_I2C5_PCLK 17 +#define CLK_GOUT_PERI_I2C6_PCLK 18 +#define CLK_GOUT_PERI_I2C7_PCLK 19 +#define CLK_GOUT_PERI_I2C8_PCLK 20 +#define CLK_GOUT_PERI_MCT_PCLK 21 +#define CLK_GOUT_PERI_PWM_MOTOR_OSCCLK 22 +#define CLK_GOUT_PERI_PWM_MOTOR_PCLK_S0 23 +#define CLK_GOUT_PERI_SFRIF_TMU_CPUCL0_PCLK 24 +#define CLK_GOUT_PERI_SFRIF_TMU_CPUCL1_PCLK 25 +#define CLK_GOUT_PERI_SFRIF_TMU_PCLK 26 +#define CLK_GOUT_PERI_SPI0_PCLK 27 +#define CLK_GOUT_PERI_SPI0_SPI_EXT_CLK 28 +#define CLK_GOUT_PERI_SPI1_PCLK 29 +#define CLK_GOUT_PERI_SPI1_SPI_EXT_CLK 30 +#define CLK_GOUT_PERI_SPI2_PCLK 31 +#define CLK_GOUT_PERI_SPI2_SPI_EXT_CLK 32 +#define CLK_GOUT_PERI_SPI3_PCLK 33 +#define CLK_GOUT_PERI_SPI3_SPI_EXT_CLK 34 +#define CLK_GOUT_PERI_SPI4_PCLK 35 +#define CLK_GOUT_PERI_SPI4_SPI_EXT_CLK 36 +#define CLK_GOUT_PERI_TMU_CLK 37 +#define CLK_GOUT_PERI_TMU_CPUCL0_CLK 38 +#define CLK_GOUT_PERI_TMU_CPUCL1_CLK 39 +#define CLK_GOUT_PERI_UART0_EXT_UCLK 40 +#define CLK_GOUT_PERI_UART0_PCLK 41 +#define CLK_GOUT_PERI_UART1_EXT_UCLK 42 +#define CLK_GOUT_PERI_UART1_PCLK 43 +#define CLK_GOUT_PERI_UART2_EXT_UCLK 44 +#define CLK_GOUT_PERI_UART2_PCLK 45 +#define CLK_GOUT_PERI_WDT_CPUCL0_PCLK 46 +#define CLK_GOUT_PERI_WDT_CPUCL1_PCLK 47 +#define PERI_NR_CLK 48 + +#endif /* _DT_BINDINGS_CLOCK_EXYNOS7870_H */ diff --git a/include/dt-bindings/clock/samsung,exynos990.h b/include/dt-bindings/clock/samsung,exynos990.h index 307215a3f3ed..6b9df09d2822 100644 --- a/include/dt-bindings/clock/samsung,exynos990.h +++ b/include/dt-bindings/clock/samsung,exynos990.h @@ -233,4 +233,25 @@ #define CLK_GOUT_HSI0_CMU_HSI0_PCLK 21 #define CLK_GOUT_HSI0_XIU_D_HSI0_ACLK 22 +/* CMU_PERIS */ +#define CLK_MOUT_PERIS_BUS_USER 1 +#define CLK_MOUT_PERIS_CLK_PERIS_GIC 2 +#define CLK_GOUT_PERIS_SYSREG_PERIS_PCLK 3 +#define CLK_GOUT_PERIS_WDT_CLUSTER2_PCLK 4 +#define CLK_GOUT_PERIS_WDT_CLUSTER0_PCLK 5 +#define CLK_CLK_PERIS_PERIS_CMU_PERIS_PCLK 6 +#define CLK_GOUT_PERIS_CLK_PERIS_BUSP_CLK 7 +#define CLK_GOUT_PERIS_CLK_PERIS_OSCCLK_CLK 8 +#define CLK_GOUT_PERIS_CLK_PERIS_GIC_CLK 9 +#define CLK_GOUT_PERIS_AD_AXI_P_PERIS_ACLKM 10 +#define CLK_GOUT_PERIS_OTP_CON_BIRA_PCLK 11 +#define CLK_GOUT_PERIS_GIC_CLK 12 +#define CLK_GOUT_PERIS_LHM_AXI_P_PERIS_CLK 13 +#define CLK_GOUT_PERIS_MCT_PCLK 14 +#define CLK_GOUT_PERIS_OTP_CON_TOP_PCLK 15 +#define CLK_GOUT_PERIS_D_TZPC_PERIS_PCLK 16 +#define CLK_GOUT_PERIS_TMU_TOP_PCLK 17 +#define CLK_GOUT_PERIS_OTP_CON_BIRA_OSCCLK 18 +#define CLK_GOUT_PERIS_OTP_CON_TOP_OSCCLK 19 + #endif diff --git a/include/dt-bindings/clock/samsung,exynosautov920.h b/include/dt-bindings/clock/samsung,exynosautov920.h index 0c681f2ba3d0..93e6233d1358 100644 --- a/include/dt-bindings/clock/samsung,exynosautov920.h +++ b/include/dt-bindings/clock/samsung,exynosautov920.h @@ -162,6 +162,57 @@ #define DOUT_CLKCMU_TAA_NOC 146 #define DOUT_TCXO_DIV2 147 +/* CMU_CPUCL0 */ +#define CLK_FOUT_CPUCL0_PLL 1 + +#define CLK_MOUT_PLL_CPUCL0 2 +#define CLK_MOUT_CPUCL0_CLUSTER_USER 3 +#define CLK_MOUT_CPUCL0_DBG_USER 4 +#define CLK_MOUT_CPUCL0_SWITCH_USER 5 +#define CLK_MOUT_CPUCL0_CLUSTER 6 +#define CLK_MOUT_CPUCL0_CORE 7 + +#define CLK_DOUT_CLUSTER0_ACLK 8 +#define CLK_DOUT_CLUSTER0_ATCLK 9 +#define CLK_DOUT_CLUSTER0_MPCLK 10 +#define CLK_DOUT_CLUSTER0_PCLK 11 +#define CLK_DOUT_CLUSTER0_PERIPHCLK 12 +#define CLK_DOUT_CPUCL0_DBG_NOC 13 +#define CLK_DOUT_CPUCL0_DBG_PCLKDBG 14 +#define CLK_DOUT_CPUCL0_NOCP 15 + +/* CMU_CPUCL1 */ +#define CLK_FOUT_CPUCL1_PLL 1 + +#define CLK_MOUT_PLL_CPUCL1 2 +#define CLK_MOUT_CPUCL1_CLUSTER_USER 3 +#define CLK_MOUT_CPUCL1_SWITCH_USER 4 +#define CLK_MOUT_CPUCL1_CLUSTER 5 +#define CLK_MOUT_CPUCL1_CORE 6 + +#define CLK_DOUT_CLUSTER1_ACLK 7 +#define CLK_DOUT_CLUSTER1_ATCLK 8 +#define CLK_DOUT_CLUSTER1_MPCLK 9 +#define CLK_DOUT_CLUSTER1_PCLK 10 +#define CLK_DOUT_CLUSTER1_PERIPHCLK 11 +#define CLK_DOUT_CPUCL1_NOCP 12 + +/* CMU_CPUCL2 */ +#define CLK_FOUT_CPUCL2_PLL 1 + +#define CLK_MOUT_PLL_CPUCL2 2 +#define CLK_MOUT_CPUCL2_CLUSTER_USER 3 +#define CLK_MOUT_CPUCL2_SWITCH_USER 4 +#define CLK_MOUT_CPUCL2_CLUSTER 5 +#define CLK_MOUT_CPUCL2_CORE 6 + +#define CLK_DOUT_CLUSTER2_ACLK 7 +#define CLK_DOUT_CLUSTER2_ATCLK 8 +#define CLK_DOUT_CLUSTER2_MPCLK 9 +#define CLK_DOUT_CLUSTER2_PCLK 10 +#define CLK_DOUT_CLUSTER2_PERIPHCLK 11 +#define CLK_DOUT_CPUCL2_NOCP 12 + /* CMU_PERIC0 */ #define CLK_MOUT_PERIC0_IP_USER 1 #define CLK_MOUT_PERIC0_NOC_USER 2 @@ -235,4 +286,13 @@ #define CLK_MOUT_HSI1_USBDRD_USER 3 #define CLK_MOUT_HSI1_USBDRD 4 +/* CMU_HSI2 */ +#define FOUT_PLL_ETH 1 +#define CLK_MOUT_HSI2_NOC_UFS_USER 2 +#define CLK_MOUT_HSI2_UFS_EMBD_USER 3 +#define CLK_MOUT_HSI2_ETHERNET 4 +#define CLK_MOUT_HSI2_ETHERNET_USER 5 +#define CLK_DOUT_HSI2_ETHERNET 6 +#define CLK_DOUT_HSI2_ETHERNET_PTP 7 + #endif /* _DT_BINDINGS_CLOCK_EXYNOSAUTOV920_H */ diff --git a/include/dt-bindings/clock/sophgo,sg2044-clk.h b/include/dt-bindings/clock/sophgo,sg2044-clk.h new file mode 100644 index 000000000000..d9adca42548e --- /dev/null +++ b/include/dt-bindings/clock/sophgo,sg2044-clk.h @@ -0,0 +1,153 @@ +/* SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause */ +/* + * Copyright (C) 2024 Inochi Amaoto <inochiama@gmail.com> + */ + +#ifndef __DT_BINDINGS_SOPHGO_SG2044_CLK_H__ +#define __DT_BINDINGS_SOPHGO_SG2044_CLK_H__ + +#define CLK_DIV_AP_SYS_FIXED 0 +#define CLK_DIV_AP_SYS_MAIN 1 +#define CLK_DIV_RP_SYS_FIXED 2 +#define CLK_DIV_RP_SYS_MAIN 3 +#define CLK_DIV_TPU_SYS_FIXED 4 +#define CLK_DIV_TPU_SYS_MAIN 5 +#define CLK_DIV_NOC_SYS_FIXED 6 +#define CLK_DIV_NOC_SYS_MAIN 7 +#define CLK_DIV_VC_SRC0_FIXED 8 +#define CLK_DIV_VC_SRC0_MAIN 9 +#define CLK_DIV_VC_SRC1_FIXED 10 +#define CLK_DIV_VC_SRC1_MAIN 11 +#define CLK_DIV_CXP_MAC_FIXED 12 +#define CLK_DIV_CXP_MAC_MAIN 13 +#define CLK_DIV_DDR0_FIXED 14 +#define CLK_DIV_DDR0_MAIN 15 +#define CLK_DIV_DDR1_FIXED 16 +#define CLK_DIV_DDR1_MAIN 17 +#define CLK_DIV_DDR2_FIXED 18 +#define CLK_DIV_DDR2_MAIN 19 +#define CLK_DIV_DDR3_FIXED 20 +#define CLK_DIV_DDR3_MAIN 21 +#define CLK_DIV_DDR4_FIXED 22 +#define CLK_DIV_DDR4_MAIN 23 +#define CLK_DIV_DDR5_FIXED 24 +#define CLK_DIV_DDR5_MAIN 25 +#define CLK_DIV_DDR6_FIXED 26 +#define CLK_DIV_DDR6_MAIN 27 +#define CLK_DIV_DDR7_FIXED 28 +#define CLK_DIV_DDR7_MAIN 29 +#define CLK_DIV_TOP_50M 30 +#define CLK_DIV_TOP_AXI0 31 +#define CLK_DIV_TOP_AXI_HSPERI 32 +#define CLK_DIV_TIMER0 33 +#define CLK_DIV_TIMER1 34 +#define CLK_DIV_TIMER2 35 +#define CLK_DIV_TIMER3 36 +#define CLK_DIV_TIMER4 37 +#define CLK_DIV_TIMER5 38 +#define CLK_DIV_TIMER6 39 +#define CLK_DIV_TIMER7 40 +#define CLK_DIV_CXP_TEST_PHY 41 +#define CLK_DIV_CXP_TEST_ETH_PHY 42 +#define CLK_DIV_C2C0_TEST_PHY 43 +#define CLK_DIV_C2C1_TEST_PHY 44 +#define CLK_DIV_PCIE_1G 45 +#define CLK_DIV_UART_500M 46 +#define CLK_DIV_GPIO_DB 47 +#define CLK_DIV_SD 48 +#define CLK_DIV_SD_100K 49 +#define CLK_DIV_EMMC 50 +#define CLK_DIV_EMMC_100K 51 +#define CLK_DIV_EFUSE 52 +#define CLK_DIV_TX_ETH0 53 +#define CLK_DIV_PTP_REF_I_ETH0 54 +#define CLK_DIV_REF_ETH0 55 +#define CLK_DIV_PKA 56 +#define CLK_MUX_DDR0 57 +#define CLK_MUX_DDR1 58 +#define CLK_MUX_DDR2 59 +#define CLK_MUX_DDR3 60 +#define CLK_MUX_DDR4 61 +#define CLK_MUX_DDR5 62 +#define CLK_MUX_DDR6 63 +#define CLK_MUX_DDR7 64 +#define CLK_MUX_NOC_SYS 65 +#define CLK_MUX_TPU_SYS 66 +#define CLK_MUX_RP_SYS 67 +#define CLK_MUX_AP_SYS 68 +#define CLK_MUX_VC_SRC0 69 +#define CLK_MUX_VC_SRC1 70 +#define CLK_MUX_CXP_MAC 71 +#define CLK_GATE_AP_SYS 72 +#define CLK_GATE_RP_SYS 73 +#define CLK_GATE_TPU_SYS 74 +#define CLK_GATE_NOC_SYS 75 +#define CLK_GATE_VC_SRC0 76 +#define CLK_GATE_VC_SRC1 77 +#define CLK_GATE_DDR0 78 +#define CLK_GATE_DDR1 79 +#define CLK_GATE_DDR2 80 +#define CLK_GATE_DDR3 81 +#define CLK_GATE_DDR4 82 +#define CLK_GATE_DDR5 83 +#define CLK_GATE_DDR6 84 +#define CLK_GATE_DDR7 85 +#define CLK_GATE_TOP_50M 86 +#define CLK_GATE_SC_RX 87 +#define CLK_GATE_SC_RX_X0Y1 88 +#define CLK_GATE_TOP_AXI0 89 +#define CLK_GATE_INTC0 90 +#define CLK_GATE_INTC1 91 +#define CLK_GATE_INTC2 92 +#define CLK_GATE_INTC3 93 +#define CLK_GATE_MAILBOX0 94 +#define CLK_GATE_MAILBOX1 95 +#define CLK_GATE_MAILBOX2 96 +#define CLK_GATE_MAILBOX3 97 +#define CLK_GATE_TOP_AXI_HSPERI 98 +#define CLK_GATE_APB_TIMER 99 +#define CLK_GATE_TIMER0 100 +#define CLK_GATE_TIMER1 101 +#define CLK_GATE_TIMER2 102 +#define CLK_GATE_TIMER3 103 +#define CLK_GATE_TIMER4 104 +#define CLK_GATE_TIMER5 105 +#define CLK_GATE_TIMER6 106 +#define CLK_GATE_TIMER7 107 +#define CLK_GATE_CXP_CFG 108 +#define CLK_GATE_CXP_MAC 109 +#define CLK_GATE_CXP_TEST_PHY 110 +#define CLK_GATE_CXP_TEST_ETH_PHY 111 +#define CLK_GATE_PCIE_1G 112 +#define CLK_GATE_C2C0_TEST_PHY 113 +#define CLK_GATE_C2C1_TEST_PHY 114 +#define CLK_GATE_UART_500M 115 +#define CLK_GATE_APB_UART 116 +#define CLK_GATE_APB_SPI 117 +#define CLK_GATE_AHB_SPIFMC 118 +#define CLK_GATE_APB_I2C 119 +#define CLK_GATE_AXI_DBG_I2C 120 +#define CLK_GATE_GPIO_DB 121 +#define CLK_GATE_APB_GPIO_INTR 122 +#define CLK_GATE_APB_GPIO 123 +#define CLK_GATE_SD 124 +#define CLK_GATE_AXI_SD 125 +#define CLK_GATE_SD_100K 126 +#define CLK_GATE_EMMC 127 +#define CLK_GATE_AXI_EMMC 128 +#define CLK_GATE_EMMC_100K 129 +#define CLK_GATE_EFUSE 130 +#define CLK_GATE_APB_EFUSE 131 +#define CLK_GATE_SYSDMA_AXI 132 +#define CLK_GATE_TX_ETH0 133 +#define CLK_GATE_AXI_ETH0 134 +#define CLK_GATE_PTP_REF_I_ETH0 135 +#define CLK_GATE_REF_ETH0 136 +#define CLK_GATE_APB_RTC 137 +#define CLK_GATE_APB_PWM 138 +#define CLK_GATE_APB_WDT 139 +#define CLK_GATE_AXI_SRAM 140 +#define CLK_GATE_AHB_ROM 141 +#define CLK_GATE_PKA 142 + +#endif /* __DT_BINDINGS_SOPHGO_SG2044_CLK_H__ */ diff --git a/include/dt-bindings/clock/sophgo,sg2044-pll.h b/include/dt-bindings/clock/sophgo,sg2044-pll.h new file mode 100644 index 000000000000..817d45e700cc --- /dev/null +++ b/include/dt-bindings/clock/sophgo,sg2044-pll.h @@ -0,0 +1,27 @@ +/* SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause */ +/* + * Copyright (C) 2024 Inochi Amaoto <inochiama@gmail.com> + */ + +#ifndef __DT_BINDINGS_SOPHGO_SG2044_PLL_H__ +#define __DT_BINDINGS_SOPHGO_SG2044_PLL_H__ + +#define CLK_FPLL0 0 +#define CLK_FPLL1 1 +#define CLK_FPLL2 2 +#define CLK_DPLL0 3 +#define CLK_DPLL1 4 +#define CLK_DPLL2 5 +#define CLK_DPLL3 6 +#define CLK_DPLL4 7 +#define CLK_DPLL5 8 +#define CLK_DPLL6 9 +#define CLK_DPLL7 10 +#define CLK_MPLL0 11 +#define CLK_MPLL1 12 +#define CLK_MPLL2 13 +#define CLK_MPLL3 14 +#define CLK_MPLL4 15 +#define CLK_MPLL5 16 + +#endif /* __DT_BINDINGS_SOPHGO_SG2044_PLL_H__ */ diff --git a/include/dt-bindings/clock/spacemit,k1-syscon.h b/include/dt-bindings/clock/spacemit,k1-syscon.h new file mode 100644 index 000000000000..2714c3fe66cd --- /dev/null +++ b/include/dt-bindings/clock/spacemit,k1-syscon.h @@ -0,0 +1,388 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (C) 2024-2025 Haylen Chu <heylenay@outlook.com> + */ + +#ifndef _DT_BINDINGS_SPACEMIT_CCU_H_ +#define _DT_BINDINGS_SPACEMIT_CCU_H_ + +/* APBS (PLL) clocks */ +#define CLK_PLL1 0 +#define CLK_PLL2 1 +#define CLK_PLL3 2 +#define CLK_PLL1_D2 3 +#define CLK_PLL1_D3 4 +#define CLK_PLL1_D4 5 +#define CLK_PLL1_D5 6 +#define CLK_PLL1_D6 7 +#define CLK_PLL1_D7 8 +#define CLK_PLL1_D8 9 +#define CLK_PLL1_D11 10 +#define CLK_PLL1_D13 11 +#define CLK_PLL1_D23 12 +#define CLK_PLL1_D64 13 +#define CLK_PLL1_D10_AUD 14 +#define CLK_PLL1_D100_AUD 15 +#define CLK_PLL2_D1 16 +#define CLK_PLL2_D2 17 +#define CLK_PLL2_D3 18 +#define CLK_PLL2_D4 19 +#define CLK_PLL2_D5 20 +#define CLK_PLL2_D6 21 +#define CLK_PLL2_D7 22 +#define CLK_PLL2_D8 23 +#define CLK_PLL3_D1 24 +#define CLK_PLL3_D2 25 +#define CLK_PLL3_D3 26 +#define CLK_PLL3_D4 27 +#define CLK_PLL3_D5 28 +#define CLK_PLL3_D6 29 +#define CLK_PLL3_D7 30 +#define CLK_PLL3_D8 31 +#define CLK_PLL3_80 32 +#define CLK_PLL3_40 33 +#define CLK_PLL3_20 34 + +/* MPMU clocks */ +#define CLK_PLL1_307P2 0 +#define CLK_PLL1_76P8 1 +#define CLK_PLL1_61P44 2 +#define CLK_PLL1_153P6 3 +#define CLK_PLL1_102P4 4 +#define CLK_PLL1_51P2 5 +#define CLK_PLL1_51P2_AP 6 +#define CLK_PLL1_57P6 7 +#define CLK_PLL1_25P6 8 +#define CLK_PLL1_12P8 9 +#define CLK_PLL1_12P8_WDT 10 +#define CLK_PLL1_6P4 11 +#define CLK_PLL1_3P2 12 +#define CLK_PLL1_1P6 13 +#define CLK_PLL1_0P8 14 +#define CLK_PLL1_409P6 15 +#define CLK_PLL1_204P8 16 +#define CLK_PLL1_491 17 +#define CLK_PLL1_245P76 18 +#define CLK_PLL1_614 19 +#define CLK_PLL1_47P26 20 +#define CLK_PLL1_31P5 21 +#define CLK_PLL1_819 22 +#define CLK_PLL1_1228 23 +#define CLK_SLOW_UART 24 +#define CLK_SLOW_UART1 25 +#define CLK_SLOW_UART2 26 +#define CLK_WDT 27 +#define CLK_RIPC 28 +#define CLK_I2S_SYSCLK 29 +#define CLK_I2S_BCLK 30 +#define CLK_APB 31 +#define CLK_WDT_BUS 32 + +/* MPMU resets */ +#define RESET_WDT 0 + +/* APBC clocks */ +#define CLK_UART0 0 +#define CLK_UART2 1 +#define CLK_UART3 2 +#define CLK_UART4 3 +#define CLK_UART5 4 +#define CLK_UART6 5 +#define CLK_UART7 6 +#define CLK_UART8 7 +#define CLK_UART9 8 +#define CLK_GPIO 9 +#define CLK_PWM0 10 +#define CLK_PWM1 11 +#define CLK_PWM2 12 +#define CLK_PWM3 13 +#define CLK_PWM4 14 +#define CLK_PWM5 15 +#define CLK_PWM6 16 +#define CLK_PWM7 17 +#define CLK_PWM8 18 +#define CLK_PWM9 19 +#define CLK_PWM10 20 +#define CLK_PWM11 21 +#define CLK_PWM12 22 +#define CLK_PWM13 23 +#define CLK_PWM14 24 +#define CLK_PWM15 25 +#define CLK_PWM16 26 +#define CLK_PWM17 27 +#define CLK_PWM18 28 +#define CLK_PWM19 29 +#define CLK_SSP3 30 +#define CLK_RTC 31 +#define CLK_TWSI0 32 +#define CLK_TWSI1 33 +#define CLK_TWSI2 34 +#define CLK_TWSI4 35 +#define CLK_TWSI5 36 +#define CLK_TWSI6 37 +#define CLK_TWSI7 38 +#define CLK_TWSI8 39 +#define CLK_TIMERS1 40 +#define CLK_TIMERS2 41 +#define CLK_AIB 42 +#define CLK_ONEWIRE 43 +#define CLK_SSPA0 44 +#define CLK_SSPA1 45 +#define CLK_DRO 46 +#define CLK_IR 47 +#define CLK_TSEN 48 +#define CLK_IPC_AP2AUD 49 +#define CLK_CAN0 50 +#define CLK_CAN0_BUS 51 +#define CLK_UART0_BUS 52 +#define CLK_UART2_BUS 53 +#define CLK_UART3_BUS 54 +#define CLK_UART4_BUS 55 +#define CLK_UART5_BUS 56 +#define CLK_UART6_BUS 57 +#define CLK_UART7_BUS 58 +#define CLK_UART8_BUS 59 +#define CLK_UART9_BUS 60 +#define CLK_GPIO_BUS 61 +#define CLK_PWM0_BUS 62 +#define CLK_PWM1_BUS 63 +#define CLK_PWM2_BUS 64 +#define CLK_PWM3_BUS 65 +#define CLK_PWM4_BUS 66 +#define CLK_PWM5_BUS 67 +#define CLK_PWM6_BUS 68 +#define CLK_PWM7_BUS 69 +#define CLK_PWM8_BUS 70 +#define CLK_PWM9_BUS 71 +#define CLK_PWM10_BUS 72 +#define CLK_PWM11_BUS 73 +#define CLK_PWM12_BUS 74 +#define CLK_PWM13_BUS 75 +#define CLK_PWM14_BUS 76 +#define CLK_PWM15_BUS 77 +#define CLK_PWM16_BUS 78 +#define CLK_PWM17_BUS 79 +#define CLK_PWM18_BUS 80 +#define CLK_PWM19_BUS 81 +#define CLK_SSP3_BUS 82 +#define CLK_RTC_BUS 83 +#define CLK_TWSI0_BUS 84 +#define CLK_TWSI1_BUS 85 +#define CLK_TWSI2_BUS 86 +#define CLK_TWSI4_BUS 87 +#define CLK_TWSI5_BUS 88 +#define CLK_TWSI6_BUS 89 +#define CLK_TWSI7_BUS 90 +#define CLK_TWSI8_BUS 91 +#define CLK_TIMERS1_BUS 92 +#define CLK_TIMERS2_BUS 93 +#define CLK_AIB_BUS 94 +#define CLK_ONEWIRE_BUS 95 +#define CLK_SSPA0_BUS 96 +#define CLK_SSPA1_BUS 97 +#define CLK_TSEN_BUS 98 +#define CLK_IPC_AP2AUD_BUS 99 + +/* APBC resets */ +#define RESET_UART0 0 +#define RESET_UART2 1 +#define RESET_UART3 2 +#define RESET_UART4 3 +#define RESET_UART5 4 +#define RESET_UART6 5 +#define RESET_UART7 6 +#define RESET_UART8 7 +#define RESET_UART9 8 +#define RESET_GPIO 9 +#define RESET_PWM0 10 +#define RESET_PWM1 11 +#define RESET_PWM2 12 +#define RESET_PWM3 13 +#define RESET_PWM4 14 +#define RESET_PWM5 15 +#define RESET_PWM6 16 +#define RESET_PWM7 17 +#define RESET_PWM8 18 +#define RESET_PWM9 19 +#define RESET_PWM10 20 +#define RESET_PWM11 21 +#define RESET_PWM12 22 +#define RESET_PWM13 23 +#define RESET_PWM14 24 +#define RESET_PWM15 25 +#define RESET_PWM16 26 +#define RESET_PWM17 27 +#define RESET_PWM18 28 +#define RESET_PWM19 29 +#define RESET_SSP3 30 +#define RESET_RTC 31 +#define RESET_TWSI0 32 +#define RESET_TWSI1 33 +#define RESET_TWSI2 34 +#define RESET_TWSI4 35 +#define RESET_TWSI5 36 +#define RESET_TWSI6 37 +#define RESET_TWSI7 38 +#define RESET_TWSI8 39 +#define RESET_TIMERS1 40 +#define RESET_TIMERS2 41 +#define RESET_AIB 42 +#define RESET_ONEWIRE 43 +#define RESET_SSPA0 44 +#define RESET_SSPA1 45 +#define RESET_DRO 46 +#define RESET_IR 47 +#define RESET_TSEN 48 +#define RESET_IPC_AP2AUD 49 +#define RESET_CAN0 50 + +/* APMU clocks */ +#define CLK_CCI550 0 +#define CLK_CPU_C0_HI 1 +#define CLK_CPU_C0_CORE 2 +#define CLK_CPU_C0_ACE 3 +#define CLK_CPU_C0_TCM 4 +#define CLK_CPU_C1_HI 5 +#define CLK_CPU_C1_CORE 6 +#define CLK_CPU_C1_ACE 7 +#define CLK_CCIC_4X 8 +#define CLK_CCIC1PHY 9 +#define CLK_SDH_AXI 10 +#define CLK_SDH0 11 +#define CLK_SDH1 12 +#define CLK_SDH2 13 +#define CLK_USB_P1 14 +#define CLK_USB_AXI 15 +#define CLK_USB30 16 +#define CLK_QSPI 17 +#define CLK_QSPI_BUS 18 +#define CLK_DMA 19 +#define CLK_AES 20 +#define CLK_VPU 21 +#define CLK_GPU 22 +#define CLK_EMMC 23 +#define CLK_EMMC_X 24 +#define CLK_AUDIO 25 +#define CLK_HDMI 26 +#define CLK_PMUA_ACLK 27 +#define CLK_PCIE0_MASTER 28 +#define CLK_PCIE0_SLAVE 29 +#define CLK_PCIE0_DBI 30 +#define CLK_PCIE1_MASTER 31 +#define CLK_PCIE1_SLAVE 32 +#define CLK_PCIE1_DBI 33 +#define CLK_PCIE2_MASTER 34 +#define CLK_PCIE2_SLAVE 35 +#define CLK_PCIE2_DBI 36 +#define CLK_EMAC0_BUS 37 +#define CLK_EMAC0_PTP 38 +#define CLK_EMAC1_BUS 39 +#define CLK_EMAC1_PTP 40 +#define CLK_JPG 41 +#define CLK_CCIC2PHY 42 +#define CLK_CCIC3PHY 43 +#define CLK_CSI 44 +#define CLK_CAMM0 45 +#define CLK_CAMM1 46 +#define CLK_CAMM2 47 +#define CLK_ISP_CPP 48 +#define CLK_ISP_BUS 49 +#define CLK_ISP 50 +#define CLK_DPU_MCLK 51 +#define CLK_DPU_ESC 52 +#define CLK_DPU_BIT 53 +#define CLK_DPU_PXCLK 54 +#define CLK_DPU_HCLK 55 +#define CLK_DPU_SPI 56 +#define CLK_DPU_SPI_HBUS 57 +#define CLK_DPU_SPIBUS 58 +#define CLK_DPU_SPI_ACLK 59 +#define CLK_V2D 60 +#define CLK_EMMC_BUS 61 + +/* APMU resets */ +#define RESET_CCIC_4X 0 +#define RESET_CCIC1_PHY 1 +#define RESET_SDH_AXI 2 +#define RESET_SDH0 3 +#define RESET_SDH1 4 +#define RESET_SDH2 5 +#define RESET_USBP1_AXI 6 +#define RESET_USB_AXI 7 +#define RESET_USB30_AHB 8 +#define RESET_USB30_VCC 9 +#define RESET_USB30_PHY 10 +#define RESET_QSPI 11 +#define RESET_QSPI_BUS 12 +#define RESET_DMA 13 +#define RESET_AES 14 +#define RESET_VPU 15 +#define RESET_GPU 16 +#define RESET_EMMC 17 +#define RESET_EMMC_X 18 +#define RESET_AUDIO_SYS 19 +#define RESET_AUDIO_MCU 20 +#define RESET_AUDIO_APMU 21 +#define RESET_HDMI 22 +#define RESET_PCIE0_MASTER 23 +#define RESET_PCIE0_SLAVE 24 +#define RESET_PCIE0_DBI 25 +#define RESET_PCIE0_GLOBAL 26 +#define RESET_PCIE1_MASTER 27 +#define RESET_PCIE1_SLAVE 28 +#define RESET_PCIE1_DBI 29 +#define RESET_PCIE1_GLOBAL 30 +#define RESET_PCIE2_MASTER 31 +#define RESET_PCIE2_SLAVE 32 +#define RESET_PCIE2_DBI 33 +#define RESET_PCIE2_GLOBAL 34 +#define RESET_EMAC0 35 +#define RESET_EMAC1 36 +#define RESET_JPG 37 +#define RESET_CCIC2PHY 38 +#define RESET_CCIC3PHY 39 +#define RESET_CSI 40 +#define RESET_ISP_CPP 41 +#define RESET_ISP_BUS 42 +#define RESET_ISP 43 +#define RESET_ISP_CI 44 +#define RESET_DPU_MCLK 45 +#define RESET_DPU_ESC 46 +#define RESET_DPU_HCLK 47 +#define RESET_DPU_SPIBUS 48 +#define RESET_DPU_SPI_HBUS 49 +#define RESET_V2D 50 +#define RESET_MIPI 51 +#define RESET_MC 52 + +/* RCPU resets */ +#define RESET_RCPU_SSP0 0 +#define RESET_RCPU_I2C0 1 +#define RESET_RCPU_UART1 2 +#define RESET_RCPU_IR 3 +#define RESET_RCPU_CAN 4 +#define RESET_RCPU_UART0 5 +#define RESET_RCPU_HDMI_AUDIO 6 + +/* RCPU2 resets */ +#define RESET_RCPU2_PWM0 0 +#define RESET_RCPU2_PWM1 1 +#define RESET_RCPU2_PWM2 2 +#define RESET_RCPU2_PWM3 3 +#define RESET_RCPU2_PWM4 4 +#define RESET_RCPU2_PWM5 5 +#define RESET_RCPU2_PWM6 6 +#define RESET_RCPU2_PWM7 7 +#define RESET_RCPU2_PWM8 8 +#define RESET_RCPU2_PWM9 9 + +/* APBC2 resets */ +#define RESET_APBC2_UART1 0 +#define RESET_APBC2_SSP2 1 +#define RESET_APBC2_TWSI3 2 +#define RESET_APBC2_RTC 3 +#define RESET_APBC2_TIMERS0 4 +#define RESET_APBC2_KPC 5 +#define RESET_APBC2_GPIO 6 + +#endif /* _DT_BINDINGS_SPACEMIT_CCU_H_ */ diff --git a/include/dt-bindings/clock/stm32h7-clks.h b/include/dt-bindings/clock/stm32h7-clks.h index 6637272b3242..330b39c2c303 100644 --- a/include/dt-bindings/clock/stm32h7-clks.h +++ b/include/dt-bindings/clock/stm32h7-clks.h @@ -126,8 +126,8 @@ #define ADC3_CK 128 #define DSI_CK 129 #define LTDC_CK 130 -#define USART8_CK 131 -#define USART7_CK 132 +#define UART8_CK 131 +#define UART7_CK 132 #define HDMICEC_CK 133 #define I2C3_CK 134 #define I2C2_CK 135 diff --git a/include/dt-bindings/clock/sun50i-h616-ccu.h b/include/dt-bindings/clock/sun50i-h616-ccu.h index ebb146ab7f8c..6889405f9fec 100644 --- a/include/dt-bindings/clock/sun50i-h616-ccu.h +++ b/include/dt-bindings/clock/sun50i-h616-ccu.h @@ -113,5 +113,9 @@ #define CLK_BUS_HDCP 127 #define CLK_PLL_SYSTEM_32K 128 #define CLK_BUS_GPADC 129 +#define CLK_TCON_LCD0 130 +#define CLK_BUS_TCON_LCD0 131 +#define CLK_TCON_LCD1 132 +#define CLK_BUS_TCON_LCD1 133 #endif /* _DT_BINDINGS_CLK_SUN50I_H616_H_ */ diff --git a/include/dt-bindings/clock/sun55i-a523-ccu.h b/include/dt-bindings/clock/sun55i-a523-ccu.h new file mode 100644 index 000000000000..c8259ac5ada7 --- /dev/null +++ b/include/dt-bindings/clock/sun55i-a523-ccu.h @@ -0,0 +1,189 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */ +/* + * Copyright (C) 2024 Arm Ltd. + */ + +#ifndef _DT_BINDINGS_CLK_SUN55I_A523_CCU_H_ +#define _DT_BINDINGS_CLK_SUN55I_A523_CCU_H_ + +#define CLK_PLL_DDR0 0 +#define CLK_PLL_PERIPH0_4X 1 +#define CLK_PLL_PERIPH0_2X 2 +#define CLK_PLL_PERIPH0_800M 3 +#define CLK_PLL_PERIPH0_480M 4 +#define CLK_PLL_PERIPH0_600M 5 +#define CLK_PLL_PERIPH0_400M 6 +#define CLK_PLL_PERIPH0_300M 7 +#define CLK_PLL_PERIPH0_200M 8 +#define CLK_PLL_PERIPH0_160M 9 +#define CLK_PLL_PERIPH0_150M 10 +#define CLK_PLL_PERIPH1_4X 11 +#define CLK_PLL_PERIPH1_2X 12 +#define CLK_PLL_PERIPH1_800M 13 +#define CLK_PLL_PERIPH1_480M 14 +#define CLK_PLL_PERIPH1_600M 15 +#define CLK_PLL_PERIPH1_400M 16 +#define CLK_PLL_PERIPH1_300M 17 +#define CLK_PLL_PERIPH1_200M 18 +#define CLK_PLL_PERIPH1_160M 19 +#define CLK_PLL_PERIPH1_150M 20 +#define CLK_PLL_GPU 21 +#define CLK_PLL_VIDEO0_8X 22 +#define CLK_PLL_VIDEO0_4X 23 +#define CLK_PLL_VIDEO0_3X 24 +#define CLK_PLL_VIDEO1_8X 25 +#define CLK_PLL_VIDEO1_4X 26 +#define CLK_PLL_VIDEO1_3X 27 +#define CLK_PLL_VIDEO2_8X 28 +#define CLK_PLL_VIDEO2_4X 29 +#define CLK_PLL_VIDEO2_3X 30 +#define CLK_PLL_VIDEO3_8X 31 +#define CLK_PLL_VIDEO3_4X 32 +#define CLK_PLL_VIDEO3_3X 33 +#define CLK_PLL_VE 34 +#define CLK_PLL_AUDIO0_4X 35 +#define CLK_PLL_AUDIO0_2X 36 +#define CLK_PLL_AUDIO0 37 +#define CLK_PLL_NPU_4X 38 +#define CLK_PLL_NPU_2X 39 +#define CLK_PLL_NPU 40 +#define CLK_AHB 41 +#define CLK_APB0 42 +#define CLK_APB1 43 +#define CLK_MBUS 44 +#define CLK_DE 45 +#define CLK_BUS_DE 46 +#define CLK_DI 47 +#define CLK_BUS_DI 48 +#define CLK_G2D 49 +#define CLK_BUS_G2D 50 +#define CLK_GPU 51 +#define CLK_BUS_GPU 52 +#define CLK_CE 53 +#define CLK_BUS_CE 54 +#define CLK_BUS_CE_SYS 55 +#define CLK_VE 56 +#define CLK_BUS_VE 57 +#define CLK_BUS_DMA 58 +#define CLK_BUS_MSGBOX 59 +#define CLK_BUS_SPINLOCK 60 +#define CLK_HSTIMER0 61 +#define CLK_HSTIMER1 62 +#define CLK_HSTIMER2 63 +#define CLK_HSTIMER3 64 +#define CLK_HSTIMER4 65 +#define CLK_HSTIMER5 66 +#define CLK_BUS_HSTIMER 67 +#define CLK_BUS_DBG 68 +#define CLK_BUS_PWM0 69 +#define CLK_BUS_PWM1 70 +#define CLK_IOMMU 71 +#define CLK_BUS_IOMMU 72 +#define CLK_DRAM 73 +#define CLK_MBUS_DMA 74 +#define CLK_MBUS_VE 75 +#define CLK_MBUS_CE 76 +#define CLK_MBUS_CSI 77 +#define CLK_MBUS_ISP 78 +#define CLK_MBUS_EMAC1 79 +#define CLK_BUS_DRAM 80 +#define CLK_NAND0 81 +#define CLK_NAND1 82 +#define CLK_BUS_NAND 83 +#define CLK_MMC0 84 +#define CLK_MMC1 85 +#define CLK_MMC2 86 +#define CLK_BUS_SYSDAP 87 +#define CLK_BUS_MMC0 88 +#define CLK_BUS_MMC1 89 +#define CLK_BUS_MMC2 90 +#define CLK_BUS_UART0 91 +#define CLK_BUS_UART1 92 +#define CLK_BUS_UART2 93 +#define CLK_BUS_UART3 94 +#define CLK_BUS_UART4 95 +#define CLK_BUS_UART5 96 +#define CLK_BUS_UART6 97 +#define CLK_BUS_UART7 98 +#define CLK_BUS_I2C0 99 +#define CLK_BUS_I2C1 100 +#define CLK_BUS_I2C2 101 +#define CLK_BUS_I2C3 102 +#define CLK_BUS_I2C4 103 +#define CLK_BUS_I2C5 104 +#define CLK_BUS_CAN 105 +#define CLK_SPI0 106 +#define CLK_SPI1 107 +#define CLK_SPI2 108 +#define CLK_SPIFC 109 +#define CLK_BUS_SPI0 110 +#define CLK_BUS_SPI1 111 +#define CLK_BUS_SPI2 112 +#define CLK_BUS_SPIFC 113 +#define CLK_EMAC0_25M 114 +#define CLK_EMAC1_25M 115 +#define CLK_BUS_EMAC0 116 +#define CLK_BUS_EMAC1 117 +#define CLK_IR_RX 118 +#define CLK_BUS_IR_RX 119 +#define CLK_IR_TX 120 +#define CLK_BUS_IR_TX 121 +#define CLK_GPADC0 122 +#define CLK_GPADC1 123 +#define CLK_BUS_GPADC0 124 +#define CLK_BUS_GPADC1 125 +#define CLK_BUS_THS 126 +#define CLK_USB_OHCI0 127 +#define CLK_USB_OHCI1 128 +#define CLK_BUS_OHCI0 129 +#define CLK_BUS_OHCI1 130 +#define CLK_BUS_EHCI0 131 +#define CLK_BUS_EHCI1 132 +#define CLK_BUS_OTG 133 +#define CLK_BUS_LRADC 134 +#define CLK_PCIE_AUX 135 +#define CLK_BUS_DISPLAY0_TOP 136 +#define CLK_BUS_DISPLAY1_TOP 137 +#define CLK_HDMI_24M 138 +#define CLK_HDMI_CEC_32K 139 +#define CLK_HDMI_CEC 140 +#define CLK_BUS_HDMI 141 +#define CLK_MIPI_DSI0 142 +#define CLK_MIPI_DSI1 143 +#define CLK_BUS_MIPI_DSI0 144 +#define CLK_BUS_MIPI_DSI1 145 +#define CLK_TCON_LCD0 146 +#define CLK_TCON_LCD1 147 +#define CLK_TCON_LCD2 148 +#define CLK_COMBOPHY_DSI0 149 +#define CLK_COMBOPHY_DSI1 150 +#define CLK_BUS_TCON_LCD0 151 +#define CLK_BUS_TCON_LCD1 152 +#define CLK_BUS_TCON_LCD2 153 +#define CLK_TCON_TV0 154 +#define CLK_TCON_TV1 155 +#define CLK_BUS_TCON_TV0 156 +#define CLK_BUS_TCON_TV1 157 +#define CLK_EDP 158 +#define CLK_BUS_EDP 159 +#define CLK_LEDC 160 +#define CLK_BUS_LEDC 161 +#define CLK_CSI_TOP 162 +#define CLK_CSI_MCLK0 163 +#define CLK_CSI_MCLK1 164 +#define CLK_CSI_MCLK2 165 +#define CLK_CSI_MCLK3 166 +#define CLK_BUS_CSI 167 +#define CLK_ISP 168 +#define CLK_DSP 169 +#define CLK_FANOUT_24M 170 +#define CLK_FANOUT_12M 171 +#define CLK_FANOUT_16M 172 +#define CLK_FANOUT_25M 173 +#define CLK_FANOUT_27M 174 +#define CLK_FANOUT_PCLK 175 +#define CLK_FANOUT0 176 +#define CLK_FANOUT1 177 +#define CLK_FANOUT2 178 + +#endif /* _DT_BINDINGS_CLK_SUN55I_A523_CCU_H_ */ diff --git a/include/dt-bindings/clock/sun55i-a523-r-ccu.h b/include/dt-bindings/clock/sun55i-a523-r-ccu.h new file mode 100644 index 000000000000..365647499b9a --- /dev/null +++ b/include/dt-bindings/clock/sun55i-a523-r-ccu.h @@ -0,0 +1,37 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */ +/* + * Copyright (C) 2024 Arm Ltd. + */ + +#ifndef _DT_BINDINGS_CLK_SUN55I_A523_R_CCU_H_ +#define _DT_BINDINGS_CLK_SUN55I_A523_R_CCU_H_ + +#define CLK_R_AHB 0 +#define CLK_R_APB0 1 +#define CLK_R_APB1 2 +#define CLK_R_TIMER0 3 +#define CLK_R_TIMER1 4 +#define CLK_R_TIMER2 5 +#define CLK_BUS_R_TIMER 6 +#define CLK_BUS_R_TWD 7 +#define CLK_R_PWMCTRL 8 +#define CLK_BUS_R_PWMCTRL 9 +#define CLK_R_SPI 10 +#define CLK_BUS_R_SPI 11 +#define CLK_BUS_R_SPINLOCK 12 +#define CLK_BUS_R_MSGBOX 13 +#define CLK_BUS_R_UART0 14 +#define CLK_BUS_R_UART1 15 +#define CLK_BUS_R_I2C0 16 +#define CLK_BUS_R_I2C1 17 +#define CLK_BUS_R_I2C2 18 +#define CLK_BUS_R_PPU0 19 +#define CLK_BUS_R_PPU1 20 +#define CLK_BUS_R_CPU_BIST 21 +#define CLK_R_IR_RX 22 +#define CLK_BUS_R_IR_RX 23 +#define CLK_BUS_R_DMA 24 +#define CLK_BUS_R_RTC 25 +#define CLK_BUS_R_CPUCFG 26 + +#endif /* _DT_BINDINGS_CLK_SUN55I_A523_R_CCU_H_ */ diff --git a/include/dt-bindings/clock/sun8i-v3s-ccu.h b/include/dt-bindings/clock/sun8i-v3s-ccu.h index 014ac6123d17..c4055629c9f9 100644 --- a/include/dt-bindings/clock/sun8i-v3s-ccu.h +++ b/include/dt-bindings/clock/sun8i-v3s-ccu.h @@ -96,7 +96,7 @@ #define CLK_TCON0 64 #define CLK_CSI_MISC 65 #define CLK_CSI0_MCLK 66 -#define CLK_CSI1_SCLK 67 +#define CLK_CSI_SCLK 67 #define CLK_CSI1_MCLK 68 #define CLK_VE 69 #define CLK_AC_DIG 70 diff --git a/include/dt-bindings/clock/thead,th1520-clk-ap.h b/include/dt-bindings/clock/thead,th1520-clk-ap.h index a199784b3512..09a9aa7b3ab1 100644 --- a/include/dt-bindings/clock/thead,th1520-clk-ap.h +++ b/include/dt-bindings/clock/thead,th1520-clk-ap.h @@ -93,4 +93,38 @@ #define CLK_SRAM3 83 #define CLK_PLL_GMAC_100M 84 #define CLK_UART_SCLK 85 + +/* VO clocks */ +#define CLK_AXI4_VO_ACLK 0 +#define CLK_GPU_MEM 1 +#define CLK_GPU_CORE 2 +#define CLK_GPU_CFG_ACLK 3 +#define CLK_DPU_PIXELCLK0 4 +#define CLK_DPU_PIXELCLK1 5 +#define CLK_DPU_HCLK 6 +#define CLK_DPU_ACLK 7 +#define CLK_DPU_CCLK 8 +#define CLK_HDMI_SFR 9 +#define CLK_HDMI_PCLK 10 +#define CLK_HDMI_CEC 11 +#define CLK_MIPI_DSI0_PCLK 12 +#define CLK_MIPI_DSI1_PCLK 13 +#define CLK_MIPI_DSI0_CFG 14 +#define CLK_MIPI_DSI1_CFG 15 +#define CLK_MIPI_DSI0_REFCLK 16 +#define CLK_MIPI_DSI1_REFCLK 17 +#define CLK_HDMI_I2S 18 +#define CLK_X2H_DPU1_ACLK 19 +#define CLK_X2H_DPU_ACLK 20 +#define CLK_AXI4_VO_PCLK 21 +#define CLK_IOPMP_VOSYS_DPU_PCLK 22 +#define CLK_IOPMP_VOSYS_DPU1_PCLK 23 +#define CLK_IOPMP_VOSYS_GPU_PCLK 24 +#define CLK_IOPMP_DPU1_ACLK 25 +#define CLK_IOPMP_DPU_ACLK 26 +#define CLK_IOPMP_GPU_ACLK 27 +#define CLK_MIPIDSI0_PIXCLK 28 +#define CLK_MIPIDSI1_PIXCLK 29 +#define CLK_HDMI_PIXCLK 30 + #endif diff --git a/include/dt-bindings/clock/xlnx-zynqmp-clk.h b/include/dt-bindings/clock/xlnx-zynqmp-clk.h index cdc4c0b9a374..f0f7ddd3dcbd 100644 --- a/include/dt-bindings/clock/xlnx-zynqmp-clk.h +++ b/include/dt-bindings/clock/xlnx-zynqmp-clk.h @@ -9,6 +9,13 @@ #ifndef _DT_BINDINGS_CLK_ZYNQMP_H #define _DT_BINDINGS_CLK_ZYNQMP_H +/* + * These bindings are deprecated, because they do not match the actual + * concept of bindings but rather contain pure firmware values. + * Instead include the header in the DTS source directory. + */ +#warning "These bindings are deprecated. Instead use the header in the DTS source directory." + #define IOPLL 0 #define RPLL 1 #define APLL 2 diff --git a/include/dt-bindings/iio/adi,ad4695.h b/include/dt-bindings/iio/adc/adi,ad4695.h index 9fbef542bf67..fea4525d2710 100644 --- a/include/dt-bindings/iio/adi,ad4695.h +++ b/include/dt-bindings/iio/adc/adi,ad4695.h @@ -6,4 +6,11 @@ #define AD4695_COMMON_MODE_REFGND 0xFF #define AD4695_COMMON_MODE_COM 0xFE +#define AD4695_TRIGGER_EVENT_BUSY 0 +#define AD4695_TRIGGER_EVENT_ALERT 1 + +#define AD4695_TRIGGER_PIN_GP0 0 +#define AD4695_TRIGGER_PIN_GP2 2 +#define AD4695_TRIGGER_PIN_GP3 3 + #endif /* _DT_BINDINGS_ADI_AD4695_H */ diff --git a/include/dt-bindings/iio/adc/adi,ad7606.h b/include/dt-bindings/iio/adc/adi,ad7606.h new file mode 100644 index 000000000000..f38a6d72b6dc --- /dev/null +++ b/include/dt-bindings/iio/adc/adi,ad7606.h @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ + +#ifndef _DT_BINDINGS_ADI_AD7606_H +#define _DT_BINDINGS_ADI_AD7606_H + +#define AD7606_TRIGGER_EVENT_BUSY 0 +#define AD7606_TRIGGER_EVENT_FRSTDATA 1 + +#endif /* _DT_BINDINGS_ADI_AD7606_H */ diff --git a/include/dt-bindings/iio/adc/adi,ad7768-1.h b/include/dt-bindings/iio/adc/adi,ad7768-1.h new file mode 100644 index 000000000000..34d92856a50b --- /dev/null +++ b/include/dt-bindings/iio/adc/adi,ad7768-1.h @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ + +#ifndef _DT_BINDINGS_ADI_AD7768_1_H +#define _DT_BINDINGS_ADI_AD7768_1_H + +#define AD7768_TRIGGER_SOURCE_SYNC_OUT 0 +#define AD7768_TRIGGER_SOURCE_GPIO3 1 +#define AD7768_TRIGGER_SOURCE_DRDY 2 + +#endif /* _DT_BINDINGS_ADI_AD7768_1_H */ diff --git a/include/dt-bindings/iio/adc/mediatek,mt6363-auxadc.h b/include/dt-bindings/iio/adc/mediatek,mt6363-auxadc.h new file mode 100644 index 000000000000..92d135477d0e --- /dev/null +++ b/include/dt-bindings/iio/adc/mediatek,mt6363-auxadc.h @@ -0,0 +1,24 @@ +/* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */ + +#ifndef _DT_BINDINGS_MEDIATEK_MT6363_AUXADC_H +#define _DT_BINDINGS_MEDIATEK_MT6363_AUXADC_H + +/* ADC Channel Index */ +#define MT6363_AUXADC_BATADC 0 +#define MT6363_AUXADC_VCDT 1 +#define MT6363_AUXADC_BAT_TEMP 2 +#define MT6363_AUXADC_CHIP_TEMP 3 +#define MT6363_AUXADC_VSYSSNS 4 +#define MT6363_AUXADC_VTREF 5 +#define MT6363_AUXADC_VCORE_TEMP 6 +#define MT6363_AUXADC_VPROC_TEMP 7 +#define MT6363_AUXADC_VGPU_TEMP 8 +#define MT6363_AUXADC_VIN1 9 +#define MT6363_AUXADC_VIN2 10 +#define MT6363_AUXADC_VIN3 11 +#define MT6363_AUXADC_VIN4 12 +#define MT6363_AUXADC_VIN5 13 +#define MT6363_AUXADC_VIN6 14 +#define MT6363_AUXADC_VIN7 15 + +#endif diff --git a/include/dt-bindings/iio/adc/mediatek,mt6373-auxadc.h b/include/dt-bindings/iio/adc/mediatek,mt6373-auxadc.h new file mode 100644 index 000000000000..17cab86d355e --- /dev/null +++ b/include/dt-bindings/iio/adc/mediatek,mt6373-auxadc.h @@ -0,0 +1,19 @@ +/* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */ + +#ifndef _DT_BINDINGS_MEDIATEK_MT6373_AUXADC_H +#define _DT_BINDINGS_MEDIATEK_MT6373_AUXADC_H + +/* ADC Channel Index */ +#define MT6373_AUXADC_CHIP_TEMP 0 +#define MT6373_AUXADC_VCORE_TEMP 1 +#define MT6373_AUXADC_VPROC_TEMP 2 +#define MT6373_AUXADC_VGPU_TEMP 3 +#define MT6373_AUXADC_VIN1 4 +#define MT6373_AUXADC_VIN2 5 +#define MT6373_AUXADC_VIN3 6 +#define MT6373_AUXADC_VIN4 7 +#define MT6373_AUXADC_VIN5 8 +#define MT6373_AUXADC_VIN6 9 +#define MT6373_AUXADC_VIN7 10 + +#endif diff --git a/include/dt-bindings/interconnect/qcom,milos-rpmh.h b/include/dt-bindings/interconnect/qcom,milos-rpmh.h new file mode 100644 index 000000000000..9326d7d9c2a3 --- /dev/null +++ b/include/dt-bindings/interconnect/qcom,milos-rpmh.h @@ -0,0 +1,141 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) 2023-2024, Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2025, Luca Weiss <luca.weiss@fairphone.com> + */ + +#ifndef __DT_BINDINGS_INTERCONNECT_QCOM_MILOS_H +#define __DT_BINDINGS_INTERCONNECT_QCOM_MILOS_H + +#define MASTER_QUP_1 0 +#define MASTER_UFS_MEM 1 +#define MASTER_USB3_0 2 +#define SLAVE_A1NOC_SNOC 3 + +#define MASTER_QDSS_BAM 0 +#define MASTER_QSPI_0 1 +#define MASTER_QUP_0 2 +#define MASTER_CRYPTO 3 +#define MASTER_IPA 4 +#define MASTER_QDSS_ETR 5 +#define MASTER_QDSS_ETR_1 6 +#define MASTER_SDCC_1 7 +#define MASTER_SDCC_2 8 +#define SLAVE_A2NOC_SNOC 9 + +#define MASTER_QUP_CORE_0 0 +#define MASTER_QUP_CORE_1 1 +#define SLAVE_QUP_CORE_0 2 +#define SLAVE_QUP_CORE_1 3 + +#define MASTER_CNOC_CFG 0 +#define SLAVE_AHB2PHY_SOUTH 1 +#define SLAVE_AHB2PHY_NORTH 2 +#define SLAVE_CAMERA_CFG 3 +#define SLAVE_CLK_CTL 4 +#define SLAVE_RBCPR_CX_CFG 5 +#define SLAVE_RBCPR_MXA_CFG 6 +#define SLAVE_CRYPTO_0_CFG 7 +#define SLAVE_CX_RDPM 8 +#define SLAVE_GFX3D_CFG 9 +#define SLAVE_IMEM_CFG 10 +#define SLAVE_CNOC_MSS 11 +#define SLAVE_MX_2_RDPM 12 +#define SLAVE_MX_RDPM 13 +#define SLAVE_PDM 14 +#define SLAVE_QDSS_CFG 15 +#define SLAVE_QSPI_0 16 +#define SLAVE_QUP_0 17 +#define SLAVE_QUP_1 18 +#define SLAVE_SDC1 19 +#define SLAVE_SDCC_2 20 +#define SLAVE_TCSR 21 +#define SLAVE_TLMM 22 +#define SLAVE_UFS_MEM_CFG 23 +#define SLAVE_USB3_0 24 +#define SLAVE_VENUS_CFG 25 +#define SLAVE_VSENSE_CTRL_CFG 26 +#define SLAVE_WLAN 27 +#define SLAVE_CNOC_MNOC_HF_CFG 28 +#define SLAVE_CNOC_MNOC_SF_CFG 29 +#define SLAVE_NSP_QTB_CFG 30 +#define SLAVE_PCIE_ANOC_CFG 31 +#define SLAVE_WLAN_Q6_THROTTLE_CFG 32 +#define SLAVE_SERVICE_CNOC_CFG 33 +#define SLAVE_QDSS_STM 34 +#define SLAVE_TCU 35 + +#define MASTER_GEM_NOC_CNOC 0 +#define MASTER_GEM_NOC_PCIE_SNOC 1 +#define SLAVE_AOSS 2 +#define SLAVE_DISPLAY_CFG 3 +#define SLAVE_IPA_CFG 4 +#define SLAVE_IPC_ROUTER_CFG 5 +#define SLAVE_PCIE_0_CFG 6 +#define SLAVE_PCIE_1_CFG 7 +#define SLAVE_PRNG 8 +#define SLAVE_TME_CFG 9 +#define SLAVE_APPSS 10 +#define SLAVE_CNOC_CFG 11 +#define SLAVE_DDRSS_CFG 12 +#define SLAVE_IMEM 13 +#define SLAVE_PIMEM 14 +#define SLAVE_SERVICE_CNOC 15 +#define SLAVE_PCIE_0 16 +#define SLAVE_PCIE_1 17 + +#define MASTER_GPU_TCU 0 +#define MASTER_SYS_TCU 1 +#define MASTER_APPSS_PROC 2 +#define MASTER_GFX3D 3 +#define MASTER_LPASS_GEM_NOC 4 +#define MASTER_MSS_PROC 5 +#define MASTER_MNOC_HF_MEM_NOC 6 +#define MASTER_MNOC_SF_MEM_NOC 7 +#define MASTER_COMPUTE_NOC 8 +#define MASTER_ANOC_PCIE_GEM_NOC 9 +#define MASTER_SNOC_GC_MEM_NOC 10 +#define MASTER_SNOC_SF_MEM_NOC 11 +#define MASTER_WLAN_Q6 12 +#define SLAVE_GEM_NOC_CNOC 13 +#define SLAVE_LLCC 14 +#define SLAVE_MEM_NOC_PCIE_SNOC 15 + +#define MASTER_LPASS_PROC 0 +#define SLAVE_LPASS_GEM_NOC 1 + +#define MASTER_LLCC 0 +#define SLAVE_EBI1 1 + +#define MASTER_CAMNOC_HF 0 +#define MASTER_CAMNOC_ICP 1 +#define MASTER_CAMNOC_SF 2 +#define MASTER_MDP 3 +#define MASTER_VIDEO 4 +#define MASTER_CNOC_MNOC_HF_CFG 5 +#define MASTER_CNOC_MNOC_SF_CFG 6 +#define SLAVE_MNOC_HF_MEM_NOC 7 +#define SLAVE_MNOC_SF_MEM_NOC 8 +#define SLAVE_SERVICE_MNOC_HF 9 +#define SLAVE_SERVICE_MNOC_SF 10 + +#define MASTER_CDSP_PROC 0 +#define SLAVE_CDSP_MEM_NOC 1 + +#define MASTER_PCIE_ANOC_CFG 0 +#define MASTER_PCIE_0 1 +#define MASTER_PCIE_1 2 +#define SLAVE_ANOC_PCIE_GEM_NOC 3 +#define SLAVE_SERVICE_PCIE_ANOC 4 + +#define MASTER_A1NOC_SNOC 0 +#define MASTER_A2NOC_SNOC 1 +#define MASTER_APSS_NOC 2 +#define MASTER_CNOC_SNOC 3 +#define MASTER_PIMEM 4 +#define MASTER_GIC 5 +#define SLAVE_SNOC_GEM_NOC_GC 6 +#define SLAVE_SNOC_GEM_NOC_SF 7 + + +#endif diff --git a/include/dt-bindings/interconnect/qcom,sm8650-rpmh.h b/include/dt-bindings/interconnect/qcom,sm8650-rpmh.h index 6c1eaf04e241..1216aa352d55 100644 --- a/include/dt-bindings/interconnect/qcom,sm8650-rpmh.h +++ b/include/dt-bindings/interconnect/qcom,sm8650-rpmh.h @@ -150,5 +150,6 @@ #define MASTER_A1NOC_SNOC 0 #define MASTER_A2NOC_SNOC 1 #define SLAVE_SNOC_GEM_NOC_SF 2 +#define MASTER_APSS_NOC 3 #endif diff --git a/include/dt-bindings/interconnect/qcom,sm8750-rpmh.h b/include/dt-bindings/interconnect/qcom,sm8750-rpmh.h new file mode 100644 index 000000000000..30563952a646 --- /dev/null +++ b/include/dt-bindings/interconnect/qcom,sm8750-rpmh.h @@ -0,0 +1,143 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#ifndef __DT_BINDINGS_INTERCONNECT_QCOM_SM8750_H +#define __DT_BINDINGS_INTERCONNECT_QCOM_SM8750_H + +#define MASTER_QSPI_0 0 +#define MASTER_QUP_1 1 +#define MASTER_QUP_3 2 +#define MASTER_SDCC_4 3 +#define MASTER_UFS_MEM 4 +#define MASTER_USB3_0 5 +#define SLAVE_A1NOC_SNOC 6 + +#define MASTER_QDSS_BAM 0 +#define MASTER_QUP_2 1 +#define MASTER_CRYPTO 2 +#define MASTER_IPA 3 +#define MASTER_SOCCP_AGGR_NOC 4 +#define MASTER_SP 5 +#define MASTER_QDSS_ETR 6 +#define MASTER_QDSS_ETR_1 7 +#define MASTER_SDCC_2 8 +#define SLAVE_A2NOC_SNOC 9 + +#define MASTER_QUP_CORE_0 0 +#define MASTER_QUP_CORE_1 1 +#define MASTER_QUP_CORE_2 2 +#define SLAVE_QUP_CORE_0 3 +#define SLAVE_QUP_CORE_1 4 +#define SLAVE_QUP_CORE_2 5 + +#define MASTER_CNOC_CFG 0 +#define SLAVE_AHB2PHY_SOUTH 1 +#define SLAVE_AHB2PHY_NORTH 2 +#define SLAVE_CAMERA_CFG 3 +#define SLAVE_CLK_CTL 4 +#define SLAVE_CRYPTO_0_CFG 5 +#define SLAVE_DISPLAY_CFG 6 +#define SLAVE_EVA_CFG 7 +#define SLAVE_GFX3D_CFG 8 +#define SLAVE_I2C 9 +#define SLAVE_I3C_IBI0_CFG 10 +#define SLAVE_I3C_IBI1_CFG 11 +#define SLAVE_IMEM_CFG 12 +#define SLAVE_CNOC_MSS 13 +#define SLAVE_PCIE_CFG 14 +#define SLAVE_PRNG 15 +#define SLAVE_QDSS_CFG 16 +#define SLAVE_QSPI_0 17 +#define SLAVE_QUP_3 18 +#define SLAVE_QUP_1 19 +#define SLAVE_QUP_2 20 +#define SLAVE_SDCC_2 21 +#define SLAVE_SDCC_4 22 +#define SLAVE_SPSS_CFG 23 +#define SLAVE_TCSR 24 +#define SLAVE_TLMM 25 +#define SLAVE_UFS_MEM_CFG 26 +#define SLAVE_USB3_0 27 +#define SLAVE_VENUS_CFG 28 +#define SLAVE_VSENSE_CTRL_CFG 29 +#define SLAVE_CNOC_MNOC_CFG 30 +#define SLAVE_PCIE_ANOC_CFG 31 +#define SLAVE_QDSS_STM 32 +#define SLAVE_TCU 33 + +#define MASTER_GEM_NOC_CNOC 0 +#define MASTER_GEM_NOC_PCIE_SNOC 1 +#define SLAVE_AOSS 2 +#define SLAVE_IPA_CFG 3 +#define SLAVE_IPC_ROUTER_CFG 4 +#define SLAVE_SOCCP 5 +#define SLAVE_TME_CFG 6 +#define SLAVE_APPSS 7 +#define SLAVE_CNOC_CFG 8 +#define SLAVE_DDRSS_CFG 9 +#define SLAVE_BOOT_IMEM 10 +#define SLAVE_IMEM 11 +#define SLAVE_BOOT_IMEM_2 12 +#define SLAVE_SERVICE_CNOC 13 +#define SLAVE_PCIE_0 14 + +#define MASTER_GPU_TCU 0 +#define MASTER_SYS_TCU 1 +#define MASTER_APPSS_PROC 2 +#define MASTER_GFX3D 3 +#define MASTER_LPASS_GEM_NOC 4 +#define MASTER_MSS_PROC 5 +#define MASTER_MNOC_HF_MEM_NOC 6 +#define MASTER_MNOC_SF_MEM_NOC 7 +#define MASTER_COMPUTE_NOC 8 +#define MASTER_ANOC_PCIE_GEM_NOC 9 +#define MASTER_SNOC_SF_MEM_NOC 10 +#define MASTER_UBWC_P 11 +#define MASTER_GIC 12 +#define SLAVE_UBWC_P 13 +#define SLAVE_GEM_NOC_CNOC 14 +#define SLAVE_LLCC 15 +#define SLAVE_MEM_NOC_PCIE_SNOC 16 + +#define MASTER_LPIAON_NOC 0 +#define SLAVE_LPASS_GEM_NOC 1 + +#define MASTER_LPASS_LPINOC 0 +#define SLAVE_LPIAON_NOC_LPASS_AG_NOC 1 + +#define MASTER_LPASS_PROC 0 +#define SLAVE_LPICX_NOC_LPIAON_NOC 1 + +#define MASTER_LLCC 0 +#define SLAVE_EBI1 1 + +#define MASTER_CAMNOC_HF 0 +#define MASTER_CAMNOC_NRT_ICP_SF 1 +#define MASTER_CAMNOC_RT_CDM_SF 2 +#define MASTER_CAMNOC_SF 3 +#define MASTER_MDP 4 +#define MASTER_CDSP_HCP 5 +#define MASTER_VIDEO_CV_PROC 6 +#define MASTER_VIDEO_EVA 7 +#define MASTER_VIDEO_MVP 8 +#define MASTER_VIDEO_V_PROC 9 +#define MASTER_CNOC_MNOC_CFG 10 +#define SLAVE_MNOC_HF_MEM_NOC 11 +#define SLAVE_MNOC_SF_MEM_NOC 12 +#define SLAVE_SERVICE_MNOC 13 + +#define MASTER_CDSP_PROC 0 +#define SLAVE_CDSP_MEM_NOC 1 + +#define MASTER_PCIE_ANOC_CFG 0 +#define MASTER_PCIE_0 1 +#define SLAVE_ANOC_PCIE_GEM_NOC 2 +#define SLAVE_SERVICE_PCIE_ANOC 3 + +#define MASTER_A1NOC_SNOC 0 +#define MASTER_A2NOC_SNOC 1 +#define SLAVE_SNOC_GEM_NOC_SF 2 + +#endif diff --git a/include/dt-bindings/media/video-interfaces.h b/include/dt-bindings/media/video-interfaces.h index 68ac4e05e37f..88b9d05d8075 100644 --- a/include/dt-bindings/media/video-interfaces.h +++ b/include/dt-bindings/media/video-interfaces.h @@ -13,4 +13,11 @@ #define MEDIA_BUS_TYPE_PARALLEL 5 #define MEDIA_BUS_TYPE_BT656 6 +#define MEDIA_BUS_CSI2_CPHY_LINE_ORDER_ABC 0 +#define MEDIA_BUS_CSI2_CPHY_LINE_ORDER_ACB 1 +#define MEDIA_BUS_CSI2_CPHY_LINE_ORDER_BAC 2 +#define MEDIA_BUS_CSI2_CPHY_LINE_ORDER_BCA 3 +#define MEDIA_BUS_CSI2_CPHY_LINE_ORDER_CAB 4 +#define MEDIA_BUS_CSI2_CPHY_LINE_ORDER_CBA 5 + #endif /* __DT_BINDINGS_MEDIA_VIDEO_INTERFACES_H__ */ diff --git a/include/dt-bindings/memory/mediatek,mt6893-memory-port.h b/include/dt-bindings/memory/mediatek,mt6893-memory-port.h new file mode 100644 index 000000000000..26e8b400db0d --- /dev/null +++ b/include/dt-bindings/memory/mediatek,mt6893-memory-port.h @@ -0,0 +1,288 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) 2020 MediaTek Inc. + * Copyright (c) 2025 Collabora Ltd + * AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> + */ +#ifndef _DT_BINDINGS_MEMORY_MT6893_LARB_PORT_H_ +#define _DT_BINDINGS_MEMORY_MT6893_LARB_PORT_H_ + +#include <dt-bindings/memory/mtk-memory-port.h> + +/* + * MM IOMMU supports 16GB dma address. + * + * The address will preassign like this: + * + * modules dma-address-region larbs-ports + * disp 0 ~ 4G larb0/2 + * vcodec 4G ~ 8G larb4/5/7 + * cam/mdp 8G ~ 12G larb9/11/13/14/16/17/18/19/20 + * CCU0 0x4000_0000 ~ 0x43ff_ffff larb13: port 9/10 + * CCU1 0x4400_0000 ~ 0x47ff_ffff larb14: port 4/5 + * + * larb3/6/8/10/12/15 are null. + */ + +/* larb0 */ +#define M4U_PORT_L0_DISP_POSTMASK0 MTK_M4U_DOM_ID(0, 0) +#define M4U_PORT_L0_MDP_RDMA4 MTK_M4U_DOM_ID(0, 1) +#define M4U_PORT_L0_OVL_RDMA0_HDR MTK_M4U_DOM_ID(0, 2) +#define M4U_PORT_L0_OVL_2L_RDMA1_HDR MTK_M4U_DOM_ID(0, 3) +#define M4U_PORT_L0_OVL_2L_RDMA3_HDR MTK_M4U_DOM_ID(0, 4) +#define M4U_PORT_L0_OVL_RDMA0 MTK_M4U_DOM_ID(0, 5) +#define M4U_PORT_L0_OVL_2L_RDMA1 MTK_M4U_DOM_ID(0, 6) +#define M4U_PORT_L0_OVL_2L_RDMA3 MTK_M4U_DOM_ID(0, 7) +#define M4U_PORT_L0_OVL_RDMA1_SYSRAM MTK_M4U_DOM_ID(0, 8) +#define M4U_PORT_L0_OVL_2L_RDMA0_SYSRAM MTK_M4U_DOM_ID(0, 9) +#define M4U_PORT_L0_OVL_2L_RDMA2_SYSRAM MTK_M4U_DOM_ID(0, 10) +#define M4U_PORT_L0_DISP_WDMA0 MTK_M4U_DOM_ID(0, 11) +#define M4U_PORT_L0_DISP_RDMA0 MTK_M4U_DOM_ID(0, 12) +#define M4U_PORT_L0_DISP_UFBC_WDMA0 MTK_M4U_DOM_ID(0, 13) +#define M4U_PORT_L0_DISP_FAKE0 MTK_M4U_DOM_ID(0, 14) + +/* larb1 */ +#define M4U_PORT_L1_DISP_POSTMASK1 MTK_M4U_DOM_ID(1, 0) +#define M4U_PORT_L1_MDP_RDMA5 MTK_M4U_DOM_ID(1, 1) +#define M4U_PORT_L1_OVL_RDMA1_HDR MTK_M4U_DOM_ID(1, 2) +#define M4U_PORT_L1_OVL_2L_RDMA0_HDR MTK_M4U_DOM_ID(1, 3) +#define M4U_PORT_L1_OVL_2L_RDMA2_HDR MTK_M4U_DOM_ID(1, 4) +#define M4U_PORT_L1_OVL_RDMA1 MTK_M4U_DOM_ID(1, 5) +#define M4U_PORT_L1_OVL_2L_RDMA0 MTK_M4U_DOM_ID(1, 6) +#define M4U_PORT_L1_OVL_2L_RDMA2 MTK_M4U_DOM_ID(1, 7) +#define M4U_PORT_L1_OVL_RDMA0_SYSRAM MTK_M4U_DOM_ID(1, 8) +#define M4U_PORT_L1_OVL_2L_RDMA1_SYSRAM MTK_M4U_DOM_ID(1, 9) +#define M4U_PORT_L1_OVL_2L_RDMA3_SYSRAM MTK_M4U_DOM_ID(1, 10) +#define M4U_PORT_L1_DISP_WDMA1 MTK_M4U_DOM_ID(1, 11) +#define M4U_PORT_L1_DISP_RDMA1 MTK_M4U_DOM_ID(1, 12) +#define M4U_PORT_L1_DISP_UFBC_WDMA1 MTK_M4U_DOM_ID(1, 13) +#define M4U_PORT_L1_DISP_FAKE1 MTK_M4U_DOM_ID(1, 14) + +/* larb2 */ +#define M4U_PORT_L2_MDP_RDMA0 MTK_M4U_DOM_ID(2, 0) +#define M4U_PORT_L2_MDP_RDMA2 MTK_M4U_DOM_ID(2, 1) +#define M4U_PORT_L2_MDP_WROT0 MTK_M4U_DOM_ID(2, 2) +#define M4U_PORT_L2_MDP_WROT2 MTK_M4U_DOM_ID(2, 3) +#define M4U_PORT_L2_MDP_FILMGRAIN0 MTK_M4U_DOM_ID(2, 4) +#define M4U_PORT_L2_MDP_FAKE0 MTK_M4U_DOM_ID(2, 5) + +/* larb3: null */ + +/* larb4 */ +#define M4U_PORT_L4_VDEC_MC_EXT_MDP MTK_M4U_DOM_ID(4, 0) +#define M4U_PORT_L4_VDEC_UFO_EXT_MDP MTK_M4U_DOM_ID(4, 1) +#define M4U_PORT_L4_VDEC_PP_EXT_MDP MTK_M4U_DOM_ID(4, 2) +#define M4U_PORT_L4_VDEC_PRED_RD_EXT_MDP MTK_M4U_DOM_ID(4, 3) +#define M4U_PORT_L4_VDEC_PRED_WR_EXT_MDP MTK_M4U_DOM_ID(4, 4) +#define M4U_PORT_L4_VDEC_PPWRAP_EXT_MDP MTK_M4U_DOM_ID(4, 5) +#define M4U_PORT_L4_VDEC_TILE_EXT_MDP MTK_M4U_DOM_ID(4, 6) +#define M4U_PORT_L4_VDEC_VLD_EXT_MDP MTK_M4U_DOM_ID(4, 7) +#define M4U_PORT_L4_VDEC_VLD2_EXT_MDP MTK_M4U_DOM_ID(4, 8) +#define M4U_PORT_L4_VDEC_AVC_MV_EXT_MDP MTK_M4U_DOM_ID(4, 9) +#define M4U_PORT_L4_VDEC_RG_CTRL_DMA_EXT_MDP MTK_M4U_DOM_ID(4, 10) + +/* larb5 */ +#define M4U_PORT_L5_VDEC_LAT0_VLD_EXT_DISP MTK_M4U_DOM_ID(5, 0) +#define M4U_PORT_L5_VDEC_LAT0_VLD2_EXT_DISP MTK_M4U_DOM_ID(5, 1) +#define M4U_PORT_L5_VDEC_LAT0_AVC_MV_EXT_DISP MTK_M4U_DOM_ID(5, 2) +#define M4U_PORT_L5_VDEC_LAT0_PRED_RD_EXT_DISP MTK_M4U_DOM_ID(5, 3) +#define M4U_PORT_L5_VDEC_LAT0_TILE_EXT_DISP MTK_M4U_DOM_ID(5, 4) +#define M4U_PORT_L5_VDEC_LAT0_WDMA_EXT_DISP MTK_M4U_DOM_ID(5, 5) +#define M4U_PORT_L5_VDEC_LAT0_RG_CTRL_DMA_EXT_DISP MTK_M4U_DOM_ID(5, 6) +#define M4U_PORT_L5_VDEC_UFO_ENC_EXT_DISP MTK_M4U_DOM_ID(5, 7) + +/* larb6: null */ + +/* larb7 */ +#define M4U_PORT_L7_VENC_RCPU_DISP MTK_M4U_DOM_ID(7, 0) +#define M4U_PORT_L7_VENC_REC_DISP MTK_M4U_DOM_ID(7, 1) +#define M4U_PORT_L7_VENC_BSDMA_DISP MTK_M4U_DOM_ID(7, 2) +#define M4U_PORT_L7_VENC_SV_COMV_DISP MTK_M4U_DOM_ID(7, 3) +#define M4U_PORT_L7_VENC_RD_COMV_DISP MTK_M4U_DOM_ID(7, 4) +#define M4U_PORT_L7_VENC_NBM_RDMA_DISP MTK_M4U_DOM_ID(7, 5) +#define M4U_PORT_L7_VENC_NBM_RDMA_LITE_DISP MTK_M4U_DOM_ID(7, 6) +#define M4U_PORT_L7_JPGENC_Y_RDMA_DISP MTK_M4U_DOM_ID(7, 7) +#define M4U_PORT_L7_JPGENC_C_RDMA_DISP MTK_M4U_DOM_ID(7, 8) +#define M4U_PORT_L7_JPGENC_Q_TABLE_DISP MTK_M4U_DOM_ID(7, 9) +#define M4U_PORT_L7_JPGENC_BSDMA_DISP MTK_M4U_DOM_ID(7, 10) +#define M4U_PORT_L7_JPGENC_WDMA0_DISP MTK_M4U_DOM_ID(7, 11) +#define M4U_PORT_L7_JPGENC_BSDMA0_DISP MTK_M4U_DOM_ID(7, 12) +#define M4U_PORT_L7_VENC_NBM_WDMA_DISP MTK_M4U_DOM_ID(7, 13) +#define M4U_PORT_L7_VENC_NBM_WDMA_LITE_DISP MTK_M4U_DOM_ID(7, 14) +#define M4U_PORT_L7_VENC_CUR_LUMA_DISP MTK_M4U_DOM_ID(7, 15) +#define M4U_PORT_L7_VENC_CUR_CHROMA_DISP MTK_M4U_DOM_ID(7, 16) +#define M4U_PORT_L7_VENC_REF_LUMA_DISP MTK_M4U_DOM_ID(7, 17) +#define M4U_PORT_L7_VENC_REF_CHROMA_DISP MTK_M4U_DOM_ID(7, 18) +#define M4U_PORT_L7_VENC_SUB_R_LUMA_DISP MTK_M4U_DOM_ID(7, 19) +#define M4U_PORT_L7_VENC_SUB_W_LUMA_DISP MTK_M4U_DOM_ID(7, 20) +#define M4U_PORT_L7_VENC_FCS_NBM_RDMA_DISP MTK_M4U_DOM_ID(7, 21) +#define M4U_PORT_L7_VENC_FCS_NBM_WDMA_DISP MTK_M4U_DOM_ID(7, 22) +#define M4U_PORT_L7_JPGENC_WDMA1_DISP MTK_M4U_DOM_ID(7, 23) +#define M4U_PORT_L7_JPGENC_BSDMA1_DISP MTK_M4U_DOM_ID(7, 24) +#define M4U_PORT_L7_JPGENC_HUFF_OFFSET1_DISP MTK_M4U_DOM_ID(7, 25) +#define M4U_PORT_L7_JPGENC_HUFF_OFFSET0_DISP MTK_M4U_DOM_ID(7, 26) + +/* larb8: null */ + +/* larb9 */ +#define M4U_PORT_L9_IMG_IMGI_D1_MDP MTK_M4U_DOM_ID(9, 0) +#define M4U_PORT_L9_IMG_IMGBI_D1_MDP MTK_M4U_DOM_ID(9, 1) +#define M4U_PORT_L9_IMG_DMGI_D1_MDP MTK_M4U_DOM_ID(9, 2) +#define M4U_PORT_L9_IMG_DEPI_D1_MDP MTK_M4U_DOM_ID(9, 3) +#define M4U_PORT_L9_IMG_ICE_D1_MDP MTK_M4U_DOM_ID(9, 4) +#define M4U_PORT_L9_IMG_SMTI_D1_MDP MTK_M4U_DOM_ID(9, 5) +#define M4U_PORT_L9_IMG_SMTO_D2_MDP MTK_M4U_DOM_ID(9, 6) +#define M4U_PORT_L9_IMG_SMTO_D1_MDP MTK_M4U_DOM_ID(9, 7) +#define M4U_PORT_L9_IMG_CRZO_D1_MDP MTK_M4U_DOM_ID(9, 8) +#define M4U_PORT_L9_IMG_IMG3O_D1_MDP MTK_M4U_DOM_ID(9, 9) +#define M4U_PORT_L9_IMG_VIPI_D1_MDP MTK_M4U_DOM_ID(9, 10) +#define M4U_PORT_L9_IMG_SMTI_D5_MDP MTK_M4U_DOM_ID(9, 11) +#define M4U_PORT_L9_IMG_TIMGO_D1_MDP MTK_M4U_DOM_ID(9, 12) +#define M4U_PORT_L9_IMG_UFBC_W0_MDP MTK_M4U_DOM_ID(9, 13) +#define M4U_PORT_L9_IMG_UFBC_R0_MDP MTK_M4U_DOM_ID(9, 14) +#define M4U_PORT_L9_IMG_WPE_RDMA1_MDP MTK_M4U_DOM_ID(9, 15) +#define M4U_PORT_L9_IMG_WPE_RDMA0_MDP MTK_M4U_DOM_ID(9, 16) +#define M4U_PORT_L9_IMG_WPE_WDMA_MDP MTK_M4U_DOM_ID(9, 17) +#define M4U_PORT_L9_IMG_MFB_RDMA0_MDP MTK_M4U_DOM_ID(9, 18) +#define M4U_PORT_L9_IMG_MFB_RDMA1_MDP MTK_M4U_DOM_ID(9, 19) +#define M4U_PORT_L9_IMG_MFB_RDMA2_MDP MTK_M4U_DOM_ID(9, 20) +#define M4U_PORT_L9_IMG_MFB_RDMA3_MDP MTK_M4U_DOM_ID(9, 21) +#define M4U_PORT_L9_IMG_MFB_RDMA4_MDP MTK_M4U_DOM_ID(9, 22) +#define M4U_PORT_L9_IMG_MFB_RDMA5_MDP MTK_M4U_DOM_ID(9, 23) +#define M4U_PORT_L9_IMG_MFB_WDMA0_MDP MTK_M4U_DOM_ID(9, 24) +#define M4U_PORT_L9_IMG_MFB_WDMA1_MDP MTK_M4U_DOM_ID(9, 25) +#define M4U_PORT_L9_IMG_RESERVE6_MDP MTK_M4U_DOM_ID(9, 26) +#define M4U_PORT_L9_IMG_RESERVE7_MDP MTK_M4U_DOM_ID(9, 27) +#define M4U_PORT_L9_IMG_RESERVE8_MDP MTK_M4U_DOM_ID(9, 28) + +/* larb10: null */ + +/* larb11 */ +#define M4U_PORT_L11_IMG_IMGI_D1_DISP MTK_M4U_DOM_ID(11, 0) +#define M4U_PORT_L11_IMG_IMGBI_D1_DISP MTK_M4U_DOM_ID(11, 1) +#define M4U_PORT_L11_IMG_DMGI_D1_DISP MTK_M4U_DOM_ID(11, 2) +#define M4U_PORT_L11_IMG_DEPI_D1_DISP MTK_M4U_DOM_ID(11, 3) +#define M4U_PORT_L11_IMG_ICE_D1_DISP MTK_M4U_DOM_ID(11, 4) +#define M4U_PORT_L11_IMG_SMTI_D1_DISP MTK_M4U_DOM_ID(11, 5) +#define M4U_PORT_L11_IMG_SMTO_D2_DISP MTK_M4U_DOM_ID(11, 6) +#define M4U_PORT_L11_IMG_SMTO_D1_DISP MTK_M4U_DOM_ID(11, 7) +#define M4U_PORT_L11_IMG_CRZO_D1_DISP MTK_M4U_DOM_ID(11, 8) +#define M4U_PORT_L11_IMG_IMG3O_D1_DISP MTK_M4U_DOM_ID(11, 9) +#define M4U_PORT_L11_IMG_VIPI_D1_DISP MTK_M4U_DOM_ID(11, 10) +#define M4U_PORT_L11_IMG_SMTI_D5_DISP MTK_M4U_DOM_ID(11, 11) +#define M4U_PORT_L11_IMG_TIMGO_D1_DISP MTK_M4U_DOM_ID(11, 12) +#define M4U_PORT_L11_IMG_UFBC_W0_DISP MTK_M4U_DOM_ID(11, 13) +#define M4U_PORT_L11_IMG_UFBC_R0_DISP MTK_M4U_DOM_ID(11, 14) +#define M4U_PORT_L11_IMG_WPE_RDMA1_DISP MTK_M4U_DOM_ID(11, 15) +#define M4U_PORT_L11_IMG_WPE_RDMA0_DISP MTK_M4U_DOM_ID(11, 16) +#define M4U_PORT_L11_IMG_WPE_WDMA_DISP MTK_M4U_DOM_ID(11, 17) +#define M4U_PORT_L11_IMG_MFB_RDMA0_DISP MTK_M4U_DOM_ID(11, 18) +#define M4U_PORT_L11_IMG_MFB_RDMA1_DISP MTK_M4U_DOM_ID(11, 19) +#define M4U_PORT_L11_IMG_MFB_RDMA2_DISP MTK_M4U_DOM_ID(11, 20) +#define M4U_PORT_L11_IMG_MFB_RDMA3_DISP MTK_M4U_DOM_ID(11, 21) +#define M4U_PORT_L11_IMG_MFB_RDMA4_DISP MTK_M4U_DOM_ID(11, 22) +#define M4U_PORT_L11_IMG_MFB_RDMA5_DISP MTK_M4U_DOM_ID(11, 23) +#define M4U_PORT_L11_IMG_MFB_WDMA0_DISP MTK_M4U_DOM_ID(11, 24) +#define M4U_PORT_L11_IMG_MFB_WDMA1_DISP MTK_M4U_DOM_ID(11, 25) +#define M4U_PORT_L11_IMG_RESERVE6_DISP MTK_M4U_DOM_ID(11, 26) +#define M4U_PORT_L11_IMG_RESERVE7_DISP MTK_M4U_DOM_ID(11, 27) +#define M4U_PORT_L11_IMG_RESERVE8_DISP MTK_M4U_DOM_ID(11, 28) + +/* larb12: null */ + +/* larb13 */ +#define M4U_PORT_L13_CAM_MRAWI_MDP MTK_M4U_DOM_ID(13, 0) +#define M4U_PORT_L13_CAM_MRAWO0_MDP MTK_M4U_DOM_ID(13, 1) +#define M4U_PORT_L13_CAM_MRAWO1_MDP MTK_M4U_DOM_ID(13, 2) +#define M4U_PORT_L13_CAM_CAMSV1_MDP MTK_M4U_DOM_ID(13, 3) +#define M4U_PORT_L13_CAM_CAMSV2_MDP MTK_M4U_DOM_ID(13, 4) +#define M4U_PORT_L13_CAM_CAMSV3_MDP MTK_M4U_DOM_ID(13, 5) +#define M4U_PORT_L13_CAM_CAMSV4_MDP MTK_M4U_DOM_ID(13, 6) +#define M4U_PORT_L13_CAM_CAMSV5_MDP MTK_M4U_DOM_ID(13, 7) +#define M4U_PORT_L13_CAM_CAMSV6_MDP MTK_M4U_DOM_ID(13, 8) +#define M4U_PORT_L13_CAM_CCUI_MDP MTK_M4U_DOM_ID(13, 9) +#define M4U_PORT_L13_CAM_CCUO_MDP MTK_M4U_DOM_ID(13, 10) +#define M4U_PORT_L13_CAM_FAKE_MDP MTK_M4U_DOM_ID(13, 11) + +/* larb14 */ +#define M4U_PORT_L14_CAM_MRAWI_DISP MTK_M4U_DOM_ID(14, 0) +#define M4U_PORT_L14_CAM_MRAWO0_DISP MTK_M4U_DOM_ID(14, 1) +#define M4U_PORT_L14_CAM_MRAWO1_DISP MTK_M4U_DOM_ID(14, 2) +#define M4U_PORT_L14_CAM_CAMSV0_DISP MTK_M4U_DOM_ID(14, 3) +#define M4U_PORT_L14_CAM_CCUI_DISP MTK_M4U_DOM_ID(14, 4) +#define M4U_PORT_L14_CAM_CCUO_DISP MTK_M4U_DOM_ID(14, 5) + +/* larb15: null */ + +/* larb16 */ +#define M4U_PORT_L16_CAM_IMGO_R1_A_MDP MTK_M4U_DOM_ID(16, 0) +#define M4U_PORT_L16_CAM_RRZO_R1_A_MDP MTK_M4U_DOM_ID(16, 1) +#define M4U_PORT_L16_CAM_CQI_R1_A_MDP MTK_M4U_DOM_ID(16, 2) +#define M4U_PORT_L16_CAM_BPCI_R1_A_MDP MTK_M4U_DOM_ID(16, 3) +#define M4U_PORT_L16_CAM_YUVO_R1_A_MDP MTK_M4U_DOM_ID(16, 4) +#define M4U_PORT_L16_CAM_UFDI_R2_A_MDP MTK_M4U_DOM_ID(16, 5) +#define M4U_PORT_L16_CAM_RAWI_R2_A_MDP MTK_M4U_DOM_ID(16, 6) +#define M4U_PORT_L16_CAM_RAWI_R3_A_MDP MTK_M4U_DOM_ID(16, 7) +#define M4U_PORT_L16_CAM_AAO_R1_A_MDP MTK_M4U_DOM_ID(16, 8) +#define M4U_PORT_L16_CAM_AFO_R1_A_MDP MTK_M4U_DOM_ID(16, 9) +#define M4U_PORT_L16_CAM_FLKO_R1_A_MDP MTK_M4U_DOM_ID(16, 10) +#define M4U_PORT_L16_CAM_LCESO_R1_A_MDP MTK_M4U_DOM_ID(16, 11) +#define M4U_PORT_L16_CAM_CRZO_R1_A_MDP MTK_M4U_DOM_ID(16, 12) +#define M4U_PORT_L16_CAM_LTMSO_R1_A_MDP MTK_M4U_DOM_ID(16, 13) +#define M4U_PORT_L16_CAM_RSSO_R1_A_MDP MTK_M4U_DOM_ID(16, 14) +#define M4U_PORT_L16_CAM_AAHO_R1_A_MDP MTK_M4U_DOM_ID(16, 15) +#define M4U_PORT_L16_CAM_LSCI_R1_A_MDP MTK_M4U_DOM_ID(16, 16) + +/* larb17 */ +#define M4U_PORT_L17_CAM_IMGO_R1_B_DISP MTK_M4U_DOM_ID(17, 0) +#define M4U_PORT_L17_CAM_RRZO_R1_B_DISP MTK_M4U_DOM_ID(17, 1) +#define M4U_PORT_L17_CAM_CQI_R1_B_DISP MTK_M4U_DOM_ID(17, 2) +#define M4U_PORT_L17_CAM_BPCI_R1_B_DISP MTK_M4U_DOM_ID(17, 3) +#define M4U_PORT_L17_CAM_YUVO_R1_B_DISP MTK_M4U_DOM_ID(17, 4) +#define M4U_PORT_L17_CAM_UFDI_R2_B_DISP MTK_M4U_DOM_ID(17, 5) +#define M4U_PORT_L17_CAM_RAWI_R2_B_DISP MTK_M4U_DOM_ID(17, 6) +#define M4U_PORT_L17_CAM_RAWI_R3_B_DISP MTK_M4U_DOM_ID(17, 7) +#define M4U_PORT_L17_CAM_AAO_R1_B_DISP MTK_M4U_DOM_ID(17, 8) +#define M4U_PORT_L17_CAM_AFO_R1_B_DISP MTK_M4U_DOM_ID(17, 9) +#define M4U_PORT_L17_CAM_FLKO_R1_B_DISP MTK_M4U_DOM_ID(17, 10) +#define M4U_PORT_L17_CAM_LCESO_R1_B_DISP MTK_M4U_DOM_ID(17, 11) +#define M4U_PORT_L17_CAM_CRZO_R1_B_DISP MTK_M4U_DOM_ID(17, 12) +#define M4U_PORT_L17_CAM_LTMSO_R1_B_DISP MTK_M4U_DOM_ID(17, 13) +#define M4U_PORT_L17_CAM_RSSO_R1_B_DISP MTK_M4U_DOM_ID(17, 14) +#define M4U_PORT_L17_CAM_AAHO_R1_B_DISP MTK_M4U_DOM_ID(17, 15) +#define M4U_PORT_L17_CAM_LSCI_R1_B_DISP MTK_M4U_DOM_ID(17, 16) + +/* larb18 */ +#define M4U_PORT_L18_CAM_IMGO_R1_C_MDP MTK_M4U_DOM_ID(18, 0) +#define M4U_PORT_L18_CAM_RRZO_R1_C_MDP MTK_M4U_DOM_ID(18, 1) +#define M4U_PORT_L18_CAM_CQI_R1_C_MDP MTK_M4U_DOM_ID(18, 2) +#define M4U_PORT_L18_CAM_BPCI_R1_C_MDP MTK_M4U_DOM_ID(18, 3) +#define M4U_PORT_L18_CAM_YUVO_R1_C_MDP MTK_M4U_DOM_ID(18, 4) +#define M4U_PORT_L18_CAM_UFDI_R2_C_MDP MTK_M4U_DOM_ID(18, 5) +#define M4U_PORT_L18_CAM_RAWI_R2_C_MDP MTK_M4U_DOM_ID(18, 6) +#define M4U_PORT_L18_CAM_RAWI_R3_C_MDP MTK_M4U_DOM_ID(18, 7) +#define M4U_PORT_L18_CAM_AAO_R1_C_MDP MTK_M4U_DOM_ID(18, 8) +#define M4U_PORT_L18_CAM_AFO_R1_C_MDP MTK_M4U_DOM_ID(18, 9) +#define M4U_PORT_L18_CAM_FLKO_R1_C_MDP MTK_M4U_DOM_ID(18, 10) +#define M4U_PORT_L18_CAM_LCESO_R1_C_MDP MTK_M4U_DOM_ID(18, 11) +#define M4U_PORT_L18_CAM_CRZO_R1_C_MDP MTK_M4U_DOM_ID(18, 12) +#define M4U_PORT_L18_CAM_LTMSO_R1_C_MDP MTK_M4U_DOM_ID(18, 13) +#define M4U_PORT_L18_CAM_RSSO_R1_C_MDP MTK_M4U_DOM_ID(18, 14) +#define M4U_PORT_L18_CAM_AAHO_R1_C_MDP MTK_M4U_DOM_ID(18, 15) +#define M4U_PORT_L18_CAM_LSCI_R1_C_MDP MTK_M4U_DOM_ID(18, 16) + +/* larb19 */ +#define M4U_PORT_L19_IPE_DVS_RDMA_DISP MTK_M4U_DOM_ID(19, 0) +#define M4U_PORT_L19_IPE_DVS_WDMA_DISP MTK_M4U_DOM_ID(19, 1) +#define M4U_PORT_L19_IPE_DVP_RDMA_DISP MTK_M4U_DOM_ID(19, 2) +#define M4U_PORT_L19_IPE_DVP_WDMA_DISP MTK_M4U_DOM_ID(19, 3) + +/* larb20 */ +#define M4U_PORT_L20_IPE_FDVT_RDA_DISP MTK_M4U_DOM_ID(20, 0) +#define M4U_PORT_L20_IPE_FDVT_RDB_DISP MTK_M4U_DOM_ID(20, 1) +#define M4U_PORT_L20_IPE_FDVT_WRA_DISP MTK_M4U_DOM_ID(20, 2) +#define M4U_PORT_L20_IPE_FDVT_WRB_DISP MTK_M4U_DOM_ID(20, 3) +#define M4U_PORT_L20_IPE_RSC_RDMA0_DISP MTK_M4U_DOM_ID(20, 4) +#define M4U_PORT_L20_IPE_RSC_WDMA_DISP MTK_M4U_DOM_ID(20, 5) + +#endif diff --git a/include/dt-bindings/memory/nvidia,tegra264.h b/include/dt-bindings/memory/nvidia,tegra264.h new file mode 100644 index 000000000000..521405c01f84 --- /dev/null +++ b/include/dt-bindings/memory/nvidia,tegra264.h @@ -0,0 +1,136 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* Copyright (c) 2025, NVIDIA CORPORATION. All rights reserved. */ + +#ifndef DT_BINDINGS_MEMORY_NVIDIA_TEGRA264_H +#define DT_BINDINGS_MEMORY_NVIDIA_TEGRA264_H + +#define TEGRA264_SID(x) ((x) << 8) + +/* + * SMMU stream IDs + */ + +#define TEGRA264_SID_AON TEGRA264_SID(0x01) +#define TEGRA264_SID_APE TEGRA264_SID(0x02) +#define TEGRA264_SID_ETR TEGRA264_SID(0x03) +#define TEGRA264_SID_BPMP TEGRA264_SID(0x04) +#define TEGRA264_SID_DCE TEGRA264_SID(0x05) +#define TEGRA264_SID_EQOS TEGRA264_SID(0x06) +#define TEGRA264_SID_GPCDMA TEGRA264_SID(0x08) +#define TEGRA264_SID_DISP TEGRA264_SID(0x09) +#define TEGRA264_SID_HDA TEGRA264_SID(0x0a) +#define TEGRA264_SID_HOST1X TEGRA264_SID(0x0b) +#define TEGRA264_SID_ISP0 TEGRA264_SID(0x0c) +#define TEGRA264_SID_ISP1 TEGRA264_SID(0x0d) +#define TEGRA264_SID_PMA0 TEGRA264_SID(0x0e) +#define TEGRA264_SID_FSI0 TEGRA264_SID(0x0f) +#define TEGRA264_SID_FSI1 TEGRA264_SID(0x10) +#define TEGRA264_SID_PVA TEGRA264_SID(0x11) +#define TEGRA264_SID_SDMMC0 TEGRA264_SID(0x12) +#define TEGRA264_SID_MGBE0 TEGRA264_SID(0x13) +#define TEGRA264_SID_MGBE1 TEGRA264_SID(0x14) +#define TEGRA264_SID_MGBE2 TEGRA264_SID(0x15) +#define TEGRA264_SID_MGBE3 TEGRA264_SID(0x16) +#define TEGRA264_SID_MSSSEQ TEGRA264_SID(0x17) +#define TEGRA264_SID_SE TEGRA264_SID(0x18) +#define TEGRA264_SID_SEU1 TEGRA264_SID(0x19) +#define TEGRA264_SID_SEU2 TEGRA264_SID(0x1a) +#define TEGRA264_SID_SEU3 TEGRA264_SID(0x1b) +#define TEGRA264_SID_PSC TEGRA264_SID(0x1c) +#define TEGRA264_SID_OESP TEGRA264_SID(0x23) +#define TEGRA264_SID_SB TEGRA264_SID(0x24) +#define TEGRA264_SID_XSPI0 TEGRA264_SID(0x25) +#define TEGRA264_SID_TSEC TEGRA264_SID(0x29) +#define TEGRA264_SID_UFS TEGRA264_SID(0x2a) +#define TEGRA264_SID_RCE TEGRA264_SID(0x2b) +#define TEGRA264_SID_RCE1 TEGRA264_SID(0x2c) +#define TEGRA264_SID_VI TEGRA264_SID(0x2e) +#define TEGRA264_SID_VI1 TEGRA264_SID(0x2f) +#define TEGRA264_SID_VIC TEGRA264_SID(0x30) +#define TEGRA264_SID_XUSB_DEV TEGRA264_SID(0x32) +#define TEGRA264_SID_XUSB_DEV1 TEGRA264_SID(0x33) +#define TEGRA264_SID_XUSB_DEV2 TEGRA264_SID(0x34) +#define TEGRA264_SID_XUSB_DEV3 TEGRA264_SID(0x35) +#define TEGRA264_SID_XUSB_DEV4 TEGRA264_SID(0x36) +#define TEGRA264_SID_XUSB_DEV5 TEGRA264_SID(0x37) + +/* + * memory client IDs + */ + +/* HOST1X read client */ +#define TEGRA264_MEMORY_CLIENT_HOST1XR 0x16 +/* VIC read client */ +#define TEGRA264_MEMORY_CLIENT_VICR 0x6c +/* VIC Write client */ +#define TEGRA264_MEMORY_CLIENT_VICW 0x6d +/* VI R5 Write client */ +#define TEGRA264_MEMORY_CLIENT_VIW 0x72 +#define TEGRA264_MEMORY_CLIENT_NVDECSRD2MC 0x78 +#define TEGRA264_MEMORY_CLIENT_NVDECSWR2MC 0x79 +/* Audio processor(APE) Read client */ +#define TEGRA264_MEMORY_CLIENT_APER 0x7a +/* Audio processor(APE) Write client */ +#define TEGRA264_MEMORY_CLIENT_APEW 0x7b +/* Audio DMA Read client */ +#define TEGRA264_MEMORY_CLIENT_APEDMAR 0x9f +/* Audio DMA Write client */ +#define TEGRA264_MEMORY_CLIENT_APEDMAW 0xa0 +#define TEGRA264_MEMORY_CLIENT_GPUR02MC 0xb6 +#define TEGRA264_MEMORY_CLIENT_GPUW02MC 0xb7 +/* VI Falcon Read client */ +#define TEGRA264_MEMORY_CLIENT_VIFALCONR 0xbc +/* VI Falcon Write client */ +#define TEGRA264_MEMORY_CLIENT_VIFALCONW 0xbd +/* Read Client of RCE */ +#define TEGRA264_MEMORY_CLIENT_RCER 0xd2 +/* Write client of RCE */ +#define TEGRA264_MEMORY_CLIENT_RCEW 0xd3 +/* PCIE0/MSI Write clients */ +#define TEGRA264_MEMORY_CLIENT_PCIE0W 0xd9 +/* PCIE1/RPX4 Read clients */ +#define TEGRA264_MEMORY_CLIENT_PCIE1R 0xda +/* PCIE1/RPX4 Write clients */ +#define TEGRA264_MEMORY_CLIENT_PCIE1W 0xdb +/* PCIE2/DMX4 Read clients */ +#define TEGRA264_MEMORY_CLIENT_PCIE2AR 0xdc +/* PCIE2/DMX4 Write clients */ +#define TEGRA264_MEMORY_CLIENT_PCIE2AW 0xdd +/* PCIE3/RPX4 Read clients */ +#define TEGRA264_MEMORY_CLIENT_PCIE3R 0xde +/* PCIE3/RPX4 Write clients */ +#define TEGRA264_MEMORY_CLIENT_PCIE3W 0xdf +/* PCIE4/DMX8 Read clients */ +#define TEGRA264_MEMORY_CLIENT_PCIE4R 0xe0 +/* PCIE4/DMX8 Write clients */ +#define TEGRA264_MEMORY_CLIENT_PCIE4W 0xe1 +/* PCIE5/DMX4 Read clients */ +#define TEGRA264_MEMORY_CLIENT_PCIE5R 0xe2 +/* PCIE5/DMX4 Write clients */ +#define TEGRA264_MEMORY_CLIENT_PCIE5W 0xe3 +/* UFS Read client */ +#define TEGRA264_MEMORY_CLIENT_UFSR 0x15c +/* UFS write client */ +#define TEGRA264_MEMORY_CLIENT_UFSW 0x15d +/* HDA Read client */ +#define TEGRA264_MEMORY_CLIENT_HDAR 0x17c +/* HDA Write client */ +#define TEGRA264_MEMORY_CLIENT_HDAW 0x17d +/* Disp ISO Read Client */ +#define TEGRA264_MEMORY_CLIENT_DISPR 0x182 +/* MGBE0 Read mccif */ +#define TEGRA264_MEMORY_CLIENT_MGBE0R 0x1a2 +/* MGBE0 Write mccif */ +#define TEGRA264_MEMORY_CLIENT_MGBE0W 0x1a3 +/* MGBE1 Read mccif */ +#define TEGRA264_MEMORY_CLIENT_MGBE1R 0x1a4 +/* MGBE1 Write mccif */ +#define TEGRA264_MEMORY_CLIENT_MGBE1W 0x1a5 +/* VI1 R5 Write client */ +#define TEGRA264_MEMORY_CLIENT_VI1W 0x1a6 +/* SDMMC0 Read mccif */ +#define TEGRA264_MEMORY_CLIENT_SDMMC0R 0x1c2 +/* SDMMC0 Write mccif */ +#define TEGRA264_MEMORY_CLIENT_SDMMC0W 0x1c3 + +#endif /* DT_BINDINGS_MEMORY_NVIDIA_TEGRA264_H */ diff --git a/include/dt-bindings/pinctrl/amlogic,pinctrl.h b/include/dt-bindings/pinctrl/amlogic,pinctrl.h new file mode 100644 index 000000000000..7d40aecc7147 --- /dev/null +++ b/include/dt-bindings/pinctrl/amlogic,pinctrl.h @@ -0,0 +1,46 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */ +/* + * Copyright (c) 2024 Amlogic, Inc. All rights reserved. + * Author: Xianwei Zhao <xianwei.zhao@amlogic.com> + */ + +#ifndef _DT_BINDINGS_AMLOGIC_PINCTRL_H +#define _DT_BINDINGS_AMLOGIC_PINCTRL_H +/* Normal PIN bank */ +#define AMLOGIC_GPIO_A 0 +#define AMLOGIC_GPIO_B 1 +#define AMLOGIC_GPIO_C 2 +#define AMLOGIC_GPIO_D 3 +#define AMLOGIC_GPIO_E 4 +#define AMLOGIC_GPIO_F 5 +#define AMLOGIC_GPIO_G 6 +#define AMLOGIC_GPIO_H 7 +#define AMLOGIC_GPIO_I 8 +#define AMLOGIC_GPIO_J 9 +#define AMLOGIC_GPIO_K 10 +#define AMLOGIC_GPIO_L 11 +#define AMLOGIC_GPIO_M 12 +#define AMLOGIC_GPIO_N 13 +#define AMLOGIC_GPIO_O 14 +#define AMLOGIC_GPIO_P 15 +#define AMLOGIC_GPIO_Q 16 +#define AMLOGIC_GPIO_R 17 +#define AMLOGIC_GPIO_S 18 +#define AMLOGIC_GPIO_T 19 +#define AMLOGIC_GPIO_U 20 +#define AMLOGIC_GPIO_V 21 +#define AMLOGIC_GPIO_W 22 +#define AMLOGIC_GPIO_X 23 +#define AMLOGIC_GPIO_Y 24 +#define AMLOGIC_GPIO_Z 25 + +/* Special PIN bank */ +#define AMLOGIC_GPIO_DV 26 +#define AMLOGIC_GPIO_AO 27 +#define AMLOGIC_GPIO_CC 28 +#define AMLOGIC_GPIO_TEST_N 29 +#define AMLOGIC_GPIO_ANALOG 30 + +#define AML_PINMUX(bank, offset, mode) (((((bank) << 8) + (offset)) << 8) | (mode)) + +#endif /* _DT_BINDINGS_AMLOGIC_PINCTRL_H */ diff --git a/include/dt-bindings/pinctrl/pinctrl-sg2042.h b/include/dt-bindings/pinctrl/pinctrl-sg2042.h new file mode 100644 index 000000000000..79d5bb8e04f8 --- /dev/null +++ b/include/dt-bindings/pinctrl/pinctrl-sg2042.h @@ -0,0 +1,196 @@ +/* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */ +/* + * Copyright (C) 2024 Inochi Amaoto <inochiama@outlook.com> + * + */ + +#ifndef _DT_BINDINGS_PINCTRL_SG2042_H +#define _DT_BINDINGS_PINCTRL_SG2042_H + +#define PINMUX(pin, mux) \ + (((pin) & 0xffff) | (((mux) & 0xff) << 16)) + +#define PIN_LPC_LCLK 0 +#define PIN_LPC_LFRAME 1 +#define PIN_LPC_LAD0 2 +#define PIN_LPC_LAD1 3 +#define PIN_LPC_LAD2 4 +#define PIN_LPC_LAD3 5 +#define PIN_LPC_LDRQ0 6 +#define PIN_LPC_LDRQ1 7 +#define PIN_LPC_SERIRQ 8 +#define PIN_LPC_CLKRUN 9 +#define PIN_LPC_LPME 10 +#define PIN_LPC_LPCPD 11 +#define PIN_LPC_LSMI 12 +#define PIN_PCIE0_L0_RESET 13 +#define PIN_PCIE0_L1_RESET 14 +#define PIN_PCIE0_L0_WAKEUP 15 +#define PIN_PCIE0_L1_WAKEUP 16 +#define PIN_PCIE0_L0_CLKREQ_IN 17 +#define PIN_PCIE0_L1_CLKREQ_IN 18 +#define PIN_PCIE1_L0_RESET 19 +#define PIN_PCIE1_L1_RESET 20 +#define PIN_PCIE1_L0_WAKEUP 21 +#define PIN_PCIE1_L1_WAKEUP 22 +#define PIN_PCIE1_L0_CLKREQ_IN 23 +#define PIN_PCIE1_L1_CLKREQ_IN 24 +#define PIN_SPIF0_CLK_SEL1 25 +#define PIN_SPIF0_CLK_SEL0 26 +#define PIN_SPIF0_WP 27 +#define PIN_SPIF0_HOLD 28 +#define PIN_SPIF0_SDI 29 +#define PIN_SPIF0_CS 30 +#define PIN_SPIF0_SCK 31 +#define PIN_SPIF0_SDO 32 +#define PIN_SPIF1_CLK_SEL1 33 +#define PIN_SPIF1_CLK_SEL0 34 +#define PIN_SPIF1_WP 35 +#define PIN_SPIF1_HOLD 36 +#define PIN_SPIF1_SDI 37 +#define PIN_SPIF1_CS 38 +#define PIN_SPIF1_SCK 39 +#define PIN_SPIF1_SDO 40 +#define PIN_EMMC_WP 41 +#define PIN_EMMC_CD 42 +#define PIN_EMMC_RST 43 +#define PIN_EMMC_PWR_EN 44 +#define PIN_SDIO_CD 45 +#define PIN_SDIO_WP 46 +#define PIN_SDIO_RST 47 +#define PIN_SDIO_PWR_EN 48 +#define PIN_RGMII0_TXD0 49 +#define PIN_RGMII0_TXD1 50 +#define PIN_RGMII0_TXD2 51 +#define PIN_RGMII0_TXD3 52 +#define PIN_RGMII0_TXCTRL 53 +#define PIN_RGMII0_RXD0 54 +#define PIN_RGMII0_RXD1 55 +#define PIN_RGMII0_RXD2 56 +#define PIN_RGMII0_RXD3 57 +#define PIN_RGMII0_RXCTRL 58 +#define PIN_RGMII0_TXC 59 +#define PIN_RGMII0_RXC 60 +#define PIN_RGMII0_REFCLKO 61 +#define PIN_RGMII0_IRQ 62 +#define PIN_RGMII0_MDC 63 +#define PIN_RGMII0_MDIO 64 +#define PIN_PWM0 65 +#define PIN_PWM1 66 +#define PIN_PWM2 67 +#define PIN_PWM3 68 +#define PIN_FAN0 69 +#define PIN_FAN1 70 +#define PIN_FAN2 71 +#define PIN_FAN3 72 +#define PIN_IIC0_SDA 73 +#define PIN_IIC0_SCL 74 +#define PIN_IIC1_SDA 75 +#define PIN_IIC1_SCL 76 +#define PIN_IIC2_SDA 77 +#define PIN_IIC2_SCL 78 +#define PIN_IIC3_SDA 79 +#define PIN_IIC3_SCL 80 +#define PIN_UART0_TX 81 +#define PIN_UART0_RX 82 +#define PIN_UART0_RTS 83 +#define PIN_UART0_CTS 84 +#define PIN_UART1_TX 85 +#define PIN_UART1_RX 86 +#define PIN_UART1_RTS 87 +#define PIN_UART1_CTS 88 +#define PIN_UART2_TX 89 +#define PIN_UART2_RX 90 +#define PIN_UART2_RTS 91 +#define PIN_UART2_CTS 92 +#define PIN_UART3_TX 93 +#define PIN_UART3_RX 94 +#define PIN_UART3_RTS 95 +#define PIN_UART3_CTS 96 +#define PIN_SPI0_CS0 97 +#define PIN_SPI0_CS1 98 +#define PIN_SPI0_SDI 99 +#define PIN_SPI0_SDO 100 +#define PIN_SPI0_SCK 101 +#define PIN_SPI1_CS0 102 +#define PIN_SPI1_CS1 103 +#define PIN_SPI1_SDI 104 +#define PIN_SPI1_SDO 105 +#define PIN_SPI1_SCK 106 +#define PIN_JTAG0_TDO 107 +#define PIN_JTAG0_TCK 108 +#define PIN_JTAG0_TDI 109 +#define PIN_JTAG0_TMS 110 +#define PIN_JTAG0_TRST 111 +#define PIN_JTAG0_SRST 112 +#define PIN_JTAG1_TDO 113 +#define PIN_JTAG1_TCK 114 +#define PIN_JTAG1_TDI 115 +#define PIN_JTAG1_TMS 116 +#define PIN_JTAG1_TRST 117 +#define PIN_JTAG1_SRST 118 +#define PIN_JTAG2_TDO 119 +#define PIN_JTAG2_TCK 120 +#define PIN_JTAG2_TDI 121 +#define PIN_JTAG2_TMS 122 +#define PIN_JTAG2_TRST 123 +#define PIN_JTAG2_SRST 124 +#define PIN_GPIO0 125 +#define PIN_GPIO1 126 +#define PIN_GPIO2 127 +#define PIN_GPIO3 128 +#define PIN_GPIO4 129 +#define PIN_GPIO5 130 +#define PIN_GPIO6 131 +#define PIN_GPIO7 132 +#define PIN_GPIO8 133 +#define PIN_GPIO9 134 +#define PIN_GPIO10 135 +#define PIN_GPIO11 136 +#define PIN_GPIO12 137 +#define PIN_GPIO13 138 +#define PIN_GPIO14 139 +#define PIN_GPIO15 140 +#define PIN_GPIO16 141 +#define PIN_GPIO17 142 +#define PIN_GPIO18 143 +#define PIN_GPIO19 144 +#define PIN_GPIO20 145 +#define PIN_GPIO21 146 +#define PIN_GPIO22 147 +#define PIN_GPIO23 148 +#define PIN_GPIO24 149 +#define PIN_GPIO25 150 +#define PIN_GPIO26 151 +#define PIN_GPIO27 152 +#define PIN_GPIO28 153 +#define PIN_GPIO29 154 +#define PIN_GPIO30 155 +#define PIN_GPIO31 156 +#define PIN_MODE_SEL0 157 +#define PIN_MODE_SEL1 158 +#define PIN_MODE_SEL2 159 +#define PIN_BOOT_SEL0 160 +#define PIN_BOOT_SEL1 161 +#define PIN_BOOT_SEL2 162 +#define PIN_BOOT_SEL3 163 +#define PIN_BOOT_SEL4 164 +#define PIN_BOOT_SEL5 165 +#define PIN_BOOT_SEL6 166 +#define PIN_BOOT_SEL7 167 +#define PIN_MULTI_SCKT 168 +#define PIN_SCKT_ID0 169 +#define PIN_SCKT_ID1 170 +#define PIN_PLL_CLK_IN_MAIN 171 +#define PIN_PLL_CLK_IN_DDR_L 172 +#define PIN_PLL_CLK_IN_DDR_R 173 +#define PIN_XTAL_32K 174 +#define PIN_SYS_RST 175 +#define PIN_PWR_BUTTON 176 +#define PIN_TEST_EN 177 +#define PIN_TEST_MODE_MBIST 178 +#define PIN_TEST_MODE_SCAN 179 +#define PIN_TEST_MODE_BSD 180 +#define PIN_BISR_BYP 181 + +#endif /* _DT_BINDINGS_PINCTRL_SG2042_H */ diff --git a/include/dt-bindings/pinctrl/pinctrl-sg2044.h b/include/dt-bindings/pinctrl/pinctrl-sg2044.h new file mode 100644 index 000000000000..2a619f681c39 --- /dev/null +++ b/include/dt-bindings/pinctrl/pinctrl-sg2044.h @@ -0,0 +1,221 @@ +/* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */ +/* + * Copyright (C) 2024 Inochi Amaoto <inochiama@outlook.com> + * + */ + +#ifndef _DT_BINDINGS_PINCTRL_SG2044_H +#define _DT_BINDINGS_PINCTRL_SG2044_H + +#define PINMUX(pin, mux) \ + (((pin) & 0xffff) | (((mux) & 0xff) << 16)) + +#define PIN_IIC0_SMBSUS_IN 0 +#define PIN_IIC0_SMBSUS_OUT 1 +#define PIN_IIC0_SMBALERT 2 +#define PIN_IIC1_SMBSUS_IN 3 +#define PIN_IIC1_SMBSUS_OUT 4 +#define PIN_IIC1_SMBALERT 5 +#define PIN_IIC2_SMBSUS_IN 6 +#define PIN_IIC2_SMBSUS_OUT 7 +#define PIN_IIC2_SMBALERT 8 +#define PIN_IIC3_SMBSUS_IN 9 +#define PIN_IIC3_SMBSUS_OUT 10 +#define PIN_IIC3_SMBALERT 11 +#define PIN_PCIE0_L0_RESET 12 +#define PIN_PCIE0_L1_RESET 13 +#define PIN_PCIE0_L0_WAKEUP 14 +#define PIN_PCIE0_L1_WAKEUP 15 +#define PIN_PCIE0_L0_CLKREQ_IN 16 +#define PIN_PCIE0_L1_CLKREQ_IN 17 +#define PIN_PCIE1_L0_RESET 18 +#define PIN_PCIE1_L1_RESET 19 +#define PIN_PCIE1_L0_WAKEUP 20 +#define PIN_PCIE1_L1_WAKEUP 21 +#define PIN_PCIE1_L0_CLKREQ_IN 22 +#define PIN_PCIE1_L1_CLKREQ_IN 23 +#define PIN_PCIE2_L0_RESET 24 +#define PIN_PCIE2_L1_RESET 25 +#define PIN_PCIE2_L0_WAKEUP 26 +#define PIN_PCIE2_L1_WAKEUP 27 +#define PIN_PCIE2_L0_CLKREQ_IN 28 +#define PIN_PCIE2_L1_CLKREQ_IN 29 +#define PIN_PCIE3_L0_RESET 30 +#define PIN_PCIE3_L1_RESET 31 +#define PIN_PCIE3_L0_WAKEUP 32 +#define PIN_PCIE3_L1_WAKEUP 33 +#define PIN_PCIE3_L0_CLKREQ_IN 34 +#define PIN_PCIE3_L1_CLKREQ_IN 35 +#define PIN_PCIE4_L0_RESET 36 +#define PIN_PCIE4_L1_RESET 37 +#define PIN_PCIE4_L0_WAKEUP 38 +#define PIN_PCIE4_L1_WAKEUP 39 +#define PIN_PCIE4_L0_CLKREQ_IN 40 +#define PIN_PCIE4_L1_CLKREQ_IN 41 +#define PIN_SPIF0_CLK_SEL1 42 +#define PIN_SPIF0_CLK_SEL0 43 +#define PIN_SPIF0_WP 44 +#define PIN_SPIF0_HOLD 45 +#define PIN_SPIF0_SDI 46 +#define PIN_SPIF0_CS 47 +#define PIN_SPIF0_SCK 48 +#define PIN_SPIF0_SDO 49 +#define PIN_SPIF1_CLK_SEL1 50 +#define PIN_SPIF1_CLK_SEL0 51 +#define PIN_SPIF1_WP 52 +#define PIN_SPIF1_HOLD 53 +#define PIN_SPIF1_SDI 54 +#define PIN_SPIF1_CS 55 +#define PIN_SPIF1_SCK 56 +#define PIN_SPIF1_SDO 57 +#define PIN_EMMC_WP 58 +#define PIN_EMMC_CD 59 +#define PIN_EMMC_RST 60 +#define PIN_EMMC_PWR_EN 61 +#define PIN_SDIO_CD 62 +#define PIN_SDIO_WP 63 +#define PIN_SDIO_RST 64 +#define PIN_SDIO_PWR_EN 65 +#define PIN_RGMII0_TXD0 66 +#define PIN_RGMII0_TXD1 67 +#define PIN_RGMII0_TXD2 68 +#define PIN_RGMII0_TXD3 69 +#define PIN_RGMII0_TXCTRL 70 +#define PIN_RGMII0_RXD0 71 +#define PIN_RGMII0_RXD1 72 +#define PIN_RGMII0_RXD2 73 +#define PIN_RGMII0_RXD3 74 +#define PIN_RGMII0_RXCTRL 75 +#define PIN_RGMII0_TXC 76 +#define PIN_RGMII0_RXC 77 +#define PIN_RGMII0_REFCLKO 78 +#define PIN_RGMII0_IRQ 79 +#define PIN_RGMII0_MDC 80 +#define PIN_RGMII0_MDIO 81 +#define PIN_PWM0 82 +#define PIN_PWM1 83 +#define PIN_PWM2 84 +#define PIN_PWM3 85 +#define PIN_FAN0 86 +#define PIN_FAN1 87 +#define PIN_FAN2 88 +#define PIN_FAN3 89 +#define PIN_IIC0_SDA 90 +#define PIN_IIC0_SCL 91 +#define PIN_IIC1_SDA 92 +#define PIN_IIC1_SCL 93 +#define PIN_IIC2_SDA 94 +#define PIN_IIC2_SCL 95 +#define PIN_IIC3_SDA 96 +#define PIN_IIC3_SCL 97 +#define PIN_UART0_TX 98 +#define PIN_UART0_RX 99 +#define PIN_UART0_RTS 100 +#define PIN_UART0_CTS 101 +#define PIN_UART1_TX 102 +#define PIN_UART1_RX 103 +#define PIN_UART1_RTS 104 +#define PIN_UART1_CTS 105 +#define PIN_UART2_TX 106 +#define PIN_UART2_RX 107 +#define PIN_UART2_RTS 108 +#define PIN_UART2_CTS 109 +#define PIN_UART3_TX 110 +#define PIN_UART3_RX 111 +#define PIN_UART3_RTS 112 +#define PIN_UART3_CTS 113 +#define PIN_SPI0_CS0 114 +#define PIN_SPI0_CS1 115 +#define PIN_SPI0_SDI 116 +#define PIN_SPI0_SDO 117 +#define PIN_SPI0_SCK 118 +#define PIN_SPI1_CS0 119 +#define PIN_SPI1_CS1 120 +#define PIN_SPI1_SDI 121 +#define PIN_SPI1_SDO 122 +#define PIN_SPI1_SCK 123 +#define PIN_JTAG0_TDO 124 +#define PIN_JTAG0_TCK 125 +#define PIN_JTAG0_TDI 126 +#define PIN_JTAG0_TMS 127 +#define PIN_JTAG0_TRST 128 +#define PIN_JTAG0_SRST 129 +#define PIN_JTAG1_TDO 130 +#define PIN_JTAG1_TCK 131 +#define PIN_JTAG1_TDI 132 +#define PIN_JTAG1_TMS 133 +#define PIN_JTAG1_TRST 134 +#define PIN_JTAG1_SRST 135 +#define PIN_JTAG2_TDO 136 +#define PIN_JTAG2_TCK 137 +#define PIN_JTAG2_TDI 138 +#define PIN_JTAG2_TMS 139 +#define PIN_JTAG2_TRST 140 +#define PIN_JTAG2_SRST 141 +#define PIN_JTAG3_TDO 142 +#define PIN_JTAG3_TCK 143 +#define PIN_JTAG3_TDI 144 +#define PIN_JTAG3_TMS 145 +#define PIN_JTAG3_TRST 146 +#define PIN_JTAG3_SRST 147 +#define PIN_GPIO0 148 +#define PIN_GPIO1 149 +#define PIN_GPIO2 150 +#define PIN_GPIO3 151 +#define PIN_GPIO4 152 +#define PIN_GPIO5 153 +#define PIN_GPIO6 154 +#define PIN_GPIO7 155 +#define PIN_GPIO8 156 +#define PIN_GPIO9 157 +#define PIN_GPIO10 158 +#define PIN_GPIO11 159 +#define PIN_GPIO12 160 +#define PIN_GPIO13 161 +#define PIN_GPIO14 162 +#define PIN_GPIO15 163 +#define PIN_GPIO16 164 +#define PIN_GPIO17 165 +#define PIN_GPIO18 166 +#define PIN_GPIO19 167 +#define PIN_GPIO20 168 +#define PIN_GPIO21 169 +#define PIN_GPIO22 170 +#define PIN_GPIO23 171 +#define PIN_GPIO24 172 +#define PIN_GPIO25 173 +#define PIN_GPIO26 174 +#define PIN_GPIO27 175 +#define PIN_GPIO28 176 +#define PIN_GPIO29 177 +#define PIN_GPIO30 178 +#define PIN_GPIO31 179 +#define PIN_MODE_SEL0 180 +#define PIN_MODE_SEL1 181 +#define PIN_MODE_SEL2 182 +#define PIN_BOOT_SEL0 183 +#define PIN_BOOT_SEL1 184 +#define PIN_BOOT_SEL2 185 +#define PIN_BOOT_SEL3 186 +#define PIN_BOOT_SEL4 187 +#define PIN_BOOT_SEL5 188 +#define PIN_BOOT_SEL6 189 +#define PIN_BOOT_SEL7 190 +#define PIN_MULTI_SCKT 191 +#define PIN_SCKT_ID0 192 +#define PIN_SCKT_ID1 193 +#define PIN_PLL_CLK_IN_MAIN 194 +#define PIN_PLL_CLK_IN_DDR_0 195 +#define PIN_PLL_CLK_IN_DDR_1 196 +#define PIN_PLL_CLK_IN_DDR_2 197 +#define PIN_PLL_CLK_IN_DDR_3 198 +#define PIN_XTAL_32K 199 +#define PIN_SYS_RST 200 +#define PIN_PWR_BUTTON 201 +#define PIN_TEST_EN 202 +#define PIN_TEST_MODE_MBIST 203 +#define PIN_TEST_MODE_SCAN 204 +#define PIN_TEST_MODE_BSD 205 +#define PIN_BISR_BYP 206 + +#endif /* _DT_BINDINGS_PINCTRL_SG2044_H */ diff --git a/include/dt-bindings/pinctrl/stm32-pinfunc.h b/include/dt-bindings/pinctrl/stm32-pinfunc.h index 28ad0235086a..af3fd388329a 100644 --- a/include/dt-bindings/pinctrl/stm32-pinfunc.h +++ b/include/dt-bindings/pinctrl/stm32-pinfunc.h @@ -26,6 +26,7 @@ #define AF14 0xf #define AF15 0x10 #define ANALOG 0x11 +#define RSVD 0x12 /* define Pins number*/ #define PIN_NO(port, line) (((port) - 'A') * 0x10 + (line)) diff --git a/include/dt-bindings/power/allwinner,sun55i-a523-pck-600.h b/include/dt-bindings/power/allwinner,sun55i-a523-pck-600.h new file mode 100644 index 000000000000..6b3d8ea7bb69 --- /dev/null +++ b/include/dt-bindings/power/allwinner,sun55i-a523-pck-600.h @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ + +#ifndef _DT_BINDINGS_POWER_SUN55I_A523_PCK600_H_ +#define _DT_BINDINGS_POWER_SUN55I_A523_PCK600_H_ + +#define PD_VE 0 +#define PD_GPU 1 +#define PD_VI 2 +#define PD_VO0 3 +#define PD_VO1 4 +#define PD_DE 5 +#define PD_NAND 6 +#define PD_PCIE 7 + +#endif /* _DT_BINDINGS_POWER_SUN55I_A523_PCK600_H_ */ diff --git a/include/dt-bindings/power/allwinner,sun55i-a523-ppu.h b/include/dt-bindings/power/allwinner,sun55i-a523-ppu.h new file mode 100644 index 000000000000..bc9aba73c19a --- /dev/null +++ b/include/dt-bindings/power/allwinner,sun55i-a523-ppu.h @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ + +#ifndef _DT_BINDINGS_POWER_SUN55I_A523_PPU_H_ +#define _DT_BINDINGS_POWER_SUN55I_A523_PPU_H_ + +#define PD_DSP 0 +#define PD_NPU 1 +#define PD_AUDIO 2 +#define PD_SRAM 3 +#define PD_RISCV 4 + +#endif /* _DT_BINDINGS_POWER_SUN55I_A523_PPU_H_ */ diff --git a/include/dt-bindings/power/allwinner,sun8i-v853-ppu.h b/include/dt-bindings/power/allwinner,sun8i-v853-ppu.h new file mode 100644 index 000000000000..b1c18a490613 --- /dev/null +++ b/include/dt-bindings/power/allwinner,sun8i-v853-ppu.h @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ + +#ifndef _DT_BINDINGS_POWER_SUN8I_V853_PPU_H_ +#define _DT_BINDINGS_POWER_SUN8I_V853_PPU_H_ + +#define PD_RISCV 0 +#define PD_NPU 1 +#define PD_VE 2 + +#endif diff --git a/include/dt-bindings/power/mediatek,mt6893-power.h b/include/dt-bindings/power/mediatek,mt6893-power.h new file mode 100644 index 000000000000..aeab51bb2ad8 --- /dev/null +++ b/include/dt-bindings/power/mediatek,mt6893-power.h @@ -0,0 +1,35 @@ +/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */ +/* + * Copyright (c) 2025 Collabora Ltd + * AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> + */ + +#ifndef _DT_BINDINGS_POWER_MT6893_POWER_H +#define _DT_BINDINGS_POWER_MT6893_POWER_H + +#define MT6893_POWER_DOMAIN_CONN 0 +#define MT6893_POWER_DOMAIN_MFG0 1 +#define MT6893_POWER_DOMAIN_MFG1 2 +#define MT6893_POWER_DOMAIN_MFG2 3 +#define MT6893_POWER_DOMAIN_MFG3 4 +#define MT6893_POWER_DOMAIN_MFG4 5 +#define MT6893_POWER_DOMAIN_MFG5 6 +#define MT6893_POWER_DOMAIN_MFG6 7 +#define MT6893_POWER_DOMAIN_ISP 8 +#define MT6893_POWER_DOMAIN_ISP2 9 +#define MT6893_POWER_DOMAIN_IPE 10 +#define MT6893_POWER_DOMAIN_VDEC0 11 +#define MT6893_POWER_DOMAIN_VDEC1 12 +#define MT6893_POWER_DOMAIN_VENC0 13 +#define MT6893_POWER_DOMAIN_VENC1 14 +#define MT6893_POWER_DOMAIN_MDP 15 +#define MT6893_POWER_DOMAIN_DISP 16 +#define MT6893_POWER_DOMAIN_AUDIO 17 +#define MT6893_POWER_DOMAIN_ADSP 18 +#define MT6893_POWER_DOMAIN_CAM 19 +#define MT6893_POWER_DOMAIN_CAM_RAWA 20 +#define MT6893_POWER_DOMAIN_CAM_RAWB 21 +#define MT6893_POWER_DOMAIN_CAM_RAWC 22 +#define MT6893_POWER_DOMAIN_DP_TX 23 + +#endif /* _DT_BINDINGS_POWER_MT6893_POWER_H */ diff --git a/include/dt-bindings/power/qcom-rpmpd.h b/include/dt-bindings/power/qcom-rpmpd.h index df599bf46220..f15bcee7c928 100644 --- a/include/dt-bindings/power/qcom-rpmpd.h +++ b/include/dt-bindings/power/qcom-rpmpd.h @@ -65,7 +65,7 @@ #define SM6350_MSS 4 #define SM6350_MX 5 -/* SM6350 Power Domain Indexes */ +/* SM6375 Power Domain Indexes */ #define SM6375_VDDCX 0 #define SM6375_VDDCX_AO 1 #define SM6375_VDDCX_VFL 2 @@ -240,6 +240,7 @@ #define RPMH_REGULATOR_LEVEL_TURBO_L2 432 #define RPMH_REGULATOR_LEVEL_TURBO_L3 448 #define RPMH_REGULATOR_LEVEL_TURBO_L4 452 +#define RPMH_REGULATOR_LEVEL_TURBO_L5 456 #define RPMH_REGULATOR_LEVEL_SUPER_TURBO 464 #define RPMH_REGULATOR_LEVEL_SUPER_TURBO_NO_CPR 480 diff --git a/include/dt-bindings/power/rockchip,rk3528-power.h b/include/dt-bindings/power/rockchip,rk3528-power.h new file mode 100644 index 000000000000..318923cdaaf6 --- /dev/null +++ b/include/dt-bindings/power/rockchip,rk3528-power.h @@ -0,0 +1,19 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +#ifndef __DT_BINDINGS_POWER_RK3528_POWER_H__ +#define __DT_BINDINGS_POWER_RK3528_POWER_H__ + +#define RK3528_PD_PMU 0 +#define RK3528_PD_BUS 1 +#define RK3528_PD_DDR 2 +#define RK3528_PD_MSCH 3 + +/* VD_GPU */ +#define RK3528_PD_GPU 4 + +/* VD_LOGIC */ +#define RK3528_PD_RKVDEC 5 +#define RK3528_PD_RKVENC 6 +#define RK3528_PD_VO 7 +#define RK3528_PD_VPU 8 + +#endif diff --git a/include/dt-bindings/power/rockchip,rk3562-power.h b/include/dt-bindings/power/rockchip,rk3562-power.h new file mode 100644 index 000000000000..5182c2427a55 --- /dev/null +++ b/include/dt-bindings/power/rockchip,rk3562-power.h @@ -0,0 +1,35 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) 2022-2024 Rockchip Electronics Co., Ltd. + */ +#ifndef __DT_BINDINGS_POWER_RK3562_POWER_H__ +#define __DT_BINDINGS_POWER_RK3562_POWER_H__ + +/* VD_CORE */ +#define RK3562_PD_CPU_0 0 +#define RK3562_PD_CPU_1 1 +#define RK3562_PD_CPU_2 2 +#define RK3562_PD_CPU_3 3 +#define RK3562_PD_CORE_ALIVE 4 + +/* VD_PMU */ +#define RK3562_PD_PMU 5 +#define RK3562_PD_PMU_ALIVE 6 + +/* VD_NPU */ +#define RK3562_PD_NPU 7 + +/* VD_GPU */ +#define RK3562_PD_GPU 8 + +/* VD_LOGIC */ +#define RK3562_PD_DDR 9 +#define RK3562_PD_VEPU 10 +#define RK3562_PD_VDPU 11 +#define RK3562_PD_VI 12 +#define RK3562_PD_VO 13 +#define RK3562_PD_RGA 14 +#define RK3562_PD_PHP 15 +#define RK3562_PD_LOGIC_ALIVE 16 + +#endif diff --git a/include/dt-bindings/power/thead,th1520-power.h b/include/dt-bindings/power/thead,th1520-power.h new file mode 100644 index 000000000000..8395bd1459f3 --- /dev/null +++ b/include/dt-bindings/power/thead,th1520-power.h @@ -0,0 +1,19 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (C) 2022 Alibaba Group Holding Limited. + * Copyright (c) 2024 Samsung Electronics Co., Ltd. + * Author: Michal Wilczynski <m.wilczynski@samsung.com> + */ + +#ifndef __DT_BINDINGS_POWER_TH1520_H +#define __DT_BINDINGS_POWER_TH1520_H + +#define TH1520_AUDIO_PD 0 +#define TH1520_VDEC_PD 1 +#define TH1520_NPU_PD 2 +#define TH1520_VENC_PD 3 +#define TH1520_GPU_PD 4 +#define TH1520_DSP0_PD 5 +#define TH1520_DSP1_PD 6 + +#endif diff --git a/include/dt-bindings/regulator/nxp,pca9450-regulator.h b/include/dt-bindings/regulator/nxp,pca9450-regulator.h new file mode 100644 index 000000000000..08434caef429 --- /dev/null +++ b/include/dt-bindings/regulator/nxp,pca9450-regulator.h @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Device Tree binding constants for the NXP PCA9450A/B/C PMIC regulators + */ + +#ifndef _DT_BINDINGS_REGULATORS_NXP_PCA9450_H +#define _DT_BINDINGS_REGULATORS_NXP_PCA9450_H + +/* + * Buck mode constants which may be used in devicetree properties (eg. + * regulator-initial-mode, regulator-allowed-modes). + * See the manufacturer's datasheet for more information on these modes. + */ + +#define PCA9450_BUCK_MODE_AUTO 0 +#define PCA9450_BUCK_MODE_FORCE_PWM 1 + +#endif diff --git a/include/dt-bindings/regulator/st,stm32mp15-regulator.h b/include/dt-bindings/regulator/st,stm32mp15-regulator.h new file mode 100644 index 000000000000..7052507cb3e5 --- /dev/null +++ b/include/dt-bindings/regulator/st,stm32mp15-regulator.h @@ -0,0 +1,40 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (C) 2025, STMicroelectronics - All Rights Reserved + */ + +#ifndef __DT_BINDINGS_REGULATOR_ST_STM32MP15_REGULATOR_H +#define __DT_BINDINGS_REGULATOR_ST_STM32MP15_REGULATOR_H + +/* SCMI voltage domain identifiers */ + +/* SOC Internal regulators */ +#define VOLTD_SCMI_REG11 0 +#define VOLTD_SCMI_REG18 1 +#define VOLTD_SCMI_USB33 2 + +/* STPMIC1 regulators */ +#define VOLTD_SCMI_STPMIC1_BUCK1 3 +#define VOLTD_SCMI_STPMIC1_BUCK2 4 +#define VOLTD_SCMI_STPMIC1_BUCK3 5 +#define VOLTD_SCMI_STPMIC1_BUCK4 6 +#define VOLTD_SCMI_STPMIC1_LDO1 7 +#define VOLTD_SCMI_STPMIC1_LDO2 8 +#define VOLTD_SCMI_STPMIC1_LDO3 9 +#define VOLTD_SCMI_STPMIC1_LDO4 10 +#define VOLTD_SCMI_STPMIC1_LDO5 11 +#define VOLTD_SCMI_STPMIC1_LDO6 12 +#define VOLTD_SCMI_STPMIC1_VREFDDR 13 +#define VOLTD_SCMI_STPMIC1_BOOST 14 +#define VOLTD_SCMI_STPMIC1_PWR_SW1 15 +#define VOLTD_SCMI_STPMIC1_PWR_SW2 16 +#define VOLTD_SCMI_VREFBUF 17 + +/* External regulators */ +#define VOLTD_SCMI_REGU0 18 +#define VOLTD_SCMI_REGU1 19 +#define VOLTD_SCMI_REGU2 20 +#define VOLTD_SCMI_REGU3 21 +#define VOLTD_SCMI_REGU4 22 + +#endif /*__DT_BINDINGS_REGULATOR_ST_STM32MP15_REGULATOR_H */ diff --git a/include/dt-bindings/reset/amlogic,meson-a1-audio-reset.h b/include/dt-bindings/reset/amlogic,meson-a1-audio-reset.h new file mode 100644 index 000000000000..7693552f1507 --- /dev/null +++ b/include/dt-bindings/reset/amlogic,meson-a1-audio-reset.h @@ -0,0 +1,36 @@ +/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */ +/* + * Copyright (c) 2024, SaluteDevices. All Rights Reserved. + * + * Author: Jan Dakinevich <jan.dakinevich@salutedevices.com> + */ + +#ifndef _DT_BINDINGS_AMLOGIC_MESON_A1_AUDIO_RESET_H +#define _DT_BINDINGS_AMLOGIC_MESON_A1_AUDIO_RESET_H + +#define AUD_RESET_DDRARB 0 +#define AUD_RESET_TDMIN_A 1 +#define AUD_RESET_TDMIN_B 2 +#define AUD_RESET_TDMIN_LB 3 +#define AUD_RESET_LOOPBACK 4 +#define AUD_RESET_TDMOUT_A 5 +#define AUD_RESET_TDMOUT_B 6 +#define AUD_RESET_FRDDR_A 7 +#define AUD_RESET_FRDDR_B 8 +#define AUD_RESET_TODDR_A 9 +#define AUD_RESET_TODDR_B 10 +#define AUD_RESET_SPDIFIN 11 +#define AUD_RESET_RESAMPLE 12 +#define AUD_RESET_EQDRC 13 +#define AUD_RESET_LOCKER 14 +#define AUD_RESET_TOACODEC 30 +#define AUD_RESET_CLKTREE 31 + +#define AUD_VAD_RESET_DDRARB 0 +#define AUD_VAD_RESET_PDM 1 +#define AUD_VAD_RESET_TDMIN_VAD 2 +#define AUD_VAD_RESET_TODDR_VAD 3 +#define AUD_VAD_RESET_TOVAD 4 +#define AUD_VAD_RESET_CLKTREE 5 + +#endif /* _DT_BINDINGS_AMLOGIC_MESON_A1_AUDIO_RESET_H */ diff --git a/include/dt-bindings/reset/canaan,k230-rst.h b/include/dt-bindings/reset/canaan,k230-rst.h new file mode 100644 index 000000000000..e4f6612607fe --- /dev/null +++ b/include/dt-bindings/reset/canaan,k230-rst.h @@ -0,0 +1,90 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (C) 2023-2024 Canaan Bright Sight Co., Ltd + * Copyright (C) 2024-2025 Junhui Liu <junhui.liu@pigmoral.tech> + */ +#ifndef _DT_BINDINGS_CANAAN_K230_RST_H_ +#define _DT_BINDINGS_CANAAN_K230_RST_H_ + +#define RST_CPU0 0 +#define RST_CPU1 1 +#define RST_CPU0_FLUSH 2 +#define RST_CPU1_FLUSH 3 +#define RST_AI 4 +#define RST_VPU 5 +#define RST_HISYS 6 +#define RST_HISYS_AHB 7 +#define RST_SDIO0 8 +#define RST_SDIO1 9 +#define RST_SDIO_AXI 10 +#define RST_USB0 11 +#define RST_USB1 12 +#define RST_USB0_AHB 13 +#define RST_USB1_AHB 14 +#define RST_SPI0 15 +#define RST_SPI1 16 +#define RST_SPI2 17 +#define RST_SEC 18 +#define RST_PDMA 19 +#define RST_SDMA 20 +#define RST_DECOMPRESS 21 +#define RST_SRAM 22 +#define RST_SHRM_AXIM 23 +#define RST_SHRM_AXIS 24 +#define RST_NONAI2D 25 +#define RST_MCTL 26 +#define RST_ISP 27 +#define RST_ISP_DW 28 +#define RST_DPU 29 +#define RST_DISP 30 +#define RST_GPU 31 +#define RST_AUDIO 32 +#define RST_TIMER0 33 +#define RST_TIMER1 34 +#define RST_TIMER2 35 +#define RST_TIMER3 36 +#define RST_TIMER4 37 +#define RST_TIMER5 38 +#define RST_TIMER_APB 39 +#define RST_HDI 40 +#define RST_WDT0 41 +#define RST_WDT1 42 +#define RST_WDT0_APB 43 +#define RST_WDT1_APB 44 +#define RST_TS_APB 45 +#define RST_MAILBOX 46 +#define RST_STC 47 +#define RST_PMU 48 +#define RST_LOSYS_APB 49 +#define RST_UART0 50 +#define RST_UART1 51 +#define RST_UART2 52 +#define RST_UART3 53 +#define RST_UART4 54 +#define RST_I2C0 55 +#define RST_I2C1 56 +#define RST_I2C2 57 +#define RST_I2C3 58 +#define RST_I2C4 59 +#define RST_JAMLINK0_APB 60 +#define RST_JAMLINK1_APB 61 +#define RST_JAMLINK2_APB 62 +#define RST_JAMLINK3_APB 63 +#define RST_CODEC_APB 64 +#define RST_GPIO_DB 65 +#define RST_GPIO_APB 66 +#define RST_ADC 67 +#define RST_ADC_APB 68 +#define RST_PWM_APB 69 +#define RST_SHRM_APB 70 +#define RST_CSI0 71 +#define RST_CSI1 72 +#define RST_CSI2 73 +#define RST_CSI_DPHY 74 +#define RST_ISP_AHB 75 +#define RST_M0 76 +#define RST_M1 77 +#define RST_M2 78 +#define RST_SPI2AXI 79 + +#endif diff --git a/include/dt-bindings/reset/imx8mp-reset-audiomix.h b/include/dt-bindings/reset/imx8mp-reset-audiomix.h new file mode 100644 index 000000000000..746c1337ed99 --- /dev/null +++ b/include/dt-bindings/reset/imx8mp-reset-audiomix.h @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0-only OR MIT */ +/* + * Copyright 2025 NXP + */ + +#ifndef DT_BINDING_RESET_IMX8MP_AUDIOMIX_H +#define DT_BINDING_RESET_IMX8MP_AUDIOMIX_H + +#define IMX8MP_AUDIOMIX_EARC_RESET 0 +#define IMX8MP_AUDIOMIX_EARC_PHY_RESET 1 +#define IMX8MP_AUDIOMIX_DSP_RUNSTALL 2 + +#endif /* DT_BINDING_RESET_IMX8MP_AUDIOMIX_H */ diff --git a/include/dt-bindings/reset/nvidia,tegra264.h b/include/dt-bindings/reset/nvidia,tegra264.h new file mode 100644 index 000000000000..a61a56bb232b --- /dev/null +++ b/include/dt-bindings/reset/nvidia,tegra264.h @@ -0,0 +1,92 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* Copyright (c) 2022-2025, NVIDIA CORPORATION. All rights reserved. */ + +#ifndef DT_BINDINGS_RESET_NVIDIA_TEGRA264_H +#define DT_BINDINGS_RESET_NVIDIA_TEGRA264_H + +#define TEGRA264_RESET_APE_TKE 1 +#define TEGRA264_RESET_CEC 2 +#define TEGRA264_RESET_ADSP_ALL 3 +#define TEGRA264_RESET_RCE_ALL 4 +#define TEGRA264_RESET_UFSHC 5 +#define TEGRA264_RESET_UFSHC_AXI_M 6 +#define TEGRA264_RESET_UFSHC_LP_SEQ 7 +#define TEGRA264_RESET_DPAUX 8 +#define TEGRA264_RESET_EQOS_PCS 9 +#define TEGRA264_RESET_HWPM 10 +#define TEGRA264_RESET_I2C1 11 +#define TEGRA264_RESET_I2C2 12 +#define TEGRA264_RESET_I2C3 13 +#define TEGRA264_RESET_I2C4 14 +#define TEGRA264_RESET_I2C6 15 +#define TEGRA264_RESET_I2C7 16 +#define TEGRA264_RESET_I2C8 17 +#define TEGRA264_RESET_I2C9 18 +#define TEGRA264_RESET_ISP 19 +#define TEGRA264_RESET_LA 20 +#define TEGRA264_RESET_NVCSI 21 +#define TEGRA264_RESET_EQOS_MAC 22 +#define TEGRA264_RESET_PWM10 23 +#define TEGRA264_RESET_PWM2 24 +#define TEGRA264_RESET_PWM3 25 +#define TEGRA264_RESET_PWM4 26 +#define TEGRA264_RESET_PWM5 27 +#define TEGRA264_RESET_PWM9 28 +#define TEGRA264_RESET_QSPI0 29 +#define TEGRA264_RESET_HDA 30 +#define TEGRA264_RESET_HDACODEC 31 +#define TEGRA264_RESET_I2C0 32 +#define TEGRA264_RESET_I2C10 33 +#define TEGRA264_RESET_SDMMC1 34 +#define TEGRA264_RESET_MIPI_CAL 35 +#define TEGRA264_RESET_SPI1 36 +#define TEGRA264_RESET_SPI2 37 +#define TEGRA264_RESET_SPI3 38 +#define TEGRA264_RESET_SPI4 39 +#define TEGRA264_RESET_SPI5 40 +#define TEGRA264_RESET_SPI7 41 +#define TEGRA264_RESET_SPI8 42 +#define TEGRA264_RESET_SPI9 43 +#define TEGRA264_RESET_TACH0 44 +#define TEGRA264_RESET_TSEC 45 +#define TEGRA264_RESET_VI 46 +#define TEGRA264_RESET_VI1 47 +#define TEGRA264_RESET_PVA0_ALL 48 +#define TEGRA264_RESET_VIC 49 +#define TEGRA264_RESET_MPHY_CLK_CTL 50 +#define TEGRA264_RESET_MPHY_L0_RX 51 +#define TEGRA264_RESET_MPHY_L0_TX 52 +#define TEGRA264_RESET_MPHY_L1_RX 53 +#define TEGRA264_RESET_MPHY_L1_TX 54 +#define TEGRA264_RESET_ISP1 55 +#define TEGRA264_RESET_I2C11 56 +#define TEGRA264_RESET_I2C12 57 +#define TEGRA264_RESET_I2C14 58 +#define TEGRA264_RESET_I2C15 59 +#define TEGRA264_RESET_I2C16 60 +#define TEGRA264_RESET_EQOS_MACSEC 61 +#define TEGRA264_RESET_MGBE0_PCS 62 +#define TEGRA264_RESET_MGBE0_MAC 63 +#define TEGRA264_RESET_MGBE0_MACSEC 64 +#define TEGRA264_RESET_MGBE1_PCS 65 +#define TEGRA264_RESET_MGBE1_MAC 66 +#define TEGRA264_RESET_MGBE1_MACSEC 67 +#define TEGRA264_RESET_MGBE2_PCS 68 +#define TEGRA264_RESET_MGBE2_MAC 69 +#define TEGRA264_RESET_MGBE2_MACSEC 70 +#define TEGRA264_RESET_MGBE3_PCS 71 +#define TEGRA264_RESET_MGBE3_MAC 72 +#define TEGRA264_RESET_MGBE3_MACSEC 73 +#define TEGRA264_RESET_ADSP_CORE0 74 +#define TEGRA264_RESET_ADSP_CORE1 75 +#define TEGRA264_RESET_APE 76 +#define TEGRA264_RESET_XUSB1_PADCTL 77 +#define TEGRA264_RESET_AON_CPU_ALL 78 +#define TEGRA264_RESET_AON_HSP 79 +#define TEGRA264_RESET_UART4 80 +#define TEGRA264_RESET_UART5 81 +#define TEGRA264_RESET_UART9 82 +#define TEGRA264_RESET_UART10 83 +#define TEGRA264_RESET_UART8 84 + +#endif /* DT_BINDINGS_RESET_NVIDIA_TEGRA264_H */ diff --git a/include/dt-bindings/reset/qcom,ipq9574-nsscc.h b/include/dt-bindings/reset/qcom,ipq9574-nsscc.h new file mode 100644 index 000000000000..7f152e98b99c --- /dev/null +++ b/include/dt-bindings/reset/qcom,ipq9574-nsscc.h @@ -0,0 +1,134 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) 2023, 2025 The Linux Foundation. All rights reserved. + */ + +#ifndef _DT_BINDINGS_RESET_IPQ_NSSCC_9574_H +#define _DT_BINDINGS_RESET_IPQ_NSSCC_9574_H + +#define EDMA_HW_RESET 0 +#define NSS_CC_CE_BCR 1 +#define NSS_CC_CLC_BCR 2 +#define NSS_CC_EIP197_BCR 3 +#define NSS_CC_HAQ_BCR 4 +#define NSS_CC_IMEM_BCR 5 +#define NSS_CC_MAC_BCR 6 +#define NSS_CC_PPE_BCR 7 +#define NSS_CC_UBI_BCR 8 +#define NSS_CC_UNIPHY_BCR 9 +#define UBI3_CLKRST_CLAMP_ENABLE 10 +#define UBI3_CORE_CLAMP_ENABLE 11 +#define UBI2_CLKRST_CLAMP_ENABLE 12 +#define UBI2_CORE_CLAMP_ENABLE 13 +#define UBI1_CLKRST_CLAMP_ENABLE 14 +#define UBI1_CORE_CLAMP_ENABLE 15 +#define UBI0_CLKRST_CLAMP_ENABLE 16 +#define UBI0_CORE_CLAMP_ENABLE 17 +#define NSSNOC_NSS_CSR_ARES 18 +#define NSS_CSR_ARES 19 +#define PPE_BTQ_ARES 20 +#define PPE_IPE_ARES 21 +#define PPE_ARES 22 +#define PPE_CFG_ARES 23 +#define PPE_EDMA_ARES 24 +#define PPE_EDMA_CFG_ARES 25 +#define CRY_PPE_ARES 26 +#define NSSNOC_PPE_ARES 27 +#define NSSNOC_PPE_CFG_ARES 28 +#define PORT1_MAC_ARES 29 +#define PORT2_MAC_ARES 30 +#define PORT3_MAC_ARES 31 +#define PORT4_MAC_ARES 32 +#define PORT5_MAC_ARES 33 +#define PORT6_MAC_ARES 34 +#define XGMAC0_PTP_REF_ARES 35 +#define XGMAC1_PTP_REF_ARES 36 +#define XGMAC2_PTP_REF_ARES 37 +#define XGMAC3_PTP_REF_ARES 38 +#define XGMAC4_PTP_REF_ARES 39 +#define XGMAC5_PTP_REF_ARES 40 +#define HAQ_AHB_ARES 41 +#define HAQ_AXI_ARES 42 +#define NSSNOC_HAQ_AHB_ARES 43 +#define NSSNOC_HAQ_AXI_ARES 44 +#define CE_APB_ARES 45 +#define CE_AXI_ARES 46 +#define NSSNOC_CE_APB_ARES 47 +#define NSSNOC_CE_AXI_ARES 48 +#define CRYPTO_ARES 49 +#define NSSNOC_CRYPTO_ARES 50 +#define NSSNOC_NC_AXI0_1_ARES 51 +#define UBI0_CORE_ARES 52 +#define UBI1_CORE_ARES 53 +#define UBI2_CORE_ARES 54 +#define UBI3_CORE_ARES 55 +#define NC_AXI0_ARES 56 +#define UTCM0_ARES 57 +#define NC_AXI1_ARES 58 +#define UTCM1_ARES 59 +#define NC_AXI2_ARES 60 +#define UTCM2_ARES 61 +#define NC_AXI3_ARES 62 +#define UTCM3_ARES 63 +#define NSSNOC_NC_AXI0_ARES 64 +#define AHB0_ARES 65 +#define INTR0_AHB_ARES 66 +#define AHB1_ARES 67 +#define INTR1_AHB_ARES 68 +#define AHB2_ARES 69 +#define INTR2_AHB_ARES 70 +#define AHB3_ARES 71 +#define INTR3_AHB_ARES 72 +#define NSSNOC_AHB0_ARES 73 +#define NSSNOC_INT0_AHB_ARES 74 +#define AXI0_ARES 75 +#define AXI1_ARES 76 +#define AXI2_ARES 77 +#define AXI3_ARES 78 +#define NSSNOC_AXI0_ARES 79 +#define IMEM_QSB_ARES 80 +#define NSSNOC_IMEM_QSB_ARES 81 +#define IMEM_AHB_ARES 82 +#define NSSNOC_IMEM_AHB_ARES 83 +#define UNIPHY_PORT1_RX_ARES 84 +#define UNIPHY_PORT1_TX_ARES 85 +#define UNIPHY_PORT2_RX_ARES 86 +#define UNIPHY_PORT2_TX_ARES 87 +#define UNIPHY_PORT3_RX_ARES 88 +#define UNIPHY_PORT3_TX_ARES 89 +#define UNIPHY_PORT4_RX_ARES 90 +#define UNIPHY_PORT4_TX_ARES 91 +#define UNIPHY_PORT5_RX_ARES 92 +#define UNIPHY_PORT5_TX_ARES 93 +#define UNIPHY_PORT6_RX_ARES 94 +#define UNIPHY_PORT6_TX_ARES 95 +#define PORT1_RX_ARES 96 +#define PORT1_TX_ARES 97 +#define PORT2_RX_ARES 98 +#define PORT2_TX_ARES 99 +#define PORT3_RX_ARES 100 +#define PORT3_TX_ARES 101 +#define PORT4_RX_ARES 102 +#define PORT4_TX_ARES 103 +#define PORT5_RX_ARES 104 +#define PORT5_TX_ARES 105 +#define PORT6_RX_ARES 106 +#define PORT6_TX_ARES 107 +#define PPE_FULL_RESET 108 +#define UNIPHY0_SOFT_RESET 109 +#define UNIPHY1_SOFT_RESET 110 +#define UNIPHY2_SOFT_RESET 111 +#define UNIPHY_PORT1_ARES 112 +#define UNIPHY_PORT2_ARES 113 +#define UNIPHY_PORT3_ARES 114 +#define UNIPHY_PORT4_ARES 115 +#define UNIPHY_PORT5_ARES 116 +#define UNIPHY_PORT6_ARES 117 +#define NSSPORT1_RESET 118 +#define NSSPORT2_RESET 119 +#define NSSPORT3_RESET 120 +#define NSSPORT4_RESET 121 +#define NSSPORT5_RESET 122 +#define NSSPORT6_RESET 123 + +#endif diff --git a/include/dt-bindings/reset/rockchip,rk3528-cru.h b/include/dt-bindings/reset/rockchip,rk3528-cru.h new file mode 100644 index 000000000000..6b024c5f2e1c --- /dev/null +++ b/include/dt-bindings/reset/rockchip,rk3528-cru.h @@ -0,0 +1,241 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */ +/* + * Copyright (c) 2022 Rockchip Electronics Co. Ltd. + * Copyright (c) 2024 Yao Zi <ziyao@disroot.org> + * Author: Joseph Chen <chenjh@rock-chips.com> + */ + +#ifndef _DT_BINDINGS_RESET_ROCKCHIP_RK3528_H +#define _DT_BINDINGS_RESET_ROCKCHIP_RK3528_H + +#define SRST_CORE0_PO 0 +#define SRST_CORE1_PO 1 +#define SRST_CORE2_PO 2 +#define SRST_CORE3_PO 3 +#define SRST_CORE0 4 +#define SRST_CORE1 5 +#define SRST_CORE2 6 +#define SRST_CORE3 7 +#define SRST_NL2 8 +#define SRST_CORE_BIU 9 +#define SRST_CORE_CRYPTO 10 +#define SRST_P_DBG 11 +#define SRST_POT_DBG 12 +#define SRST_NT_DBG 13 +#define SRST_P_CORE_GRF 14 +#define SRST_P_DAPLITE_BIU 15 +#define SRST_P_CPU_BIU 16 +#define SRST_REF_PVTPLL_CORE 17 +#define SRST_A_BUS_VOPGL_BIU 18 +#define SRST_A_BUS_H_BIU 19 +#define SRST_A_SYSMEM_BIU 20 +#define SRST_A_BUS_BIU 21 +#define SRST_H_BUS_BIU 22 +#define SRST_P_BUS_BIU 23 +#define SRST_P_DFT2APB 24 +#define SRST_P_BUS_GRF 25 +#define SRST_A_BUS_M_BIU 26 +#define SRST_A_GIC 27 +#define SRST_A_SPINLOCK 28 +#define SRST_A_DMAC 29 +#define SRST_P_TIMER 30 +#define SRST_TIMER0 31 +#define SRST_TIMER1 32 +#define SRST_TIMER2 33 +#define SRST_TIMER3 34 +#define SRST_TIMER4 35 +#define SRST_TIMER5 36 +#define SRST_P_JDBCK_DAP 37 +#define SRST_JDBCK_DAP 38 +#define SRST_P_WDT_NS 39 +#define SRST_T_WDT_NS 40 +#define SRST_H_TRNG_NS 41 +#define SRST_P_UART0 42 +#define SRST_S_UART0 43 +#define SRST_PKA_CRYPTO 44 +#define SRST_A_CRYPTO 45 +#define SRST_H_CRYPTO 46 +#define SRST_P_DMA2DDR 47 +#define SRST_A_DMA2DDR 48 +#define SRST_P_PWM0 49 +#define SRST_PWM0 50 +#define SRST_P_PWM1 51 +#define SRST_PWM1 52 +#define SRST_P_SCR 53 +#define SRST_A_DCF 54 +#define SRST_P_INTMUX 55 +#define SRST_A_VPU_BIU 56 +#define SRST_H_VPU_BIU 57 +#define SRST_P_VPU_BIU 58 +#define SRST_A_VPU 59 +#define SRST_H_VPU 60 +#define SRST_P_CRU_PCIE 61 +#define SRST_P_VPU_GRF 62 +#define SRST_H_SFC 63 +#define SRST_S_SFC 64 +#define SRST_C_EMMC 65 +#define SRST_H_EMMC 66 +#define SRST_A_EMMC 67 +#define SRST_B_EMMC 68 +#define SRST_T_EMMC 69 +#define SRST_P_GPIO1 70 +#define SRST_DB_GPIO1 71 +#define SRST_A_VPU_L_BIU 72 +#define SRST_P_VPU_IOC 73 +#define SRST_H_SAI_I2S0 74 +#define SRST_M_SAI_I2S0 75 +#define SRST_H_SAI_I2S2 76 +#define SRST_M_SAI_I2S2 77 +#define SRST_P_ACODEC 78 +#define SRST_P_GPIO3 79 +#define SRST_DB_GPIO3 80 +#define SRST_P_SPI1 81 +#define SRST_SPI1 82 +#define SRST_P_UART2 83 +#define SRST_S_UART2 84 +#define SRST_P_UART5 85 +#define SRST_S_UART5 86 +#define SRST_P_UART6 87 +#define SRST_S_UART6 88 +#define SRST_P_UART7 89 +#define SRST_S_UART7 90 +#define SRST_P_I2C3 91 +#define SRST_I2C3 92 +#define SRST_P_I2C5 93 +#define SRST_I2C5 94 +#define SRST_P_I2C6 95 +#define SRST_I2C6 96 +#define SRST_A_MAC 97 +#define SRST_P_PCIE 98 +#define SRST_PCIE_PIPE_PHY 99 +#define SRST_PCIE_POWER_UP 100 +#define SRST_P_PCIE_PHY 101 +#define SRST_P_PIPE_GRF 102 +#define SRST_H_SDIO0 103 +#define SRST_H_SDIO1 104 +#define SRST_TS_0 105 +#define SRST_TS_1 106 +#define SRST_P_CAN2 107 +#define SRST_CAN2 108 +#define SRST_P_CAN3 109 +#define SRST_CAN3 110 +#define SRST_P_SARADC 111 +#define SRST_SARADC 112 +#define SRST_SARADC_PHY 113 +#define SRST_P_TSADC 114 +#define SRST_TSADC 115 +#define SRST_A_USB3OTG 116 +#define SRST_A_GPU_BIU 117 +#define SRST_P_GPU_BIU 118 +#define SRST_A_GPU 119 +#define SRST_REF_PVTPLL_GPU 120 +#define SRST_H_RKVENC_BIU 121 +#define SRST_A_RKVENC_BIU 122 +#define SRST_P_RKVENC_BIU 123 +#define SRST_H_RKVENC 124 +#define SRST_A_RKVENC 125 +#define SRST_CORE_RKVENC 126 +#define SRST_H_SAI_I2S1 127 +#define SRST_M_SAI_I2S1 128 +#define SRST_P_I2C1 129 +#define SRST_I2C1 130 +#define SRST_P_I2C0 131 +#define SRST_I2C0 132 +#define SRST_P_SPI0 133 +#define SRST_SPI0 134 +#define SRST_P_GPIO4 135 +#define SRST_DB_GPIO4 136 +#define SRST_P_RKVENC_IOC 137 +#define SRST_H_SPDIF 138 +#define SRST_M_SPDIF 139 +#define SRST_H_PDM 140 +#define SRST_M_PDM 141 +#define SRST_P_UART1 142 +#define SRST_S_UART1 143 +#define SRST_P_UART3 144 +#define SRST_S_UART3 145 +#define SRST_P_RKVENC_GRF 146 +#define SRST_P_CAN0 147 +#define SRST_CAN0 148 +#define SRST_P_CAN1 149 +#define SRST_CAN1 150 +#define SRST_A_VO_BIU 151 +#define SRST_H_VO_BIU 152 +#define SRST_P_VO_BIU 153 +#define SRST_H_RGA2E 154 +#define SRST_A_RGA2E 155 +#define SRST_CORE_RGA2E 156 +#define SRST_H_VDPP 157 +#define SRST_A_VDPP 158 +#define SRST_CORE_VDPP 159 +#define SRST_P_VO_GRF 160 +#define SRST_P_CRU 161 +#define SRST_A_VOP_BIU 162 +#define SRST_H_VOP 163 +#define SRST_D_VOP0 164 +#define SRST_D_VOP1 165 +#define SRST_A_VOP 166 +#define SRST_P_HDMI 167 +#define SRST_HDMI 168 +#define SRST_P_HDMIPHY 169 +#define SRST_H_HDCP_KEY 170 +#define SRST_A_HDCP 171 +#define SRST_H_HDCP 172 +#define SRST_P_HDCP 173 +#define SRST_H_CVBS 174 +#define SRST_D_CVBS_VOP 175 +#define SRST_D_4X_CVBS_VOP 176 +#define SRST_A_JPEG_DECODER 177 +#define SRST_H_JPEG_DECODER 178 +#define SRST_A_VO_L_BIU 179 +#define SRST_A_MAC_VO 180 +#define SRST_A_JPEG_BIU 181 +#define SRST_H_SAI_I2S3 182 +#define SRST_M_SAI_I2S3 183 +#define SRST_MACPHY 184 +#define SRST_P_VCDCPHY 185 +#define SRST_P_GPIO2 186 +#define SRST_DB_GPIO2 187 +#define SRST_P_VO_IOC 188 +#define SRST_H_SDMMC0 189 +#define SRST_P_OTPC_NS 190 +#define SRST_SBPI_OTPC_NS 191 +#define SRST_USER_OTPC_NS 192 +#define SRST_HDMIHDP0 193 +#define SRST_H_USBHOST 194 +#define SRST_H_USBHOST_ARB 195 +#define SRST_HOST_UTMI 196 +#define SRST_P_UART4 197 +#define SRST_S_UART4 198 +#define SRST_P_I2C4 199 +#define SRST_I2C4 200 +#define SRST_P_I2C7 201 +#define SRST_I2C7 202 +#define SRST_P_USBPHY 203 +#define SRST_USBPHY_POR 204 +#define SRST_USBPHY_OTG 205 +#define SRST_USBPHY_HOST 206 +#define SRST_P_DDRPHY_CRU 207 +#define SRST_H_RKVDEC_BIU 208 +#define SRST_A_RKVDEC_BIU 209 +#define SRST_A_RKVDEC 210 +#define SRST_H_RKVDEC 211 +#define SRST_HEVC_CA_RKVDEC 212 +#define SRST_REF_PVTPLL_RKVDEC 213 +#define SRST_P_DDR_BIU 214 +#define SRST_P_DDRC 215 +#define SRST_P_DDRMON 216 +#define SRST_TIMER_DDRMON 217 +#define SRST_P_MSCH_BIU 218 +#define SRST_P_DDR_GRF 219 +#define SRST_P_DDR_HWLP 220 +#define SRST_P_DDRPHY 221 +#define SRST_MSCH_BIU 222 +#define SRST_A_DDR_UPCTL 223 +#define SRST_DDR_UPCTL 224 +#define SRST_DDRMON 225 +#define SRST_A_DDR_SCRAMBLE 226 +#define SRST_A_SPLIT 227 +#define SRST_DDR_PHY 228 + +#endif // _DT_BINDINGS_RESET_ROCKCHIP_RK3528_H diff --git a/include/dt-bindings/reset/rockchip,rk3562-cru.h b/include/dt-bindings/reset/rockchip,rk3562-cru.h new file mode 100644 index 000000000000..8df95113056e --- /dev/null +++ b/include/dt-bindings/reset/rockchip,rk3562-cru.h @@ -0,0 +1,358 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) 2024-2025 Rockchip Electronics Co. Ltd. + * + * Author: Elaine Zhang <zhangqing@rock-chips.com> + */ + +#ifndef _DT_BINDINGS_RESET_ROCKCHIP_RK3562_H +#define _DT_BINDINGS_RESET_ROCKCHIP_RK3562_H + +/********Name=SOFTRST_CON01,Offset=0x404********/ +#define SRST_A_TOP_BIU 0 +#define SRST_A_TOP_VIO_BIU 1 +#define SRST_REF_PVTPLL_LOGIC 2 +/********Name=SOFTRST_CON03,Offset=0x40C********/ +#define SRST_NCOREPORESET0 3 +#define SRST_NCOREPORESET1 4 +#define SRST_NCOREPORESET2 5 +#define SRST_NCOREPORESET3 6 +#define SRST_NCORESET0 7 +#define SRST_NCORESET1 8 +#define SRST_NCORESET2 9 +#define SRST_NCORESET3 10 +#define SRST_NL2RESET 11 +/********Name=SOFTRST_CON04,Offset=0x410********/ +#define SRST_DAP 12 +#define SRST_P_DBG_DAPLITE 13 +#define SRST_REF_PVTPLL_CORE 14 +/********Name=SOFTRST_CON05,Offset=0x414********/ +#define SRST_A_CORE_BIU 15 +#define SRST_P_CORE_BIU 16 +#define SRST_H_CORE_BIU 17 +/********Name=SOFTRST_CON06,Offset=0x418********/ +#define SRST_A_NPU_BIU 18 +#define SRST_H_NPU_BIU 19 +#define SRST_A_RKNN 20 +#define SRST_H_RKNN 21 +#define SRST_REF_PVTPLL_NPU 22 +/********Name=SOFTRST_CON08,Offset=0x420********/ +#define SRST_A_GPU_BIU 23 +#define SRST_GPU 24 +#define SRST_REF_PVTPLL_GPU 25 +#define SRST_GPU_BRG_BIU 26 +/********Name=SOFTRST_CON09,Offset=0x424********/ +#define SRST_RKVENC_CORE 27 +#define SRST_A_VEPU_BIU 28 +#define SRST_H_VEPU_BIU 29 +#define SRST_A_RKVENC 30 +#define SRST_H_RKVENC 31 +/********Name=SOFTRST_CON10,Offset=0x428********/ +#define SRST_RKVDEC_HEVC_CA 32 +#define SRST_A_VDPU_BIU 33 +#define SRST_H_VDPU_BIU 34 +#define SRST_A_RKVDEC 35 +#define SRST_H_RKVDEC 36 +/********Name=SOFTRST_CON11,Offset=0x42C********/ +#define SRST_A_VI_BIU 37 +#define SRST_H_VI_BIU 38 +#define SRST_P_VI_BIU 39 +#define SRST_ISP 40 +#define SRST_A_VICAP 41 +#define SRST_H_VICAP 42 +#define SRST_D_VICAP 43 +#define SRST_I0_VICAP 44 +#define SRST_I1_VICAP 45 +#define SRST_I2_VICAP 46 +#define SRST_I3_VICAP 47 +/********Name=SOFTRST_CON12,Offset=0x430********/ +#define SRST_P_CSIHOST0 48 +#define SRST_P_CSIHOST1 49 +#define SRST_P_CSIHOST2 50 +#define SRST_P_CSIHOST3 51 +#define SRST_P_CSIPHY0 52 +#define SRST_P_CSIPHY1 53 +/********Name=SOFTRST_CON13,Offset=0x434********/ +#define SRST_A_VO_BIU 54 +#define SRST_H_VO_BIU 55 +#define SRST_A_VOP 56 +#define SRST_H_VOP 57 +#define SRST_D_VOP 58 +#define SRST_D_VOP1 59 +/********Name=SOFTRST_CON14,Offset=0x438********/ +#define SRST_A_RGA_BIU 60 +#define SRST_H_RGA_BIU 61 +#define SRST_A_RGA 62 +#define SRST_H_RGA 63 +#define SRST_RGA_CORE 64 +#define SRST_A_JDEC 65 +#define SRST_H_JDEC 66 +/********Name=SOFTRST_CON15,Offset=0x43C********/ +#define SRST_B_EBK_BIU 67 +#define SRST_P_EBK_BIU 68 +#define SRST_AHB2AXI_EBC 69 +#define SRST_H_EBC 70 +#define SRST_D_EBC 71 +#define SRST_H_EINK 72 +#define SRST_P_EINK 73 +/********Name=SOFTRST_CON16,Offset=0x440********/ +#define SRST_P_PHP_BIU 74 +#define SRST_A_PHP_BIU 75 +#define SRST_P_PCIE20 76 +#define SRST_PCIE20_POWERUP 77 +#define SRST_USB3OTG 78 +/********Name=SOFTRST_CON17,Offset=0x444********/ +#define SRST_PIPEPHY 79 +/********Name=SOFTRST_CON18,Offset=0x448********/ +#define SRST_A_BUS_BIU 80 +#define SRST_H_BUS_BIU 81 +#define SRST_P_BUS_BIU 82 +/********Name=SOFTRST_CON19,Offset=0x44C********/ +#define SRST_P_I2C1 83 +#define SRST_P_I2C2 84 +#define SRST_P_I2C3 85 +#define SRST_P_I2C4 86 +#define SRST_P_I2C5 87 +#define SRST_I2C1 88 +#define SRST_I2C2 89 +#define SRST_I2C3 90 +#define SRST_I2C4 91 +#define SRST_I2C5 92 +/********Name=SOFTRST_CON20,Offset=0x450********/ +#define SRST_BUS_GPIO3 93 +#define SRST_BUS_GPIO4 94 +/********Name=SOFTRST_CON21,Offset=0x454********/ +#define SRST_P_TIMER 95 +#define SRST_TIMER0 96 +#define SRST_TIMER1 97 +#define SRST_TIMER2 98 +#define SRST_TIMER3 99 +#define SRST_TIMER4 100 +#define SRST_TIMER5 101 +#define SRST_P_STIMER 102 +#define SRST_STIMER0 103 +#define SRST_STIMER1 104 +/********Name=SOFTRST_CON22,Offset=0x458********/ +#define SRST_P_WDTNS 105 +#define SRST_WDTNS 106 +#define SRST_P_GRF 107 +#define SRST_P_SGRF 108 +#define SRST_P_MAILBOX 109 +#define SRST_P_INTC 110 +#define SRST_A_BUS_GIC400 111 +#define SRST_A_BUS_GIC400_DEBUG 112 +/********Name=SOFTRST_CON23,Offset=0x45C********/ +#define SRST_A_BUS_SPINLOCK 113 +#define SRST_A_DCF 114 +#define SRST_P_DCF 115 +#define SRST_F_BUS_CM0_CORE 116 +#define SRST_T_BUS_CM0_JTAG 117 +#define SRST_H_ICACHE 118 +#define SRST_H_DCACHE 119 +/********Name=SOFTRST_CON24,Offset=0x460********/ +#define SRST_P_TSADC 120 +#define SRST_TSADC 121 +#define SRST_TSADCPHY 122 +#define SRST_P_DFT2APB 123 +/********Name=SOFTRST_CON25,Offset=0x464********/ +#define SRST_A_GMAC 124 +#define SRST_P_APB2ASB_VCCIO156 125 +#define SRST_P_DSIPHY 126 +#define SRST_P_DSITX 127 +#define SRST_P_CPU_EMA_DET 128 +#define SRST_P_HASH 129 +#define SRST_P_TOPCRU 130 +/********Name=SOFTRST_CON26,Offset=0x468********/ +#define SRST_P_ASB2APB_VCCIO156 131 +#define SRST_P_IOC_VCCIO156 132 +#define SRST_P_GPIO3_VCCIO156 133 +#define SRST_P_GPIO4_VCCIO156 134 +#define SRST_P_SARADC_VCCIO156 135 +#define SRST_SARADC_VCCIO156 136 +#define SRST_SARADC_VCCIO156_PHY 137 +/********Name=SOFTRST_CON27,Offset=0x46c********/ +#define SRST_A_MAC100 138 + +/********Name=PMU0SOFTRST_CON00,Offset=0x10200********/ +#define SRST_P_PMU0_CRU 139 +#define SRST_P_PMU0_PMU 140 +#define SRST_PMU0_PMU 141 +#define SRST_P_PMU0_HP_TIMER 142 +#define SRST_PMU0_HP_TIMER 143 +#define SRST_PMU0_32K_HP_TIMER 144 +#define SRST_P_PMU0_PVTM 145 +#define SRST_PMU0_PVTM 146 +#define SRST_P_IOC_PMUIO 147 +#define SRST_P_PMU0_GPIO0 148 +#define SRST_PMU0_GPIO0 149 +#define SRST_P_PMU0_GRF 150 +#define SRST_P_PMU0_SGRF 151 +/********Name=PMU0SOFTRST_CON01,Offset=0x10204********/ +#define SRST_DDR_FAIL_SAFE 152 +#define SRST_P_PMU0_SCRKEYGEN 153 +/********Name=PMU0SOFTRST_CON02,Offset=0x10208********/ +#define SRST_P_PMU0_I2C0 154 +#define SRST_PMU0_I2C0 155 + +/********Name=PMU1SOFTRST_CON00,Offset=0x18200********/ +#define SRST_P_PMU1_CRU 156 +#define SRST_H_PMU1_MEM 157 +#define SRST_H_PMU1_BIU 158 +#define SRST_P_PMU1_BIU 159 +#define SRST_P_PMU1_UART0 160 +#define SRST_S_PMU1_UART0 161 +/********Name=PMU1SOFTRST_CON01,Offset=0x18204********/ +#define SRST_P_PMU1_SPI0 162 +#define SRST_PMU1_SPI0 163 +#define SRST_P_PMU1_PWM0 164 +#define SRST_PMU1_PWM0 165 +/********Name=PMU1SOFTRST_CON02,Offset=0x18208********/ +#define SRST_F_PMU1_CM0_CORE 166 +#define SRST_T_PMU1_CM0_JTAG 167 +#define SRST_P_PMU1_WDTNS 168 +#define SRST_PMU1_WDTNS 169 +#define SRST_PMU1_MAILBOX 170 + +/********Name=DDRSOFTRST_CON00,Offset=0x20200********/ +#define SRST_MSCH_BRG_BIU 171 +#define SRST_P_MSCH_BIU 172 +#define SRST_P_DDR_HWLP 173 +#define SRST_P_DDR_PHY 290 +#define SRST_P_DDR_DFICTL 174 +#define SRST_P_DDR_DMA2DDR 175 +/********Name=DDRSOFTRST_CON01,Offset=0x20204********/ +#define SRST_P_DDR_MON 176 +#define SRST_TM_DDR_MON 177 +#define SRST_P_DDR_GRF 178 +#define SRST_P_DDR_CRU 179 +#define SRST_P_SUBDDR_CRU 180 + +/********Name=SUBDDRSOFTRST_CON00,Offset=0x28200********/ +#define SRST_MSCH_BIU 181 +#define SRST_DDR_PHY 182 +#define SRST_DDR_DFICTL 183 +#define SRST_DDR_SCRAMBLE 184 +#define SRST_DDR_MON 185 +#define SRST_A_DDR_SPLIT 186 +#define SRST_DDR_DMA2DDR 187 + +/********Name=PERISOFTRST_CON01,Offset=0x30404********/ +#define SRST_A_PERI_BIU 188 +#define SRST_H_PERI_BIU 189 +#define SRST_P_PERI_BIU 190 +#define SRST_P_PERICRU 191 +/********Name=PERISOFTRST_CON02,Offset=0x30408********/ +#define SRST_H_SAI0_8CH 192 +#define SRST_M_SAI0_8CH 193 +#define SRST_H_SAI1_8CH 194 +#define SRST_M_SAI1_8CH 195 +#define SRST_H_SAI2_2CH 196 +#define SRST_M_SAI2_2CH 197 +/********Name=PERISOFTRST_CON03,Offset=0x3040C********/ +#define SRST_H_DSM 198 +#define SRST_DSM 199 +#define SRST_H_PDM 200 +#define SRST_M_PDM 201 +#define SRST_H_SPDIF 202 +#define SRST_M_SPDIF 203 +/********Name=PERISOFTRST_CON04,Offset=0x30410********/ +#define SRST_H_SDMMC0 204 +#define SRST_H_SDMMC1 205 +#define SRST_H_EMMC 206 +#define SRST_A_EMMC 207 +#define SRST_C_EMMC 208 +#define SRST_B_EMMC 209 +#define SRST_T_EMMC 210 +#define SRST_S_SFC 211 +#define SRST_H_SFC 212 +/********Name=PERISOFTRST_CON05,Offset=0x30414********/ +#define SRST_H_USB2HOST 213 +#define SRST_H_USB2HOST_ARB 214 +#define SRST_USB2HOST_UTMI 215 +/********Name=PERISOFTRST_CON06,Offset=0x30418********/ +#define SRST_P_SPI1 216 +#define SRST_SPI1 217 +#define SRST_P_SPI2 218 +#define SRST_SPI2 219 +/********Name=PERISOFTRST_CON07,Offset=0x3041C********/ +#define SRST_P_UART1 220 +#define SRST_P_UART2 221 +#define SRST_P_UART3 222 +#define SRST_P_UART4 223 +#define SRST_P_UART5 224 +#define SRST_P_UART6 225 +#define SRST_P_UART7 226 +#define SRST_P_UART8 227 +#define SRST_P_UART9 228 +#define SRST_S_UART1 229 +#define SRST_S_UART2 230 +/********Name=PERISOFTRST_CON08,Offset=0x30420********/ +#define SRST_S_UART3 231 +#define SRST_S_UART4 232 +#define SRST_S_UART5 233 +#define SRST_S_UART6 234 +#define SRST_S_UART7 235 +/********Name=PERISOFTRST_CON09,Offset=0x30424********/ +#define SRST_S_UART8 236 +#define SRST_S_UART9 237 +/********Name=PERISOFTRST_CON10,Offset=0x30428********/ +#define SRST_P_PWM1_PERI 238 +#define SRST_PWM1_PERI 239 +#define SRST_P_PWM2_PERI 240 +#define SRST_PWM2_PERI 241 +#define SRST_P_PWM3_PERI 242 +#define SRST_PWM3_PERI 243 +/********Name=PERISOFTRST_CON11,Offset=0x3042C********/ +#define SRST_P_CAN0 244 +#define SRST_CAN0 245 +#define SRST_P_CAN1 246 +#define SRST_CAN1 247 +/********Name=PERISOFTRST_CON12,Offset=0x30430********/ +#define SRST_A_CRYPTO 248 +#define SRST_H_CRYPTO 249 +#define SRST_P_CRYPTO 250 +#define SRST_CORE_CRYPTO 251 +#define SRST_PKA_CRYPTO 252 +#define SRST_H_KLAD 253 +#define SRST_P_KEY_READER 254 +#define SRST_H_RK_RNG_NS 255 +#define SRST_H_RK_RNG_S 256 +#define SRST_H_TRNG_NS 257 +#define SRST_H_TRNG_S 258 +#define SRST_H_CRYPTO_S 259 +/********Name=PERISOFTRST_CON13,Offset=0x30434********/ +#define SRST_P_PERI_WDT 260 +#define SRST_T_PERI_WDT 261 +#define SRST_A_SYSMEM 262 +#define SRST_H_BOOTROM 263 +#define SRST_P_PERI_GRF 264 +#define SRST_A_DMAC 265 +#define SRST_A_RKDMAC 267 +/********Name=PERISOFTRST_CON14,Offset=0x30438********/ +#define SRST_P_OTPC_NS 268 +#define SRST_SBPI_OTPC_NS 269 +#define SRST_USER_OTPC_NS 270 +#define SRST_P_OTPC_S 271 +#define SRST_SBPI_OTPC_S 272 +#define SRST_USER_OTPC_S 273 +#define SRST_OTPC_ARB 274 +#define SRST_P_OTPPHY 275 +#define SRST_OTP_NPOR 276 +/********Name=PERISOFTRST_CON15,Offset=0x3043C********/ +#define SRST_P_USB2PHY 277 +#define SRST_USB2PHY_POR 278 +#define SRST_USB2PHY_OTG 279 +#define SRST_USB2PHY_HOST 280 +#define SRST_P_PIPEPHY 281 +/********Name=PERISOFTRST_CON16,Offset=0x30440********/ +#define SRST_P_SARADC 282 +#define SRST_SARADC 283 +#define SRST_SARADC_PHY 284 +#define SRST_P_IOC_VCCIO234 285 +/********Name=PERISOFTRST_CON17,Offset=0x30444********/ +#define SRST_P_PERI_GPIO1 286 +#define SRST_P_PERI_GPIO2 287 +#define SRST_PERI_GPIO1 288 +#define SRST_PERI_GPIO2 289 + +#endif diff --git a/include/dt-bindings/reset/rockchip,rk3588-cru.h b/include/dt-bindings/reset/rockchip,rk3588-cru.h index e2fe4bd5f7f0..878beae6dc3b 100644 --- a/include/dt-bindings/reset/rockchip,rk3588-cru.h +++ b/include/dt-bindings/reset/rockchip,rk3588-cru.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: (GPL-2.0 OR MIT) */ /* - * Copyright (c) 2021 Rockchip Electronics Co. Ltd. + * Copyright (c) 2021, 2024 Rockchip Electronics Co. Ltd. * Copyright (c) 2022 Collabora Ltd. * * Author: Elaine Zhang <zhangqing@rock-chips.com> @@ -753,4 +753,43 @@ #define SRST_A_HDMIRX_BIU 660 +/* SCMI Secure Resets */ + +/* Name=SECURE_SOFTRST_CON00,Offset=0xA00 */ +#define SCMI_SRST_A_SECURE_NS_BIU 10 +#define SCMI_SRST_H_SECURE_NS_BIU 11 +#define SCMI_SRST_A_SECURE_S_BIU 12 +#define SCMI_SRST_H_SECURE_S_BIU 13 +#define SCMI_SRST_P_SECURE_S_BIU 14 +#define SCMI_SRST_CRYPTO_CORE 15 +/* Name=SECURE_SOFTRST_CON01,Offset=0xA04 */ +#define SCMI_SRST_CRYPTO_PKA 16 +#define SCMI_SRST_CRYPTO_RNG 17 +#define SCMI_SRST_A_CRYPTO 18 +#define SCMI_SRST_H_CRYPTO 19 +#define SCMI_SRST_KEYLADDER_CORE 25 +#define SCMI_SRST_KEYLADDER_RNG 26 +#define SCMI_SRST_A_KEYLADDER 27 +#define SCMI_SRST_H_KEYLADDER 28 +#define SCMI_SRST_P_OTPC_S 29 +#define SCMI_SRST_OTPC_S 30 +#define SCMI_SRST_WDT_S 31 +/* Name=SECURE_SOFTRST_CON02,Offset=0xA08 */ +#define SCMI_SRST_T_WDT_S 32 +#define SCMI_SRST_H_BOOTROM 33 +#define SCMI_SRST_A_DCF 34 +#define SCMI_SRST_P_DCF 35 +#define SCMI_SRST_H_BOOTROM_NS 37 +#define SCMI_SRST_P_KEYLADDER 46 +#define SCMI_SRST_H_TRNG_S 47 +/* Name=SECURE_SOFTRST_CON03,Offset=0xA0C */ +#define SCMI_SRST_H_TRNG_NS 48 +#define SCMI_SRST_D_SDMMC_BUFFER 49 +#define SCMI_SRST_H_SDMMC 50 +#define SCMI_SRST_H_SDMMC_BUFFER 51 +#define SCMI_SRST_SDMMC 52 +#define SCMI_SRST_P_TRNG_CHK 53 +#define SCMI_SRST_TRNG_S 54 + + #endif diff --git a/include/dt-bindings/reset/sun50i-h616-ccu.h b/include/dt-bindings/reset/sun50i-h616-ccu.h index ed177c04afdd..ba626f7015b5 100644 --- a/include/dt-bindings/reset/sun50i-h616-ccu.h +++ b/include/dt-bindings/reset/sun50i-h616-ccu.h @@ -67,5 +67,8 @@ #define RST_BUS_HDCP 58 #define RST_BUS_KEYADC 59 #define RST_BUS_GPADC 60 +#define RST_BUS_TCON_LCD0 61 +#define RST_BUS_TCON_LCD1 62 +#define RST_BUS_LVDS 63 #endif /* _DT_BINDINGS_RESET_SUN50I_H616_H_ */ diff --git a/include/dt-bindings/reset/sun55i-a523-ccu.h b/include/dt-bindings/reset/sun55i-a523-ccu.h new file mode 100644 index 000000000000..70df503f34fe --- /dev/null +++ b/include/dt-bindings/reset/sun55i-a523-ccu.h @@ -0,0 +1,88 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */ +/* + * Copyright (c) 2024 Arm Ltd. + */ + +#ifndef _DT_BINDINGS_RST_SUN55I_A523_CCU_H_ +#define _DT_BINDINGS_RST_SUN55I_A523_CCU_H_ + +#define RST_MBUS 0 +#define RST_BUS_NSI 1 +#define RST_BUS_DE 2 +#define RST_BUS_DI 3 +#define RST_BUS_G2D 4 +#define RST_BUS_SYS 5 +#define RST_BUS_GPU 6 +#define RST_BUS_CE 7 +#define RST_BUS_SYS_CE 8 +#define RST_BUS_VE 9 +#define RST_BUS_DMA 10 +#define RST_BUS_MSGBOX 11 +#define RST_BUS_SPINLOCK 12 +#define RST_BUS_CPUXTIMER 13 +#define RST_BUS_DBG 14 +#define RST_BUS_PWM0 15 +#define RST_BUS_PWM1 16 +#define RST_BUS_DRAM 17 +#define RST_BUS_NAND 18 +#define RST_BUS_MMC0 19 +#define RST_BUS_MMC1 20 +#define RST_BUS_MMC2 21 +#define RST_BUS_SYSDAP 22 +#define RST_BUS_UART0 23 +#define RST_BUS_UART1 24 +#define RST_BUS_UART2 25 +#define RST_BUS_UART3 26 +#define RST_BUS_UART4 27 +#define RST_BUS_UART5 28 +#define RST_BUS_UART6 29 +#define RST_BUS_UART7 30 +#define RST_BUS_I2C0 31 +#define RST_BUS_I2C1 32 +#define RST_BUS_I2C2 33 +#define RST_BUS_I2C3 34 +#define RST_BUS_I2C4 35 +#define RST_BUS_I2C5 36 +#define RST_BUS_CAN 37 +#define RST_BUS_SPI0 38 +#define RST_BUS_SPI1 39 +#define RST_BUS_SPI2 40 +#define RST_BUS_SPIFC 41 +#define RST_BUS_EMAC0 42 +#define RST_BUS_EMAC1 43 +#define RST_BUS_IR_RX 44 +#define RST_BUS_IR_TX 45 +#define RST_BUS_GPADC0 46 +#define RST_BUS_GPADC1 47 +#define RST_BUS_THS 48 +#define RST_USB_PHY0 49 +#define RST_USB_PHY1 50 +#define RST_BUS_OHCI0 51 +#define RST_BUS_OHCI1 52 +#define RST_BUS_EHCI0 53 +#define RST_BUS_EHCI1 54 +#define RST_BUS_OTG 55 +#define RST_BUS_3 56 +#define RST_BUS_LRADC 57 +#define RST_BUS_PCIE_USB3 58 +#define RST_BUS_DISPLAY0_TOP 59 +#define RST_BUS_DISPLAY1_TOP 60 +#define RST_BUS_HDMI_MAIN 61 +#define RST_BUS_HDMI_SUB 62 +#define RST_BUS_MIPI_DSI0 63 +#define RST_BUS_MIPI_DSI1 64 +#define RST_BUS_TCON_LCD0 65 +#define RST_BUS_TCON_LCD1 66 +#define RST_BUS_TCON_LCD2 67 +#define RST_BUS_TCON_TV0 68 +#define RST_BUS_TCON_TV1 69 +#define RST_BUS_LVDS0 70 +#define RST_BUS_LVDS1 71 +#define RST_BUS_EDP 72 +#define RST_BUS_VIDEO_OUT0 73 +#define RST_BUS_VIDEO_OUT1 74 +#define RST_BUS_LEDC 75 +#define RST_BUS_CSI 76 +#define RST_BUS_ISP 77 + +#endif /* _DT_BINDINGS_RST_SUN55I_A523_CCU_H_ */ diff --git a/include/dt-bindings/reset/sun55i-a523-r-ccu.h b/include/dt-bindings/reset/sun55i-a523-r-ccu.h new file mode 100644 index 000000000000..eb31ae9958d6 --- /dev/null +++ b/include/dt-bindings/reset/sun55i-a523-r-ccu.h @@ -0,0 +1,26 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */ +/* + * Copyright (C) 2024 Arm Ltd. + */ + +#ifndef _DT_BINDINGS_RST_SUN55I_A523_R_CCU_H_ +#define _DT_BINDINGS_RST_SUN55I_A523_R_CCU_H_ + +#define RST_BUS_R_TIMER 0 +#define RST_BUS_R_TWD 1 +#define RST_BUS_R_PWMCTRL 2 +#define RST_BUS_R_SPI 3 +#define RST_BUS_R_SPINLOCK 4 +#define RST_BUS_R_MSGBOX 5 +#define RST_BUS_R_UART0 6 +#define RST_BUS_R_UART1 7 +#define RST_BUS_R_I2C0 8 +#define RST_BUS_R_I2C1 9 +#define RST_BUS_R_I2C2 10 +#define RST_BUS_R_PPU1 11 +#define RST_BUS_R_IR_RX 12 +#define RST_BUS_R_RTC 13 +#define RST_BUS_R_CPUCFG 14 +#define RST_BUS_R_PPU0 15 + +#endif /* _DT_BINDINGS_RST_SUN55I_A523_R_CCU_H_ */ diff --git a/include/dt-bindings/reset/thead,th1520-reset.h b/include/dt-bindings/reset/thead,th1520-reset.h new file mode 100644 index 000000000000..00459f160489 --- /dev/null +++ b/include/dt-bindings/reset/thead,th1520-reset.h @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) 2024 Samsung Electronics Co., Ltd. + * Author: Michal Wilczynski <m.wilczynski@samsung.com> + */ + +#ifndef _DT_BINDINGS_TH1520_RESET_H +#define _DT_BINDINGS_TH1520_RESET_H + +#define TH1520_RESET_ID_GPU 0 +#define TH1520_RESET_ID_GPU_CLKGEN 1 +#define TH1520_RESET_ID_NPU 2 +#define TH1520_RESET_ID_WDT0 3 +#define TH1520_RESET_ID_WDT1 4 + +#endif /* _DT_BINDINGS_TH1520_RESET_H */ diff --git a/include/dt-bindings/soc/samsung,exynos-usi.h b/include/dt-bindings/soc/samsung,exynos-usi.h index a01af169d249..b46de214dd09 100644 --- a/include/dt-bindings/soc/samsung,exynos-usi.h +++ b/include/dt-bindings/soc/samsung,exynos-usi.h @@ -9,9 +9,18 @@ #ifndef __DT_BINDINGS_SAMSUNG_EXYNOS_USI_H #define __DT_BINDINGS_SAMSUNG_EXYNOS_USI_H -#define USI_V2_NONE 0 -#define USI_V2_UART 1 -#define USI_V2_SPI 2 -#define USI_V2_I2C 3 +#define USI_MODE_NONE 0 +#define USI_MODE_UART 1 +#define USI_MODE_SPI 2 +#define USI_MODE_I2C 3 +#define USI_MODE_I2C1 4 +#define USI_MODE_I2C0_1 5 +#define USI_MODE_UART_I2C1 6 + +/* Deprecated */ +#define USI_V2_NONE USI_MODE_NONE +#define USI_V2_UART USI_MODE_UART +#define USI_V2_SPI USI_MODE_SPI +#define USI_V2_I2C USI_MODE_I2C #endif /* __DT_BINDINGS_SAMSUNG_EXYNOS_USI_H */ diff --git a/include/dt-bindings/sound/cs48l32.h b/include/dt-bindings/sound/cs48l32.h new file mode 100644 index 000000000000..4e82260fff67 --- /dev/null +++ b/include/dt-bindings/sound/cs48l32.h @@ -0,0 +1,20 @@ +/* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */ +/* + * Device Tree defines for CS48L32 DSP. + * + * Copyright (C) 2016-2018, 2022, 2025 Cirrus Logic, Inc. and + * Cirrus Logic International Semiconductor Ltd. + */ + +#ifndef DT_BINDINGS_SOUND_CS48L32_H +#define DT_BINDINGS_SOUND_CS48L32_H + +/* Values for cirrus,in-type */ +#define CS48L32_IN_TYPE_DIFF 0 +#define CS48L32_IN_TYPE_SE 1 + +/* Values for cirrus,pdm-sup */ +#define CS48L32_PDM_SUP_VOUT_MIC 0 +#define CS48L32_PDM_SUP_MICBIAS1 1 + +#endif diff --git a/include/dt-bindings/sound/qcom,q6dsp-lpass-ports.h b/include/dt-bindings/sound/qcom,q6dsp-lpass-ports.h index 39f203256c4f..6d1ce7f5da51 100644 --- a/include/dt-bindings/sound/qcom,q6dsp-lpass-ports.h +++ b/include/dt-bindings/sound/qcom,q6dsp-lpass-ports.h @@ -139,6 +139,7 @@ #define DISPLAY_PORT_RX_5 133 #define DISPLAY_PORT_RX_6 134 #define DISPLAY_PORT_RX_7 135 +#define USB_RX 136 #define LPASS_CLK_ID_PRI_MI2S_IBIT 1 #define LPASS_CLK_ID_PRI_MI2S_EBIT 2 diff --git a/include/dt-bindings/sound/qcom,wcd934x.h b/include/dt-bindings/sound/qcom,wcd934x.h new file mode 100644 index 000000000000..8b30d34fcc87 --- /dev/null +++ b/include/dt-bindings/sound/qcom,wcd934x.h @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ + +#ifndef __DT_SOUND_QCOM_WCD934x_H +#define __DT_SOUND_QCOM_WCD934x_H + +#define AIF1_PB 0 +#define AIF1_CAP 1 +#define AIF2_PB 2 +#define AIF2_CAP 3 +#define AIF3_PB 4 +#define AIF3_CAP 5 +#define AIF4_PB 6 +#define AIF4_VIFEED 7 +#define AIF4_MAD_TX 8 + +#endif |