diff options
Diffstat (limited to 'drivers/pinctrl/qcom')
66 files changed, 3542 insertions, 152 deletions
diff --git a/drivers/pinctrl/qcom/Kconfig b/drivers/pinctrl/qcom/Kconfig index dd9bbe8f3e11..c480e8b78503 100644 --- a/drivers/pinctrl/qcom/Kconfig +++ b/drivers/pinctrl/qcom/Kconfig @@ -8,6 +8,7 @@ config PINCTRL_MSM depends on OF select QCOM_SCM select PINMUX + select GENERIC_PINMUX_FUNCTIONS select PINCONF select GENERIC_PINCONF select GPIOLIB_IRQCHIP @@ -68,6 +69,16 @@ config PINCTRL_SC7280_LPASS_LPI Qualcomm Technologies Inc LPASS (Low Power Audio SubSystem) LPI (Low Power Island) found on the Qualcomm Technologies Inc SC7280 platform. +config PINCTRL_SDM660_LPASS_LPI + tristate "Qualcomm Technologies Inc SDM660 LPASS LPI pin controller driver" + depends on GPIOLIB + depends on ARM64 || COMPILE_TEST + depends on PINCTRL_LPASS_LPI + help + This is the pinctrl, pinmux, pinconf and gpiolib driver for the + Qualcomm Technologies Inc LPASS (Low Power Audio SubSystem) LPI + (Low Power Island) found on the Qualcomm Technologies Inc SDM660 platform. + config PINCTRL_SM4250_LPASS_LPI tristate "Qualcomm Technologies Inc SM4250 LPASS LPI pin controller driver" depends on ARM64 || COMPILE_TEST diff --git a/drivers/pinctrl/qcom/Kconfig.msm b/drivers/pinctrl/qcom/Kconfig.msm index 0bb44c9a4c06..69a5b47adedc 100644 --- a/drivers/pinctrl/qcom/Kconfig.msm +++ b/drivers/pinctrl/qcom/Kconfig.msm @@ -15,6 +15,16 @@ config PINCTRL_APQ8084 This is the pinctrl, pinmux, pinconf and gpiolib driver for the Qualcomm TLMM block found in the Qualcomm APQ8084 platform. +config PINCTRL_GLYMUR + tristate "Qualcomm Technologies Inc Glymur pin controller driver" + depends on ARM64 || COMPILE_TEST + help + This is the pinctrl, pinmux, pinconf and gpiolib driver for the + Qualcomm Technologies Inc Top Level Mode Multiplexer block (TLMM) + block found on the Qualcomm Technologies Inc Glymur platform. + Say Y here to compile statically, or M here to compile it as a module. + If unsure, say N. + config PINCTRL_IPQ4019 tristate "Qualcomm IPQ4019 pin controller driver" depends on ARM || COMPILE_TEST @@ -371,6 +381,14 @@ config PINCTRL_SM7150 Qualcomm Technologies Inc TLMM block found on the Qualcomm Technologies Inc SM7150 platform. +config PINCTRL_MILOS + tristate "Qualcomm Technologies Inc Milos pin controller driver" + depends on ARM64 || COMPILE_TEST + help + This is the pinctrl, pinmux, pinconf and gpiolib driver for the + Qualcomm Technologies Inc TLMM block found on the Qualcomm + Technologies Inc Milos platform. + config PINCTRL_SM8150 tristate "Qualcomm Technologies Inc SM8150 pin controller driver" depends on ARM64 || COMPILE_TEST diff --git a/drivers/pinctrl/qcom/Makefile b/drivers/pinctrl/qcom/Makefile index 954f5291cc37..567d3051e760 100644 --- a/drivers/pinctrl/qcom/Makefile +++ b/drivers/pinctrl/qcom/Makefile @@ -3,6 +3,7 @@ obj-$(CONFIG_PINCTRL_MSM) += pinctrl-msm.o obj-$(CONFIG_PINCTRL_APQ8064) += pinctrl-apq8064.o obj-$(CONFIG_PINCTRL_APQ8084) += pinctrl-apq8084.o +obj-$(CONFIG_PINCTRL_GLYMUR) += pinctrl-glymur.o obj-$(CONFIG_PINCTRL_IPQ4019) += pinctrl-ipq4019.o obj-$(CONFIG_PINCTRL_IPQ5018) += pinctrl-ipq5018.o obj-$(CONFIG_PINCTRL_IPQ8064) += pinctrl-ipq8064.o @@ -30,6 +31,7 @@ obj-$(CONFIG_PINCTRL_QCS8300) += pinctrl-qcs8300.o obj-$(CONFIG_PINCTRL_QDF2XXX) += pinctrl-qdf2xxx.o obj-$(CONFIG_PINCTRL_MDM9607) += pinctrl-mdm9607.o obj-$(CONFIG_PINCTRL_MDM9615) += pinctrl-mdm9615.o +obj-$(CONFIG_PINCTRL_MILOS) += pinctrl-milos.o obj-$(CONFIG_PINCTRL_QCOM_SPMI_PMIC) += pinctrl-spmi-gpio.o obj-$(CONFIG_PINCTRL_QCOM_SPMI_PMIC) += pinctrl-spmi-mpp.o obj-$(CONFIG_PINCTRL_QCOM_SSBI_PMIC) += pinctrl-ssbi-gpio.o @@ -43,6 +45,7 @@ obj-$(CONFIG_PINCTRL_SC7280_LPASS_LPI) += pinctrl-sc7280-lpass-lpi.o obj-$(CONFIG_PINCTRL_SC8180X) += pinctrl-sc8180x.o obj-$(CONFIG_PINCTRL_SC8280XP) += pinctrl-sc8280xp.o obj-$(CONFIG_PINCTRL_SDM660) += pinctrl-sdm660.o +obj-$(CONFIG_PINCTRL_SDM660_LPASS_LPI) += pinctrl-sdm660-lpass-lpi.o obj-$(CONFIG_PINCTRL_SDM670) += pinctrl-sdm670.o obj-$(CONFIG_PINCTRL_SDM845) += pinctrl-sdm845.o obj-$(CONFIG_PINCTRL_SDX55) += pinctrl-sdx55.o diff --git a/drivers/pinctrl/qcom/pinctrl-glymur.c b/drivers/pinctrl/qcom/pinctrl-glymur.c new file mode 100644 index 000000000000..9913f98e9531 --- /dev/null +++ b/drivers/pinctrl/qcom/pinctrl-glymur.c @@ -0,0 +1,1777 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2025 Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#include <linux/module.h> +#include <linux/of.h> +#include <linux/of_device.h> +#include <linux/platform_device.h> +#include <linux/pinctrl/pinctrl.h> + +#include "pinctrl-msm.h" + +#define REG_SIZE 0x1000 +#define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7, f8, f9, f10, f11) \ + { \ + .grp = PINCTRL_PINGROUP("gpio" #id, \ + gpio##id##_pins, \ + ARRAY_SIZE(gpio##id##_pins)), \ + .ctl_reg = REG_SIZE * id, \ + .io_reg = 0x4 + REG_SIZE * id, \ + .intr_cfg_reg = 0x8 + REG_SIZE * id, \ + .intr_status_reg = 0xc + REG_SIZE * id, \ + .intr_target_reg = 0x8 + REG_SIZE * id, \ + .mux_bit = 2, \ + .pull_bit = 0, \ + .drv_bit = 6, \ + .egpio_enable = 12, \ + .egpio_present = 11, \ + .oe_bit = 9, \ + .in_bit = 0, \ + .out_bit = 1, \ + .intr_enable_bit = 0, \ + .intr_status_bit = 0, \ + .intr_target_bit = 5, \ + .intr_target_kpss_val = 3, \ + .intr_raw_status_bit = 4, \ + .intr_polarity_bit = 1, \ + .intr_detection_bit = 2, \ + .intr_detection_width = 2, \ + .funcs = (int[]){ \ + msm_mux_gpio, /* gpio mode */ \ + msm_mux_##f1, \ + msm_mux_##f2, \ + msm_mux_##f3, \ + msm_mux_##f4, \ + msm_mux_##f5, \ + msm_mux_##f6, \ + msm_mux_##f7, \ + msm_mux_##f8, \ + msm_mux_##f9, \ + msm_mux_##f10, \ + msm_mux_##f11 /* egpio mode */ \ + }, \ + .nfuncs = 12, \ + } + +#define SDC_QDSD_PINGROUP(pg_name, ctl, pull, drv) \ + { \ + .grp = PINCTRL_PINGROUP(#pg_name, \ + pg_name##_pins, \ + ARRAY_SIZE(pg_name##_pins)), \ + .ctl_reg = ctl, \ + .io_reg = 0, \ + .intr_cfg_reg = 0, \ + .intr_status_reg = 0, \ + .intr_target_reg = 0, \ + .mux_bit = -1, \ + .pull_bit = pull, \ + .drv_bit = drv, \ + .oe_bit = -1, \ + .in_bit = -1, \ + .out_bit = -1, \ + .intr_enable_bit = -1, \ + .intr_status_bit = -1, \ + .intr_target_bit = -1, \ + .intr_raw_status_bit = -1, \ + .intr_polarity_bit = -1, \ + .intr_detection_bit = -1, \ + .intr_detection_width = -1, \ + } + +#define UFS_RESET(pg_name, ctl, io) \ + { \ + .grp = PINCTRL_PINGROUP(#pg_name, \ + pg_name##_pins, \ + ARRAY_SIZE(pg_name##_pins)), \ + .ctl_reg = ctl, \ + .io_reg = io, \ + .intr_cfg_reg = 0, \ + .intr_status_reg = 0, \ + .intr_target_reg = 0, \ + .mux_bit = -1, \ + .pull_bit = 3, \ + .drv_bit = 0, \ + .oe_bit = -1, \ + .in_bit = -1, \ + .out_bit = 0, \ + .intr_enable_bit = -1, \ + .intr_status_bit = -1, \ + .intr_target_bit = -1, \ + .intr_raw_status_bit = -1, \ + .intr_polarity_bit = -1, \ + .intr_detection_bit = -1, \ + .intr_detection_width = -1, \ + } + +static const struct pinctrl_pin_desc glymur_pins[] = { + PINCTRL_PIN(0, "GPIO_0"), + PINCTRL_PIN(1, "GPIO_1"), + PINCTRL_PIN(2, "GPIO_2"), + PINCTRL_PIN(3, "GPIO_3"), + PINCTRL_PIN(4, "GPIO_4"), + PINCTRL_PIN(5, "GPIO_5"), + PINCTRL_PIN(6, "GPIO_6"), + PINCTRL_PIN(7, "GPIO_7"), + PINCTRL_PIN(8, "GPIO_8"), + PINCTRL_PIN(9, "GPIO_9"), + PINCTRL_PIN(10, "GPIO_10"), + PINCTRL_PIN(11, "GPIO_11"), + PINCTRL_PIN(12, "GPIO_12"), + PINCTRL_PIN(13, "GPIO_13"), + PINCTRL_PIN(14, "GPIO_14"), + PINCTRL_PIN(15, "GPIO_15"), + PINCTRL_PIN(16, "GPIO_16"), + PINCTRL_PIN(17, "GPIO_17"), + PINCTRL_PIN(18, "GPIO_18"), + PINCTRL_PIN(19, "GPIO_19"), + PINCTRL_PIN(20, "GPIO_20"), + PINCTRL_PIN(21, "GPIO_21"), + PINCTRL_PIN(22, "GPIO_22"), + PINCTRL_PIN(23, "GPIO_23"), + PINCTRL_PIN(24, "GPIO_24"), + PINCTRL_PIN(25, "GPIO_25"), + PINCTRL_PIN(26, "GPIO_26"), + PINCTRL_PIN(27, "GPIO_27"), + PINCTRL_PIN(28, "GPIO_28"), + PINCTRL_PIN(29, "GPIO_29"), + PINCTRL_PIN(30, "GPIO_30"), + PINCTRL_PIN(31, "GPIO_31"), + PINCTRL_PIN(32, "GPIO_32"), + PINCTRL_PIN(33, "GPIO_33"), + PINCTRL_PIN(34, "GPIO_34"), + PINCTRL_PIN(35, "GPIO_35"), + PINCTRL_PIN(36, "GPIO_36"), + PINCTRL_PIN(37, "GPIO_37"), + PINCTRL_PIN(38, "GPIO_38"), + PINCTRL_PIN(39, "GPIO_39"), + PINCTRL_PIN(40, "GPIO_40"), + PINCTRL_PIN(41, "GPIO_41"), + PINCTRL_PIN(42, "GPIO_42"), + PINCTRL_PIN(43, "GPIO_43"), + PINCTRL_PIN(44, "GPIO_44"), + PINCTRL_PIN(45, "GPIO_45"), + PINCTRL_PIN(46, "GPIO_46"), + PINCTRL_PIN(47, "GPIO_47"), + PINCTRL_PIN(48, "GPIO_48"), + PINCTRL_PIN(49, "GPIO_49"), + PINCTRL_PIN(50, "GPIO_50"), + PINCTRL_PIN(51, "GPIO_51"), + PINCTRL_PIN(52, "GPIO_52"), + PINCTRL_PIN(53, "GPIO_53"), + PINCTRL_PIN(54, "GPIO_54"), + PINCTRL_PIN(55, "GPIO_55"), + PINCTRL_PIN(56, "GPIO_56"), + PINCTRL_PIN(57, "GPIO_57"), + PINCTRL_PIN(58, "GPIO_58"), + PINCTRL_PIN(59, "GPIO_59"), + PINCTRL_PIN(60, "GPIO_60"), + PINCTRL_PIN(61, "GPIO_61"), + PINCTRL_PIN(62, "GPIO_62"), + PINCTRL_PIN(63, "GPIO_63"), + PINCTRL_PIN(64, "GPIO_64"), + PINCTRL_PIN(65, "GPIO_65"), + PINCTRL_PIN(66, "GPIO_66"), + PINCTRL_PIN(67, "GPIO_67"), + PINCTRL_PIN(68, "GPIO_68"), + PINCTRL_PIN(69, "GPIO_69"), + PINCTRL_PIN(70, "GPIO_70"), + PINCTRL_PIN(71, "GPIO_71"), + PINCTRL_PIN(72, "GPIO_72"), + PINCTRL_PIN(73, "GPIO_73"), + PINCTRL_PIN(74, "GPIO_74"), + PINCTRL_PIN(75, "GPIO_75"), + PINCTRL_PIN(76, "GPIO_76"), + PINCTRL_PIN(77, "GPIO_77"), + PINCTRL_PIN(78, "GPIO_78"), + PINCTRL_PIN(79, "GPIO_79"), + PINCTRL_PIN(80, "GPIO_80"), + PINCTRL_PIN(81, "GPIO_81"), + PINCTRL_PIN(82, "GPIO_82"), + PINCTRL_PIN(83, "GPIO_83"), + PINCTRL_PIN(84, "GPIO_84"), + PINCTRL_PIN(85, "GPIO_85"), + PINCTRL_PIN(86, "GPIO_86"), + PINCTRL_PIN(87, "GPIO_87"), + PINCTRL_PIN(88, "GPIO_88"), + PINCTRL_PIN(89, "GPIO_89"), + PINCTRL_PIN(90, "GPIO_90"), + PINCTRL_PIN(91, "GPIO_91"), + PINCTRL_PIN(92, "GPIO_92"), + PINCTRL_PIN(93, "GPIO_93"), + PINCTRL_PIN(94, "GPIO_94"), + PINCTRL_PIN(95, "GPIO_95"), + PINCTRL_PIN(96, "GPIO_96"), + PINCTRL_PIN(97, "GPIO_97"), + PINCTRL_PIN(98, "GPIO_98"), + PINCTRL_PIN(99, "GPIO_99"), + PINCTRL_PIN(100, "GPIO_100"), + PINCTRL_PIN(101, "GPIO_101"), + PINCTRL_PIN(102, "GPIO_102"), + PINCTRL_PIN(103, "GPIO_103"), + PINCTRL_PIN(104, "GPIO_104"), + PINCTRL_PIN(105, "GPIO_105"), + PINCTRL_PIN(106, "GPIO_106"), + PINCTRL_PIN(107, "GPIO_107"), + PINCTRL_PIN(108, "GPIO_108"), + PINCTRL_PIN(109, "GPIO_109"), + PINCTRL_PIN(110, "GPIO_110"), + PINCTRL_PIN(111, "GPIO_111"), + PINCTRL_PIN(112, "GPIO_112"), + PINCTRL_PIN(113, "GPIO_113"), + PINCTRL_PIN(114, "GPIO_114"), + PINCTRL_PIN(115, "GPIO_115"), + PINCTRL_PIN(116, "GPIO_116"), + PINCTRL_PIN(117, "GPIO_117"), + PINCTRL_PIN(118, "GPIO_118"), + PINCTRL_PIN(119, "GPIO_119"), + PINCTRL_PIN(120, "GPIO_120"), + PINCTRL_PIN(121, "GPIO_121"), + PINCTRL_PIN(122, "GPIO_122"), + PINCTRL_PIN(123, "GPIO_123"), + PINCTRL_PIN(124, "GPIO_124"), + PINCTRL_PIN(125, "GPIO_125"), + PINCTRL_PIN(126, "GPIO_126"), + PINCTRL_PIN(127, "GPIO_127"), + PINCTRL_PIN(128, "GPIO_128"), + PINCTRL_PIN(129, "GPIO_129"), + PINCTRL_PIN(130, "GPIO_130"), + PINCTRL_PIN(131, "GPIO_131"), + PINCTRL_PIN(132, "GPIO_132"), + PINCTRL_PIN(133, "GPIO_133"), + PINCTRL_PIN(134, "GPIO_134"), + PINCTRL_PIN(135, "GPIO_135"), + PINCTRL_PIN(136, "GPIO_136"), + PINCTRL_PIN(137, "GPIO_137"), + PINCTRL_PIN(138, "GPIO_138"), + PINCTRL_PIN(139, "GPIO_139"), + PINCTRL_PIN(140, "GPIO_140"), + PINCTRL_PIN(141, "GPIO_141"), + PINCTRL_PIN(142, "GPIO_142"), + PINCTRL_PIN(143, "GPIO_143"), + PINCTRL_PIN(144, "GPIO_144"), + PINCTRL_PIN(145, "GPIO_145"), + PINCTRL_PIN(146, "GPIO_146"), + PINCTRL_PIN(147, "GPIO_147"), + PINCTRL_PIN(148, "GPIO_148"), + PINCTRL_PIN(149, "GPIO_149"), + PINCTRL_PIN(150, "GPIO_150"), + PINCTRL_PIN(151, "GPIO_151"), + PINCTRL_PIN(152, "GPIO_152"), + PINCTRL_PIN(153, "GPIO_153"), + PINCTRL_PIN(154, "GPIO_154"), + PINCTRL_PIN(155, "GPIO_155"), + PINCTRL_PIN(156, "GPIO_156"), + PINCTRL_PIN(157, "GPIO_157"), + PINCTRL_PIN(158, "GPIO_158"), + PINCTRL_PIN(159, "GPIO_159"), + PINCTRL_PIN(160, "GPIO_160"), + PINCTRL_PIN(161, "GPIO_161"), + PINCTRL_PIN(162, "GPIO_162"), + PINCTRL_PIN(163, "GPIO_163"), + PINCTRL_PIN(164, "GPIO_164"), + PINCTRL_PIN(165, "GPIO_165"), + PINCTRL_PIN(166, "GPIO_166"), + PINCTRL_PIN(167, "GPIO_167"), + PINCTRL_PIN(168, "GPIO_168"), + PINCTRL_PIN(169, "GPIO_169"), + PINCTRL_PIN(170, "GPIO_170"), + PINCTRL_PIN(171, "GPIO_171"), + PINCTRL_PIN(172, "GPIO_172"), + PINCTRL_PIN(173, "GPIO_173"), + PINCTRL_PIN(174, "GPIO_174"), + PINCTRL_PIN(175, "GPIO_175"), + PINCTRL_PIN(176, "GPIO_176"), + PINCTRL_PIN(177, "GPIO_177"), + PINCTRL_PIN(178, "GPIO_178"), + PINCTRL_PIN(179, "GPIO_179"), + PINCTRL_PIN(180, "GPIO_180"), + PINCTRL_PIN(181, "GPIO_181"), + PINCTRL_PIN(182, "GPIO_182"), + PINCTRL_PIN(183, "GPIO_183"), + PINCTRL_PIN(184, "GPIO_184"), + PINCTRL_PIN(185, "GPIO_185"), + PINCTRL_PIN(186, "GPIO_186"), + PINCTRL_PIN(187, "GPIO_187"), + PINCTRL_PIN(188, "GPIO_188"), + PINCTRL_PIN(189, "GPIO_189"), + PINCTRL_PIN(190, "GPIO_190"), + PINCTRL_PIN(191, "GPIO_191"), + PINCTRL_PIN(192, "GPIO_192"), + PINCTRL_PIN(193, "GPIO_193"), + PINCTRL_PIN(194, "GPIO_194"), + PINCTRL_PIN(195, "GPIO_195"), + PINCTRL_PIN(196, "GPIO_196"), + PINCTRL_PIN(197, "GPIO_197"), + PINCTRL_PIN(198, "GPIO_198"), + PINCTRL_PIN(199, "GPIO_199"), + PINCTRL_PIN(200, "GPIO_200"), + PINCTRL_PIN(201, "GPIO_201"), + PINCTRL_PIN(202, "GPIO_202"), + PINCTRL_PIN(203, "GPIO_203"), + PINCTRL_PIN(204, "GPIO_204"), + PINCTRL_PIN(205, "GPIO_205"), + PINCTRL_PIN(206, "GPIO_206"), + PINCTRL_PIN(207, "GPIO_207"), + PINCTRL_PIN(208, "GPIO_208"), + PINCTRL_PIN(209, "GPIO_209"), + PINCTRL_PIN(210, "GPIO_210"), + PINCTRL_PIN(211, "GPIO_211"), + PINCTRL_PIN(212, "GPIO_212"), + PINCTRL_PIN(213, "GPIO_213"), + PINCTRL_PIN(214, "GPIO_214"), + PINCTRL_PIN(215, "GPIO_215"), + PINCTRL_PIN(216, "GPIO_216"), + PINCTRL_PIN(217, "GPIO_217"), + PINCTRL_PIN(218, "GPIO_218"), + PINCTRL_PIN(219, "GPIO_219"), + PINCTRL_PIN(220, "GPIO_220"), + PINCTRL_PIN(221, "GPIO_221"), + PINCTRL_PIN(222, "GPIO_222"), + PINCTRL_PIN(223, "GPIO_223"), + PINCTRL_PIN(224, "GPIO_224"), + PINCTRL_PIN(225, "GPIO_225"), + PINCTRL_PIN(226, "GPIO_226"), + PINCTRL_PIN(227, "GPIO_227"), + PINCTRL_PIN(228, "GPIO_228"), + PINCTRL_PIN(229, "GPIO_229"), + PINCTRL_PIN(230, "GPIO_230"), + PINCTRL_PIN(231, "GPIO_231"), + PINCTRL_PIN(232, "GPIO_232"), + PINCTRL_PIN(233, "GPIO_233"), + PINCTRL_PIN(234, "GPIO_234"), + PINCTRL_PIN(235, "GPIO_235"), + PINCTRL_PIN(236, "GPIO_236"), + PINCTRL_PIN(237, "GPIO_237"), + PINCTRL_PIN(238, "GPIO_238"), + PINCTRL_PIN(239, "GPIO_239"), + PINCTRL_PIN(240, "GPIO_240"), + PINCTRL_PIN(241, "GPIO_241"), + PINCTRL_PIN(242, "GPIO_242"), + PINCTRL_PIN(243, "GPIO_243"), + PINCTRL_PIN(244, "GPIO_244"), + PINCTRL_PIN(245, "GPIO_245"), + PINCTRL_PIN(246, "GPIO_246"), + PINCTRL_PIN(247, "GPIO_247"), + PINCTRL_PIN(248, "GPIO_248"), + PINCTRL_PIN(249, "GPIO_249"), +}; + +#define DECLARE_MSM_GPIO_PINS(pin) \ + static const unsigned int gpio##pin##_pins[] = { pin } +DECLARE_MSM_GPIO_PINS(0); +DECLARE_MSM_GPIO_PINS(1); +DECLARE_MSM_GPIO_PINS(2); +DECLARE_MSM_GPIO_PINS(3); +DECLARE_MSM_GPIO_PINS(4); +DECLARE_MSM_GPIO_PINS(5); +DECLARE_MSM_GPIO_PINS(6); +DECLARE_MSM_GPIO_PINS(7); +DECLARE_MSM_GPIO_PINS(8); +DECLARE_MSM_GPIO_PINS(9); +DECLARE_MSM_GPIO_PINS(10); +DECLARE_MSM_GPIO_PINS(11); +DECLARE_MSM_GPIO_PINS(12); +DECLARE_MSM_GPIO_PINS(13); +DECLARE_MSM_GPIO_PINS(14); +DECLARE_MSM_GPIO_PINS(15); +DECLARE_MSM_GPIO_PINS(16); +DECLARE_MSM_GPIO_PINS(17); +DECLARE_MSM_GPIO_PINS(18); +DECLARE_MSM_GPIO_PINS(19); +DECLARE_MSM_GPIO_PINS(20); +DECLARE_MSM_GPIO_PINS(21); +DECLARE_MSM_GPIO_PINS(22); +DECLARE_MSM_GPIO_PINS(23); +DECLARE_MSM_GPIO_PINS(24); +DECLARE_MSM_GPIO_PINS(25); +DECLARE_MSM_GPIO_PINS(26); +DECLARE_MSM_GPIO_PINS(27); +DECLARE_MSM_GPIO_PINS(28); +DECLARE_MSM_GPIO_PINS(29); +DECLARE_MSM_GPIO_PINS(30); +DECLARE_MSM_GPIO_PINS(31); +DECLARE_MSM_GPIO_PINS(32); +DECLARE_MSM_GPIO_PINS(33); +DECLARE_MSM_GPIO_PINS(34); +DECLARE_MSM_GPIO_PINS(35); +DECLARE_MSM_GPIO_PINS(36); +DECLARE_MSM_GPIO_PINS(37); +DECLARE_MSM_GPIO_PINS(38); +DECLARE_MSM_GPIO_PINS(39); +DECLARE_MSM_GPIO_PINS(40); +DECLARE_MSM_GPIO_PINS(41); +DECLARE_MSM_GPIO_PINS(42); +DECLARE_MSM_GPIO_PINS(43); +DECLARE_MSM_GPIO_PINS(44); +DECLARE_MSM_GPIO_PINS(45); +DECLARE_MSM_GPIO_PINS(46); +DECLARE_MSM_GPIO_PINS(47); +DECLARE_MSM_GPIO_PINS(48); +DECLARE_MSM_GPIO_PINS(49); +DECLARE_MSM_GPIO_PINS(50); +DECLARE_MSM_GPIO_PINS(51); +DECLARE_MSM_GPIO_PINS(52); +DECLARE_MSM_GPIO_PINS(53); +DECLARE_MSM_GPIO_PINS(54); +DECLARE_MSM_GPIO_PINS(55); +DECLARE_MSM_GPIO_PINS(56); +DECLARE_MSM_GPIO_PINS(57); +DECLARE_MSM_GPIO_PINS(58); +DECLARE_MSM_GPIO_PINS(59); +DECLARE_MSM_GPIO_PINS(60); +DECLARE_MSM_GPIO_PINS(61); +DECLARE_MSM_GPIO_PINS(62); +DECLARE_MSM_GPIO_PINS(63); +DECLARE_MSM_GPIO_PINS(64); +DECLARE_MSM_GPIO_PINS(65); +DECLARE_MSM_GPIO_PINS(66); +DECLARE_MSM_GPIO_PINS(67); +DECLARE_MSM_GPIO_PINS(68); +DECLARE_MSM_GPIO_PINS(69); +DECLARE_MSM_GPIO_PINS(70); +DECLARE_MSM_GPIO_PINS(71); +DECLARE_MSM_GPIO_PINS(72); +DECLARE_MSM_GPIO_PINS(73); +DECLARE_MSM_GPIO_PINS(74); +DECLARE_MSM_GPIO_PINS(75); +DECLARE_MSM_GPIO_PINS(76); +DECLARE_MSM_GPIO_PINS(77); +DECLARE_MSM_GPIO_PINS(78); +DECLARE_MSM_GPIO_PINS(79); +DECLARE_MSM_GPIO_PINS(80); +DECLARE_MSM_GPIO_PINS(81); +DECLARE_MSM_GPIO_PINS(82); +DECLARE_MSM_GPIO_PINS(83); +DECLARE_MSM_GPIO_PINS(84); +DECLARE_MSM_GPIO_PINS(85); +DECLARE_MSM_GPIO_PINS(86); +DECLARE_MSM_GPIO_PINS(87); +DECLARE_MSM_GPIO_PINS(88); +DECLARE_MSM_GPIO_PINS(89); +DECLARE_MSM_GPIO_PINS(90); +DECLARE_MSM_GPIO_PINS(91); +DECLARE_MSM_GPIO_PINS(92); +DECLARE_MSM_GPIO_PINS(93); +DECLARE_MSM_GPIO_PINS(94); +DECLARE_MSM_GPIO_PINS(95); +DECLARE_MSM_GPIO_PINS(96); +DECLARE_MSM_GPIO_PINS(97); +DECLARE_MSM_GPIO_PINS(98); +DECLARE_MSM_GPIO_PINS(99); +DECLARE_MSM_GPIO_PINS(100); +DECLARE_MSM_GPIO_PINS(101); +DECLARE_MSM_GPIO_PINS(102); +DECLARE_MSM_GPIO_PINS(103); +DECLARE_MSM_GPIO_PINS(104); +DECLARE_MSM_GPIO_PINS(105); +DECLARE_MSM_GPIO_PINS(106); +DECLARE_MSM_GPIO_PINS(107); +DECLARE_MSM_GPIO_PINS(108); +DECLARE_MSM_GPIO_PINS(109); +DECLARE_MSM_GPIO_PINS(110); +DECLARE_MSM_GPIO_PINS(111); +DECLARE_MSM_GPIO_PINS(112); +DECLARE_MSM_GPIO_PINS(113); +DECLARE_MSM_GPIO_PINS(114); +DECLARE_MSM_GPIO_PINS(115); +DECLARE_MSM_GPIO_PINS(116); +DECLARE_MSM_GPIO_PINS(117); +DECLARE_MSM_GPIO_PINS(118); +DECLARE_MSM_GPIO_PINS(119); +DECLARE_MSM_GPIO_PINS(120); +DECLARE_MSM_GPIO_PINS(121); +DECLARE_MSM_GPIO_PINS(122); +DECLARE_MSM_GPIO_PINS(123); +DECLARE_MSM_GPIO_PINS(124); +DECLARE_MSM_GPIO_PINS(125); +DECLARE_MSM_GPIO_PINS(126); +DECLARE_MSM_GPIO_PINS(127); +DECLARE_MSM_GPIO_PINS(128); +DECLARE_MSM_GPIO_PINS(129); +DECLARE_MSM_GPIO_PINS(130); +DECLARE_MSM_GPIO_PINS(131); +DECLARE_MSM_GPIO_PINS(132); +DECLARE_MSM_GPIO_PINS(133); +DECLARE_MSM_GPIO_PINS(134); +DECLARE_MSM_GPIO_PINS(135); +DECLARE_MSM_GPIO_PINS(136); +DECLARE_MSM_GPIO_PINS(137); +DECLARE_MSM_GPIO_PINS(138); +DECLARE_MSM_GPIO_PINS(139); +DECLARE_MSM_GPIO_PINS(140); +DECLARE_MSM_GPIO_PINS(141); +DECLARE_MSM_GPIO_PINS(142); +DECLARE_MSM_GPIO_PINS(143); +DECLARE_MSM_GPIO_PINS(144); +DECLARE_MSM_GPIO_PINS(145); +DECLARE_MSM_GPIO_PINS(146); +DECLARE_MSM_GPIO_PINS(147); +DECLARE_MSM_GPIO_PINS(148); +DECLARE_MSM_GPIO_PINS(149); +DECLARE_MSM_GPIO_PINS(150); +DECLARE_MSM_GPIO_PINS(151); +DECLARE_MSM_GPIO_PINS(152); +DECLARE_MSM_GPIO_PINS(153); +DECLARE_MSM_GPIO_PINS(154); +DECLARE_MSM_GPIO_PINS(155); +DECLARE_MSM_GPIO_PINS(156); +DECLARE_MSM_GPIO_PINS(157); +DECLARE_MSM_GPIO_PINS(158); +DECLARE_MSM_GPIO_PINS(159); +DECLARE_MSM_GPIO_PINS(160); +DECLARE_MSM_GPIO_PINS(161); +DECLARE_MSM_GPIO_PINS(162); +DECLARE_MSM_GPIO_PINS(163); +DECLARE_MSM_GPIO_PINS(164); +DECLARE_MSM_GPIO_PINS(165); +DECLARE_MSM_GPIO_PINS(166); +DECLARE_MSM_GPIO_PINS(167); +DECLARE_MSM_GPIO_PINS(168); +DECLARE_MSM_GPIO_PINS(169); +DECLARE_MSM_GPIO_PINS(170); +DECLARE_MSM_GPIO_PINS(171); +DECLARE_MSM_GPIO_PINS(172); +DECLARE_MSM_GPIO_PINS(173); +DECLARE_MSM_GPIO_PINS(174); +DECLARE_MSM_GPIO_PINS(175); +DECLARE_MSM_GPIO_PINS(176); +DECLARE_MSM_GPIO_PINS(177); +DECLARE_MSM_GPIO_PINS(178); +DECLARE_MSM_GPIO_PINS(179); +DECLARE_MSM_GPIO_PINS(180); +DECLARE_MSM_GPIO_PINS(181); +DECLARE_MSM_GPIO_PINS(182); +DECLARE_MSM_GPIO_PINS(183); +DECLARE_MSM_GPIO_PINS(184); +DECLARE_MSM_GPIO_PINS(185); +DECLARE_MSM_GPIO_PINS(186); +DECLARE_MSM_GPIO_PINS(187); +DECLARE_MSM_GPIO_PINS(188); +DECLARE_MSM_GPIO_PINS(189); +DECLARE_MSM_GPIO_PINS(190); +DECLARE_MSM_GPIO_PINS(191); +DECLARE_MSM_GPIO_PINS(192); +DECLARE_MSM_GPIO_PINS(193); +DECLARE_MSM_GPIO_PINS(194); +DECLARE_MSM_GPIO_PINS(195); +DECLARE_MSM_GPIO_PINS(196); +DECLARE_MSM_GPIO_PINS(197); +DECLARE_MSM_GPIO_PINS(198); +DECLARE_MSM_GPIO_PINS(199); +DECLARE_MSM_GPIO_PINS(200); +DECLARE_MSM_GPIO_PINS(201); +DECLARE_MSM_GPIO_PINS(202); +DECLARE_MSM_GPIO_PINS(203); +DECLARE_MSM_GPIO_PINS(204); +DECLARE_MSM_GPIO_PINS(205); +DECLARE_MSM_GPIO_PINS(206); +DECLARE_MSM_GPIO_PINS(207); +DECLARE_MSM_GPIO_PINS(208); +DECLARE_MSM_GPIO_PINS(209); +DECLARE_MSM_GPIO_PINS(210); +DECLARE_MSM_GPIO_PINS(211); +DECLARE_MSM_GPIO_PINS(212); +DECLARE_MSM_GPIO_PINS(213); +DECLARE_MSM_GPIO_PINS(214); +DECLARE_MSM_GPIO_PINS(215); +DECLARE_MSM_GPIO_PINS(216); +DECLARE_MSM_GPIO_PINS(217); +DECLARE_MSM_GPIO_PINS(218); +DECLARE_MSM_GPIO_PINS(219); +DECLARE_MSM_GPIO_PINS(220); +DECLARE_MSM_GPIO_PINS(221); +DECLARE_MSM_GPIO_PINS(222); +DECLARE_MSM_GPIO_PINS(223); +DECLARE_MSM_GPIO_PINS(224); +DECLARE_MSM_GPIO_PINS(225); +DECLARE_MSM_GPIO_PINS(226); +DECLARE_MSM_GPIO_PINS(227); +DECLARE_MSM_GPIO_PINS(228); +DECLARE_MSM_GPIO_PINS(229); +DECLARE_MSM_GPIO_PINS(230); +DECLARE_MSM_GPIO_PINS(231); +DECLARE_MSM_GPIO_PINS(232); +DECLARE_MSM_GPIO_PINS(233); +DECLARE_MSM_GPIO_PINS(234); +DECLARE_MSM_GPIO_PINS(235); +DECLARE_MSM_GPIO_PINS(236); +DECLARE_MSM_GPIO_PINS(237); +DECLARE_MSM_GPIO_PINS(238); +DECLARE_MSM_GPIO_PINS(239); +DECLARE_MSM_GPIO_PINS(240); +DECLARE_MSM_GPIO_PINS(241); +DECLARE_MSM_GPIO_PINS(242); +DECLARE_MSM_GPIO_PINS(243); +DECLARE_MSM_GPIO_PINS(244); +DECLARE_MSM_GPIO_PINS(245); +DECLARE_MSM_GPIO_PINS(246); +DECLARE_MSM_GPIO_PINS(247); +DECLARE_MSM_GPIO_PINS(248); +DECLARE_MSM_GPIO_PINS(249); + +static const unsigned int ufs_reset_pins[] = { 250 }; +static const unsigned int sdc2_clk_pins[] = { 251 }; +static const unsigned int sdc2_cmd_pins[] = { 252 }; +static const unsigned int sdc2_data_pins[] = { 253 }; + +enum glymur_functions { + msm_mux_gpio, + msm_mux_resout_gpio_n, + msm_mux_aoss_cti, + msm_mux_asc_cci, + msm_mux_atest_char, + msm_mux_atest_usb, + msm_mux_audio_ext_mclk0, + msm_mux_audio_ext_mclk1, + msm_mux_audio_ref_clk, + msm_mux_cam_asc_mclk4, + msm_mux_cam_mclk, + msm_mux_cci_async_in, + msm_mux_cci_i2c_scl, + msm_mux_cci_i2c_sda, + msm_mux_cci_timer, + msm_mux_cmu_rng, + msm_mux_cri_trng, + msm_mux_dbg_out_clk, + msm_mux_ddr_bist_complete, + msm_mux_ddr_bist_fail, + msm_mux_ddr_bist_start, + msm_mux_ddr_bist_stop, + msm_mux_ddr_pxi, + msm_mux_edp0_hot, + msm_mux_edp0_lcd, + msm_mux_edp1_lcd, + msm_mux_egpio, + msm_mux_eusb_ac_en, + msm_mux_gcc_gp1, + msm_mux_gcc_gp2, + msm_mux_gcc_gp3, + msm_mux_host2wlan_sol, + msm_mux_i2c0_s_scl, + msm_mux_i2c0_s_sda, + msm_mux_i2s0_data, + msm_mux_i2s0_sck, + msm_mux_i2s0_ws, + msm_mux_i2s1_data, + msm_mux_i2s1_sck, + msm_mux_i2s1_ws, + msm_mux_ibi_i3c, + msm_mux_jitter_bist, + msm_mux_mdp_vsync_out, + msm_mux_mdp_vsync_e, + msm_mux_mdp_vsync_p, + msm_mux_mdp_vsync_s, + msm_mux_pcie3a_clk, + msm_mux_pcie3a_rst_n, + msm_mux_pcie3b_clk, + msm_mux_pcie4_clk_req_n, + msm_mux_pcie5_clk_req_n, + msm_mux_pcie6_clk_req_n, + msm_mux_phase_flag, + msm_mux_pll_bist_sync, + msm_mux_pll_clk_aux, + msm_mux_pmc_oca_n, + msm_mux_pmc_uva_n, + msm_mux_prng_rosc, + msm_mux_qdss_cti, + msm_mux_qdss_gpio, + msm_mux_qspi0, + msm_mux_qup0_se0, + msm_mux_qup0_se1, + msm_mux_qup0_se2, + msm_mux_qup0_se3, + msm_mux_qup0_se4, + msm_mux_qup0_se5, + msm_mux_qup0_se6, + msm_mux_qup0_se7, + msm_mux_qup1_se0, + msm_mux_qup1_se1, + msm_mux_qup1_se2, + msm_mux_qup1_se3, + msm_mux_qup1_se4, + msm_mux_qup1_se5, + msm_mux_qup1_se6, + msm_mux_qup1_se7, + msm_mux_qup2_se0, + msm_mux_qup2_se1, + msm_mux_qup2_se2, + msm_mux_qup2_se3, + msm_mux_qup2_se4, + msm_mux_qup2_se5, + msm_mux_qup2_se6, + msm_mux_qup2_se7, + msm_mux_qup3_se0, + msm_mux_qup3_se1, + msm_mux_sd_write_protect, + msm_mux_sdc4_clk, + msm_mux_sdc4_cmd, + msm_mux_sdc4_data, + msm_mux_smb_acok_n, + msm_mux_sys_throttle, + msm_mux_tb_trig_sdc2, + msm_mux_tb_trig_sdc4, + msm_mux_tmess_prng, + msm_mux_tsense_pwm, + msm_mux_tsense_therm, + msm_mux_usb0_dp, + msm_mux_usb0_phy_ps, + msm_mux_usb0_sbrx, + msm_mux_usb0_sbtx, + msm_mux_usb0_tmu, + msm_mux_usb1_dbg, + msm_mux_usb1_dp, + msm_mux_usb1_phy_ps, + msm_mux_usb1_sbrx, + msm_mux_usb1_sbtx, + msm_mux_usb1_tmu, + msm_mux_usb2_dp, + msm_mux_usb2_phy_ps, + msm_mux_usb2_sbrx, + msm_mux_usb2_sbtx, + msm_mux_usb2_tmu, + msm_mux_vsense_trigger_mirnat, + msm_mux_wcn_sw, + msm_mux_wcn_sw_ctrl, + msm_mux__, +}; + +static const char *const gpio_groups[] = { + "gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", + "gpio6", "gpio7", "gpio8", "gpio9", "gpio10", "gpio11", + "gpio12", "gpio13", "gpio14", "gpio15", "gpio16", "gpio17", + "gpio18", "gpio19", "gpio20", "gpio21", "gpio22", "gpio23", + "gpio24", "gpio25", "gpio26", "gpio27", "gpio28", "gpio29", + "gpio30", "gpio31", "gpio32", "gpio33", "gpio34", "gpio35", + "gpio36", "gpio37", "gpio38", "gpio39", "gpio40", "gpio41", + "gpio42", "gpio43", "gpio44", "gpio45", "gpio46", "gpio47", + "gpio48", "gpio49", "gpio50", "gpio51", "gpio52", "gpio53", + "gpio54", "gpio55", "gpio56", "gpio57", "gpio58", "gpio59", + "gpio60", "gpio61", "gpio62", "gpio63", "gpio64", "gpio65", + "gpio66", "gpio67", "gpio68", "gpio69", "gpio70", "gpio71", + "gpio72", "gpio73", "gpio74", "gpio75", "gpio76", "gpio77", + "gpio78", "gpio79", "gpio80", "gpio81", "gpio82", "gpio83", + "gpio84", "gpio85", "gpio86", "gpio87", "gpio88", "gpio89", + "gpio90", "gpio91", "gpio92", "gpio93", "gpio94", "gpio95", + "gpio96", "gpio97", "gpio98", "gpio99", "gpio100", "gpio101", + "gpio102", "gpio103", "gpio104", "gpio105", "gpio106", "gpio107", + "gpio108", "gpio109", "gpio110", "gpio111", "gpio112", "gpio113", + "gpio114", "gpio115", "gpio116", "gpio117", "gpio118", "gpio119", + "gpio120", "gpio121", "gpio122", "gpio123", "gpio124", "gpio125", + "gpio126", "gpio127", "gpio128", "gpio129", "gpio130", "gpio131", + "gpio132", "gpio133", "gpio134", "gpio135", "gpio136", "gpio137", + "gpio138", "gpio139", "gpio140", "gpio141", "gpio142", "gpio143", + "gpio144", "gpio145", "gpio146", "gpio147", "gpio148", "gpio149", + "gpio150", "gpio151", "gpio152", "gpio153", "gpio154", "gpio155", + "gpio156", "gpio157", "gpio158", "gpio159", "gpio160", "gpio161", + "gpio162", "gpio163", "gpio164", "gpio165", "gpio166", "gpio167", + "gpio168", "gpio169", "gpio170", "gpio171", "gpio172", "gpio173", + "gpio174", "gpio175", "gpio176", "gpio177", "gpio178", "gpio179", + "gpio180", "gpio181", "gpio182", "gpio183", "gpio184", "gpio185", + "gpio186", "gpio187", "gpio188", "gpio189", "gpio190", "gpio191", + "gpio192", "gpio193", "gpio194", "gpio195", "gpio196", "gpio197", + "gpio198", "gpio199", "gpio200", "gpio201", "gpio202", "gpio203", + "gpio204", "gpio205", "gpio206", "gpio207", "gpio208", "gpio209", + "gpio210", "gpio211", "gpio212", "gpio213", "gpio214", "gpio215", + "gpio216", "gpio217", "gpio218", "gpio219", "gpio220", "gpio221", + "gpio222", "gpio223", "gpio224", "gpio225", "gpio226", "gpio227", + "gpio228", "gpio229", "gpio230", "gpio231", "gpio232", "gpio233", + "gpio234", "gpio235", "gpio236", "gpio237", "gpio238", "gpio239", + "gpio240", "gpio241", "gpio242", "gpio243", "gpio244", "gpio245", + "gpio246", "gpio247", "gpio248", "gpio249", +}; + +static const char *const resout_gpio_n_groups[] = { + "gpio160", +}; + +static const char *const aoss_cti_groups[] = { + "gpio60", + "gpio61", + "gpio62", + "gpio63", +}; + +static const char *const asc_cci_groups[] = { + "gpio235", + "gpio236", +}; + +static const char *const atest_char_groups[] = { + "gpio172", "gpio184", "gpio188", "gpio164", + "gpio163", +}; + +static const char *const atest_usb_groups[] = { + "gpio39", "gpio40", "gpio41", "gpio38", + "gpio44", "gpio45", "gpio42", "gpio43", + "gpio49", "gpio50", "gpio51", "gpio48", + "gpio54", "gpio55", "gpio52", "gpio53", + "gpio65", "gpio66", "gpio46", "gpio47", + "gpio72", "gpio73", "gpio80", "gpio81", +}; + +static const char *const audio_ext_mclk0_groups[] = { + "gpio134", +}; + +static const char *const audio_ext_mclk1_groups[] = { + "gpio142", +}; + +static const char *const audio_ref_clk_groups[] = { + "gpio142", +}; + +static const char *const cam_asc_mclk4_groups[] = { + "gpio100", +}; + +static const char *const cam_mclk_groups[] = { + "gpio96", + "gpio97", + "gpio98", + "gpio99", +}; + +static const char *const cci_async_in_groups[] = { + "gpio113", "gpio112", "gpio111", +}; + +static const char *const cci_i2c_scl_groups[] = { + "gpio102", "gpio104", "gpio106", +}; + +static const char *const cci_i2c_sda_groups[] = { + "gpio101", "gpio103", "gpio105", +}; + +static const char *const cci_timer_groups[] = { + "gpio109", "gpio110", "gpio111", "gpio112", + "gpio113", +}; + +static const char *const cmu_rng_groups[] = { + "gpio48", "gpio47", "gpio46", "gpio45", +}; + +static const char *const cri_trng_groups[] = { + "gpio173", +}; + +static const char *const dbg_out_clk_groups[] = { + "gpio51", +}; + +static const char *const ddr_bist_complete_groups[] = { + "gpio57", +}; + +static const char *const ddr_bist_fail_groups[] = { + "gpio56", +}; + +static const char *const ddr_bist_start_groups[] = { + "gpio54", +}; + +static const char *const ddr_bist_stop_groups[] = { + "gpio55", +}; + +static const char *const ddr_pxi_groups[] = { + "gpio38", "gpio39", "gpio40", "gpio41", + "gpio72", "gpio73", "gpio80", "gpio81", + "gpio42", "gpio43", "gpio44", "gpio45", + "gpio46", "gpio47", "gpio48", "gpio49", + "gpio50", "gpio51", "gpio52", "gpio53", + "gpio54", "gpio55", "gpio65", "gpio66", +}; + +static const char *const edp0_hot_groups[] = { + "gpio119", +}; + +static const char *const edp0_lcd_groups[] = { + "gpio120", +}; + +static const char *const edp1_lcd_groups[] = { + "gpio115", + "gpio119", +}; + +static const char *const egpio_groups[] = { + "gpio192", "gpio193", "gpio194", "gpio195", "gpio196", "gpio197", + "gpio198", "gpio199", "gpio200", "gpio201", "gpio202", "gpio203", + "gpio204", "gpio205", "gpio206", "gpio207", "gpio208", "gpio209", + "gpio210", "gpio211", "gpio212", "gpio213", "gpio214", "gpio215", + "gpio216", "gpio217", "gpio218", "gpio219", "gpio220", "gpio221", + "gpio222", "gpio223", "gpio224", "gpio225", "gpio226", "gpio227", + "gpio228", "gpio229", "gpio230", "gpio231", "gpio232", "gpio233", + "gpio234", "gpio235", "gpio236", "gpio237", "gpio238", "gpio239", + "gpio240", "gpio241", "gpio242", "gpio243", "gpio244", +}; + +static const char *const eusb_ac_en_groups[] = { + "gpio168", "gpio177", "gpio186", "gpio69", + "gpio187", "gpio178", +}; + +static const char *const gcc_gp1_groups[] = { + "gpio71", + "gpio72", +}; + +static const char *const gcc_gp2_groups[] = { + "gpio64", + "gpio73", +}; + +static const char *const gcc_gp3_groups[] = { + "gpio74", + "gpio82", +}; + +static const char *const host2wlan_sol_groups[] = { + "gpio118", +}; + +static const char *const i2c0_s_scl_groups[] = { + "gpio7", +}; + +static const char *const i2c0_s_sda_groups[] = { + "gpio6", +}; + +static const char *const i2s0_data_groups[] = { + "gpio136", "gpio137", +}; + +static const char *const i2s0_sck_groups[] = { + "gpio135", +}; + +static const char *const i2s0_ws_groups[] = { + "gpio138", +}; + +static const char *const i2s1_data_groups[] = { + "gpio140", "gpio142", +}; + +static const char *const i2s1_sck_groups[] = { + "gpio139", +}; + +static const char *const i2s1_ws_groups[] = { + "gpio141", +}; + +static const char *const ibi_i3c_groups[] = { + "gpio0", "gpio1", "gpio4", "gpio5", "gpio32", "gpio33", + "gpio36", "gpio37", "gpio64", "gpio65", "gpio68", "gpio69", +}; + +static const char *const jitter_bist_groups[] = { + "gpio52", +}; + +static const char *const mdp_vsync_out_groups[] = { + "gpio114", "gpio114", "gpio115", "gpio115", + "gpio109", "gpio110", "gpio111", "gpio112", + "gpio113", +}; + +static const char *const mdp_vsync_e_groups[] = { + "gpio106", +}; + +static const char *const mdp_vsync_p_groups[] = { + "gpio98", +}; + +static const char *const mdp_vsync_s_groups[] = { + "gpio105", +}; + +static const char *const pcie3a_clk_groups[] = { + "gpio144", +}; + +static const char *const pcie3a_rst_n_groups[] = { + "gpio143", +}; + +static const char *const pcie3b_clk_groups[] = { + "gpio156", +}; + +static const char *const pcie4_clk_req_n_groups[] = { + "gpio147", +}; + +static const char *const pcie5_clk_req_n_groups[] = { + "gpio153", +}; + +static const char *const pcie6_clk_req_n_groups[] = { + "gpio150", +}; + +static const char *const phase_flag_groups[] = { + "gpio6", "gpio7", "gpio16", "gpio17", + "gpio18", "gpio19", "gpio20", "gpio21", + "gpio22", "gpio23", "gpio24", "gpio25", + "gpio8", "gpio26", "gpio27", "gpio163", + "gpio164", "gpio188", "gpio184", "gpio172", + "gpio186", "gpio173", "gpio76", "gpio9", + "gpio77", "gpio78", "gpio10", "gpio11", + "gpio12", "gpio13", "gpio14", "gpio15", +}; + +static const char *const pll_bist_sync_groups[] = { + "gpio28", +}; + +static const char *const pll_clk_aux_groups[] = { + "gpio35", +}; + +static const char *const pmc_oca_n_groups[] = { + "gpio249", +}; + +static const char *const pmc_uva_n_groups[] = { + "gpio248", +}; + +static const char *const prng_rosc_groups[] = { + "gpio186", "gpio188", "gpio164", "gpio163", +}; + +static const char *const qdss_cti_groups[] = { + "gpio18", "gpio19", "gpio23", "gpio27", + "gpio161", "gpio162", "gpio215", "gpio217", +}; + +static const char *const qdss_gpio_groups[] = { + "gpio104", "gpio151", "gpio227", "gpio228", + "gpio96", "gpio219", "gpio97", "gpio220", + "gpio108", "gpio231", "gpio109", "gpio232", + "gpio110", "gpio233", "gpio111", "gpio234", + "gpio112", "gpio235", "gpio113", "gpio236", + "gpio149", "gpio221", "gpio99", "gpio222", + "gpio100", "gpio223", "gpio101", "gpio224", + "gpio102", "gpio225", "gpio103", "gpio226", + "gpio152", "gpio237", "gpio107", "gpio238", +}; + +static const char *const qspi0_groups[] = { + "gpio127", "gpio132", "gpio133", "gpio128", + "gpio129", "gpio130", "gpio131", +}; + +static const char *const qup0_se0_groups[] = { + "gpio0", "gpio1", "gpio2", "gpio3", +}; + +static const char *const qup0_se1_groups[] = { + "gpio4", "gpio5", "gpio6", "gpio7", +}; + +static const char *const qup0_se2_groups[] = { + "gpio8", "gpio9", "gpio10", "gpio11", + "gpio17", "gpio18", "gpio19", +}; + +static const char *const qup0_se3_groups[] = { + "gpio12", "gpio13", "gpio14", "gpio15", + "gpio21", "gpio22", "gpio23", +}; + +static const char *const qup0_se4_groups[] = { + "gpio16", "gpio17", "gpio18", "gpio19", +}; + +static const char *const qup0_se5_groups[] = { + "gpio20", "gpio21", "gpio22", "gpio23", +}; + +static const char *const qup0_se6_groups[] = { + "gpio6", "gpio7", "gpio4", "gpio5", +}; + +static const char *const qup0_se7_groups[] = { + "gpio14", "gpio15", "gpio12", "gpio13", +}; + +static const char *const qup1_se0_groups[] = { + "gpio32", "gpio33", "gpio34", "gpio35", +}; + +static const char *const qup1_se1_groups[] = { + "gpio36", "gpio37", "gpio38", "gpio39", +}; + +static const char *const qup1_se2_groups[] = { + "gpio40", "gpio41", "gpio42", "gpio43", + "gpio49", "gpio50", "gpio51", +}; + +static const char *const qup1_se3_groups[] = { + "gpio44", "gpio45", "gpio46", "gpio47", + "gpio33", "gpio34", "gpio35", +}; + +static const char *const qup1_se4_groups[] = { + "gpio48", "gpio49", "gpio50", "gpio51", +}; + +static const char *const qup1_se5_groups[] = { + "gpio52", "gpio53", "gpio54", "gpio55", +}; + +static const char *const qup1_se6_groups[] = { + "gpio56", "gpio57", "gpio58", "gpio59", +}; + +static const char *const qup1_se7_groups[] = { + "gpio54", "gpio55", "gpio52", "gpio53", +}; + +static const char *const qup2_se0_groups[] = { + "gpio64", "gpio65", "gpio66", "gpio67", +}; + +static const char *const qup2_se1_groups[] = { + "gpio68", "gpio69", "gpio70", "gpio71", +}; + +static const char *const qup2_se2_groups[] = { + "gpio72", "gpio73", "gpio74", "gpio75", + "gpio81", "gpio82", "gpio83", +}; + +static const char *const qup2_se3_groups[] = { + "gpio76", "gpio77", "gpio78", "gpio79", + "gpio65", "gpio66", "gpio67", +}; + +static const char *const qup2_se4_groups[] = { + "gpio80", "gpio81", "gpio82", "gpio83", +}; + +static const char *const qup2_se5_groups[] = { + "gpio84", "gpio85", "gpio86", "gpio87", +}; + +static const char *const qup2_se6_groups[] = { + "gpio88", "gpio89", "gpio90", "gpio91", +}; + +static const char *const qup2_se7_groups[] = { + "gpio80", "gpio81", "gpio82", "gpio83", +}; + +static const char *const qup3_se0_groups[] = { + "gpio128", "gpio129", "gpio127", "gpio132", + "gpio130", "gpio131", "gpio133", "gpio247", +}; + +static const char *const qup3_se1_groups[] = { + "gpio40", "gpio41", "gpio42", "gpio43", + "gpio49", "gpio50", "gpio51", "gpio48", +}; + +static const char *const sd_write_protect_groups[] = { + "gpio162", +}; + +static const char *const sdc4_clk_groups[] = { + "gpio127", +}; + +static const char *const sdc4_cmd_groups[] = { + "gpio132", +}; + +static const char *const sdc4_data_groups[] = { + "gpio128", + "gpio129", + "gpio130", + "gpio131", +}; + +static const char *const smb_acok_n_groups[] = { + "gpio245", +}; + +static const char *const sys_throttle_groups[] = { + "gpio39", + "gpio94", +}; + +static const char *const tb_trig_sdc2_groups[] = { + "gpio137", +}; + +static const char *const tb_trig_sdc4_groups[] = { + "gpio133", +}; + +static const char *const tmess_prng_groups[] = { + "gpio92", "gpio93", "gpio94", "gpio95", +}; + +static const char *const tsense_pwm_groups[] = { + "gpio28", "gpio29", "gpio30", "gpio31", + "gpio34", "gpio138", "gpio139", "gpio140", +}; + +static const char *const tsense_therm_groups[] = { + "gpio141", +}; + +static const char *const usb0_dp_groups[] = { + "gpio122", +}; + +static const char *const usb0_phy_ps_groups[] = { + "gpio121", +}; + +static const char *const usb0_sbrx_groups[] = { + "gpio163", +}; + +static const char *const usb0_sbtx_groups[] = { + "gpio164", + "gpio165", +}; + +static const char *const usb0_tmu_groups[] = { + "gpio98", +}; + +static const char *const usb1_dbg_groups[] = { + "gpio105", + "gpio106", +}; + +static const char *const usb1_dp_groups[] = { + "gpio124", +}; + +static const char *const usb1_phy_ps_groups[] = { + "gpio123", +}; + +static const char *const usb1_sbrx_groups[] = { + "gpio172", +}; + +static const char *const usb1_sbtx_groups[] = { + "gpio173", + "gpio174", +}; + +static const char *const usb1_tmu_groups[] = { + "gpio98", +}; + +static const char *const usb2_dp_groups[] = { + "gpio126", +}; + +static const char *const usb2_phy_ps_groups[] = { + "gpio125", +}; + +static const char *const usb2_sbrx_groups[] = { + "gpio181", +}; + +static const char *const usb2_sbtx_groups[] = { + "gpio182", + "gpio183", +}; + +static const char *const usb2_tmu_groups[] = { + "gpio98", +}; + +static const char *const vsense_trigger_mirnat_groups[] = { + "gpio38", +}; + +static const char *const wcn_sw_groups[] = { + "gpio221", +}; + +static const char *const wcn_sw_ctrl_groups[] = { + "gpio214", +}; + +static const struct pinfunction glymur_functions[] = { + MSM_PIN_FUNCTION(gpio), + MSM_PIN_FUNCTION(resout_gpio_n), + MSM_PIN_FUNCTION(aoss_cti), + MSM_PIN_FUNCTION(asc_cci), + MSM_PIN_FUNCTION(atest_char), + MSM_PIN_FUNCTION(atest_usb), + MSM_PIN_FUNCTION(audio_ext_mclk0), + MSM_PIN_FUNCTION(audio_ext_mclk1), + MSM_PIN_FUNCTION(audio_ref_clk), + MSM_PIN_FUNCTION(cam_asc_mclk4), + MSM_PIN_FUNCTION(cam_mclk), + MSM_PIN_FUNCTION(cci_async_in), + MSM_PIN_FUNCTION(cci_i2c_scl), + MSM_PIN_FUNCTION(cci_i2c_sda), + MSM_PIN_FUNCTION(cci_timer), + MSM_PIN_FUNCTION(cmu_rng), + MSM_PIN_FUNCTION(cri_trng), + MSM_PIN_FUNCTION(dbg_out_clk), + MSM_PIN_FUNCTION(ddr_bist_complete), + MSM_PIN_FUNCTION(ddr_bist_fail), + MSM_PIN_FUNCTION(ddr_bist_start), + MSM_PIN_FUNCTION(ddr_bist_stop), + MSM_PIN_FUNCTION(ddr_pxi), + MSM_PIN_FUNCTION(edp0_hot), + MSM_PIN_FUNCTION(edp0_lcd), + MSM_PIN_FUNCTION(edp1_lcd), + MSM_PIN_FUNCTION(egpio), + MSM_PIN_FUNCTION(eusb_ac_en), + MSM_PIN_FUNCTION(gcc_gp1), + MSM_PIN_FUNCTION(gcc_gp2), + MSM_PIN_FUNCTION(gcc_gp3), + MSM_PIN_FUNCTION(host2wlan_sol), + MSM_PIN_FUNCTION(i2c0_s_scl), + MSM_PIN_FUNCTION(i2c0_s_sda), + MSM_PIN_FUNCTION(i2s0_data), + MSM_PIN_FUNCTION(i2s0_sck), + MSM_PIN_FUNCTION(i2s0_ws), + MSM_PIN_FUNCTION(i2s1_data), + MSM_PIN_FUNCTION(i2s1_sck), + MSM_PIN_FUNCTION(i2s1_ws), + MSM_PIN_FUNCTION(ibi_i3c), + MSM_PIN_FUNCTION(jitter_bist), + MSM_PIN_FUNCTION(mdp_vsync_out), + MSM_PIN_FUNCTION(mdp_vsync_e), + MSM_PIN_FUNCTION(mdp_vsync_p), + MSM_PIN_FUNCTION(mdp_vsync_s), + MSM_PIN_FUNCTION(pcie3a_clk), + MSM_PIN_FUNCTION(pcie3a_rst_n), + MSM_PIN_FUNCTION(pcie3b_clk), + MSM_PIN_FUNCTION(pcie4_clk_req_n), + MSM_PIN_FUNCTION(pcie5_clk_req_n), + MSM_PIN_FUNCTION(pcie6_clk_req_n), + MSM_PIN_FUNCTION(phase_flag), + MSM_PIN_FUNCTION(pll_bist_sync), + MSM_PIN_FUNCTION(pll_clk_aux), + MSM_PIN_FUNCTION(pmc_oca_n), + MSM_PIN_FUNCTION(pmc_uva_n), + MSM_PIN_FUNCTION(prng_rosc), + MSM_PIN_FUNCTION(qdss_cti), + MSM_PIN_FUNCTION(qdss_gpio), + MSM_PIN_FUNCTION(qspi0), + MSM_PIN_FUNCTION(qup0_se0), + MSM_PIN_FUNCTION(qup0_se1), + MSM_PIN_FUNCTION(qup0_se2), + MSM_PIN_FUNCTION(qup0_se3), + MSM_PIN_FUNCTION(qup0_se4), + MSM_PIN_FUNCTION(qup0_se5), + MSM_PIN_FUNCTION(qup0_se6), + MSM_PIN_FUNCTION(qup0_se7), + MSM_PIN_FUNCTION(qup1_se0), + MSM_PIN_FUNCTION(qup1_se1), + MSM_PIN_FUNCTION(qup1_se2), + MSM_PIN_FUNCTION(qup1_se3), + MSM_PIN_FUNCTION(qup1_se4), + MSM_PIN_FUNCTION(qup1_se5), + MSM_PIN_FUNCTION(qup1_se6), + MSM_PIN_FUNCTION(qup1_se7), + MSM_PIN_FUNCTION(qup2_se0), + MSM_PIN_FUNCTION(qup2_se1), + MSM_PIN_FUNCTION(qup2_se2), + MSM_PIN_FUNCTION(qup2_se3), + MSM_PIN_FUNCTION(qup2_se4), + MSM_PIN_FUNCTION(qup2_se5), + MSM_PIN_FUNCTION(qup2_se6), + MSM_PIN_FUNCTION(qup2_se7), + MSM_PIN_FUNCTION(qup3_se0), + MSM_PIN_FUNCTION(qup3_se1), + MSM_PIN_FUNCTION(sd_write_protect), + MSM_PIN_FUNCTION(sdc4_clk), + MSM_PIN_FUNCTION(sdc4_cmd), + MSM_PIN_FUNCTION(sdc4_data), + MSM_PIN_FUNCTION(smb_acok_n), + MSM_PIN_FUNCTION(sys_throttle), + MSM_PIN_FUNCTION(tb_trig_sdc2), + MSM_PIN_FUNCTION(tb_trig_sdc4), + MSM_PIN_FUNCTION(tmess_prng), + MSM_PIN_FUNCTION(tsense_pwm), + MSM_PIN_FUNCTION(tsense_therm), + MSM_PIN_FUNCTION(usb0_dp), + MSM_PIN_FUNCTION(usb0_phy_ps), + MSM_PIN_FUNCTION(usb0_sbrx), + MSM_PIN_FUNCTION(usb0_sbtx), + MSM_PIN_FUNCTION(usb0_tmu), + MSM_PIN_FUNCTION(usb1_dbg), + MSM_PIN_FUNCTION(usb1_dp), + MSM_PIN_FUNCTION(usb1_phy_ps), + MSM_PIN_FUNCTION(usb1_sbrx), + MSM_PIN_FUNCTION(usb1_sbtx), + MSM_PIN_FUNCTION(usb1_tmu), + MSM_PIN_FUNCTION(usb2_dp), + MSM_PIN_FUNCTION(usb2_phy_ps), + MSM_PIN_FUNCTION(usb2_sbrx), + MSM_PIN_FUNCTION(usb2_sbtx), + MSM_PIN_FUNCTION(usb2_tmu), + MSM_PIN_FUNCTION(vsense_trigger_mirnat), + MSM_PIN_FUNCTION(wcn_sw), + MSM_PIN_FUNCTION(wcn_sw_ctrl), +}; + +static const struct msm_pingroup glymur_groups[] = { + [0] = PINGROUP(0, qup0_se0, ibi_i3c, _, _, _, _, _, _, _, _, _), + [1] = PINGROUP(1, qup0_se0, ibi_i3c, _, _, _, _, _, _, _, _, _), + [2] = PINGROUP(2, qup0_se0, _, _, _, _, _, _, _, _, _, _), + [3] = PINGROUP(3, qup0_se0, _, _, _, _, _, _, _, _, _, _), + [4] = PINGROUP(4, qup0_se1, qup0_se6, ibi_i3c, _, _, _, _, _, _, _, _), + [5] = PINGROUP(5, qup0_se1, qup0_se6, ibi_i3c, _, _, _, _, _, _, _, _), + [6] = PINGROUP(6, qup0_se1, qup0_se6, i2c0_s_sda, phase_flag, _, _, _, _, _, _, _), + [7] = PINGROUP(7, qup0_se1, qup0_se6, i2c0_s_scl, phase_flag, _, _, _, _, _, _, _), + [8] = PINGROUP(8, qup0_se2, phase_flag, _, _, _, _, _, _, _, _, _), + [9] = PINGROUP(9, qup0_se2, phase_flag, _, _, _, _, _, _, _, _, _), + [10] = PINGROUP(10, qup0_se2, phase_flag, _, _, _, _, _, _, _, _, _), + [11] = PINGROUP(11, qup0_se2, phase_flag, _, _, _, _, _, _, _, _, _), + [12] = PINGROUP(12, qup0_se3, qup0_se7, phase_flag, _, _, _, _, _, _, _, _), + [13] = PINGROUP(13, qup0_se3, qup0_se7, phase_flag, _, _, _, _, _, _, _, _), + [14] = PINGROUP(14, qup0_se3, qup0_se7, phase_flag, _, _, _, _, _, _, _, _), + [15] = PINGROUP(15, qup0_se3, qup0_se7, phase_flag, _, _, _, _, _, _, _, _), + [16] = PINGROUP(16, qup0_se4, phase_flag, _, _, _, _, _, _, _, _, _), + [17] = PINGROUP(17, qup0_se4, qup0_se2, phase_flag, _, _, _, _, _, _, _, _), + [18] = PINGROUP(18, qup0_se4, qup0_se2, phase_flag, _, qdss_cti, _, _, _, _, _, _), + [19] = PINGROUP(19, qup0_se4, qup0_se2, phase_flag, _, qdss_cti, _, _, _, _, _, _), + [20] = PINGROUP(20, qup0_se5, _, phase_flag, _, _, _, _, _, _, _, _), + [21] = PINGROUP(21, qup0_se5, qup0_se3, _, phase_flag, _, _, _, _, _, _, _), + [22] = PINGROUP(22, qup0_se5, qup0_se3, _, phase_flag, _, _, _, _, _, _, _), + [23] = PINGROUP(23, qup0_se5, qup0_se3, phase_flag, _, qdss_cti, _, _, _, _, _, _), + [24] = PINGROUP(24, phase_flag, _, _, _, _, _, _, _, _, _, _), + [25] = PINGROUP(25, phase_flag, _, _, _, _, _, _, _, _, _, _), + [26] = PINGROUP(26, phase_flag, _, _, _, _, _, _, _, _, _, _), + [27] = PINGROUP(27, phase_flag, _, qdss_cti, _, _, _, _, _, _, _, _), + [28] = PINGROUP(28, pll_bist_sync, tsense_pwm, _, _, _, _, _, _, _, _, _), + [29] = PINGROUP(29, tsense_pwm, _, _, _, _, _, _, _, _, _, _), + [30] = PINGROUP(30, tsense_pwm, _, _, _, _, _, _, _, _, _, _), + [31] = PINGROUP(31, tsense_pwm, _, _, _, _, _, _, _, _, _, _), + [32] = PINGROUP(32, qup1_se0, ibi_i3c, _, _, _, _, _, _, _, _, _), + [33] = PINGROUP(33, qup1_se0, ibi_i3c, qup1_se3, _, _, _, _, _, _, _, _), + [34] = PINGROUP(34, qup1_se0, qup1_se3, tsense_pwm, _, _, _, _, _, _, _, _), + [35] = PINGROUP(35, qup1_se0, qup1_se3, pll_clk_aux, _, _, _, _, _, _, _, _), + [36] = PINGROUP(36, qup1_se1, ibi_i3c, _, _, _, _, _, _, _, _, _), + [37] = PINGROUP(37, qup1_se1, ibi_i3c, _, _, _, _, _, _, _, _, _), + [38] = PINGROUP(38, qup1_se1, atest_usb, ddr_pxi, vsense_trigger_mirnat, _, _, _, _, + _, _, _), + [39] = PINGROUP(39, qup1_se1, sys_throttle, _, atest_usb, ddr_pxi, _, _, _, _, _, _), + [40] = PINGROUP(40, qup1_se2, qup3_se1, _, atest_usb, ddr_pxi, _, _, _, _, _, _), + [41] = PINGROUP(41, qup1_se2, qup3_se1, qup3_se0, atest_usb, ddr_pxi, _, _, _, _, + _, _), + [42] = PINGROUP(42, qup1_se2, qup3_se1, qup0_se1, atest_usb, ddr_pxi, _, _, _, _, + _, _), + [43] = PINGROUP(43, qup1_se2, qup3_se1, _, atest_usb, ddr_pxi, _, _, _, _, _, _), + [44] = PINGROUP(44, qup1_se3, _, atest_usb, ddr_pxi, _, _, _, _, _, _, _), + [45] = PINGROUP(45, qup1_se3, cmu_rng, _, atest_usb, ddr_pxi, _, _, _, _, _, _), + [46] = PINGROUP(46, qup1_se3, cmu_rng, _, atest_usb, ddr_pxi, _, _, _, _, _, _), + [47] = PINGROUP(47, qup1_se3, cmu_rng, _, atest_usb, ddr_pxi, _, _, _, _, _, _), + [48] = PINGROUP(48, qup1_se4, qup3_se1, cmu_rng, _, atest_usb, ddr_pxi, _, _, _, + _, _), + [49] = PINGROUP(49, qup1_se4, qup1_se2, qup3_se1, _, atest_usb, ddr_pxi, _, _, + _, _, _), + [50] = PINGROUP(50, qup1_se4, qup1_se2, qup3_se1, _, atest_usb, ddr_pxi, _, _, + _, _, _), + [51] = PINGROUP(51, qup1_se4, qup1_se2, qup3_se1, dbg_out_clk, atest_usb, + ddr_pxi, _, _, _, _, _), + [52] = PINGROUP(52, qup1_se5, qup1_se7, jitter_bist, atest_usb, ddr_pxi, _, _, _, + _, _, _), + [53] = PINGROUP(53, qup1_se5, qup1_se7, _, atest_usb, ddr_pxi, _, _, _, _, _, _), + [54] = PINGROUP(54, qup1_se5, qup1_se7, ddr_bist_start, atest_usb, ddr_pxi, _, _, + _, _, _, _), + [55] = PINGROUP(55, qup1_se5, qup1_se7, ddr_bist_stop, atest_usb, ddr_pxi, _, _, + _, _, _, _), + [56] = PINGROUP(56, qup1_se6, ddr_bist_fail, _, _, _, _, _, _, _, _, _), + [57] = PINGROUP(57, qup1_se6, ddr_bist_complete, _, _, _, _, _, _, _, _, _), + [58] = PINGROUP(58, qup1_se6, _, _, _, _, _, _, _, _, _, _), + [59] = PINGROUP(59, qup1_se6, _, _, _, _, _, _, _, _, _, _), + [60] = PINGROUP(60, aoss_cti, _, _, _, _, _, _, _, _, _, _), + [61] = PINGROUP(61, aoss_cti, _, _, _, _, _, _, _, _, _, _), + [62] = PINGROUP(62, aoss_cti, _, _, _, _, _, _, _, _, _, _), + [63] = PINGROUP(63, aoss_cti, _, _, _, _, _, _, _, _, _, _), + [64] = PINGROUP(64, qup2_se0, ibi_i3c, gcc_gp2, _, _, _, _, _, _, _, _), + [65] = PINGROUP(65, qup2_se0, qup2_se3, ibi_i3c, atest_usb, ddr_pxi, _, _, _, _, + _, _), + [66] = PINGROUP(66, qup2_se0, qup2_se3, atest_usb, ddr_pxi, _, _, _, _, _, _, _), + [67] = PINGROUP(67, qup2_se0, qup2_se3, _, _, _, _, _, _, _, _, _), + [68] = PINGROUP(68, qup2_se1, ibi_i3c, _, _, _, _, _, _, _, _, _), + [69] = PINGROUP(69, qup2_se1, ibi_i3c, _, _, _, _, _, _, _, _, _), + [70] = PINGROUP(70, qup2_se1, _, _, _, _, _, _, _, _, _, _), + [71] = PINGROUP(71, qup2_se1, gcc_gp1, _, _, _, _, _, _, _, _, _), + [72] = PINGROUP(72, qup2_se2, gcc_gp1, atest_usb, ddr_pxi, _, _, _, _, _, _, _), + [73] = PINGROUP(73, qup2_se2, gcc_gp2, atest_usb, ddr_pxi, _, _, _, _, _, _, _), + [74] = PINGROUP(74, qup2_se2, gcc_gp3, _, _, _, _, _, _, _, _, _), + [75] = PINGROUP(75, qup2_se2, _, _, _, _, _, _, _, _, _, _), + [76] = PINGROUP(76, qup2_se3, phase_flag, _, _, _, _, _, _, _, _, _), + [77] = PINGROUP(77, qup2_se3, phase_flag, _, _, _, _, _, _, _, _, _), + [78] = PINGROUP(78, qup2_se3, phase_flag, _, _, _, _, _, _, _, _, _), + [79] = PINGROUP(79, qup2_se3, _, _, _, _, _, _, _, _, _, _), + [80] = PINGROUP(80, qup2_se4, qup2_se7, atest_usb, ddr_pxi, _, _, _, _, _, _, _), + [81] = PINGROUP(81, qup2_se4, qup2_se2, qup2_se7, atest_usb, ddr_pxi, _, _, _, + _, _, _), + [82] = PINGROUP(82, qup2_se4, qup2_se2, qup2_se7, gcc_gp3, _, _, _, _, _, _, _), + [83] = PINGROUP(83, qup2_se4, qup2_se2, qup2_se7, _, _, _, _, _, _, _, _), + [84] = PINGROUP(84, qup2_se5, _, _, _, _, _, _, _, _, _, _), + [85] = PINGROUP(85, qup2_se5, _, _, _, _, _, _, _, _, _, _), + [86] = PINGROUP(86, qup2_se5, _, _, _, _, _, _, _, _, _, _), + [87] = PINGROUP(87, qup2_se5, _, _, _, _, _, _, _, _, _, _), + [88] = PINGROUP(88, qup2_se6, _, _, _, _, _, _, _, _, _, _), + [89] = PINGROUP(89, qup2_se6, _, _, _, _, _, _, _, _, _, _), + [90] = PINGROUP(90, qup2_se6, _, _, _, _, _, _, _, _, _, _), + [91] = PINGROUP(91, qup2_se6, _, _, _, _, _, _, _, _, _, _), + [92] = PINGROUP(92, tmess_prng, _, _, _, _, _, _, _, _, _, _), + [93] = PINGROUP(93, tmess_prng, _, _, _, _, _, _, _, _, _, _), + [94] = PINGROUP(94, sys_throttle, tmess_prng, _, _, _, _, _, _, _, _, _), + [95] = PINGROUP(95, tmess_prng, _, _, _, _, _, _, _, _, _, _), + [96] = PINGROUP(96, cam_mclk, qdss_gpio, _, _, _, _, _, _, _, _, _), + [97] = PINGROUP(97, cam_mclk, qdss_gpio, _, _, _, _, _, _, _, _, _), + [98] = PINGROUP(98, cam_mclk, mdp_vsync_p, usb0_tmu, usb1_tmu, usb2_tmu, _, _, _, _, _, _), + [99] = PINGROUP(99, cam_mclk, qdss_gpio, _, _, _, _, _, _, _, _, _), + [100] = PINGROUP(100, cam_asc_mclk4, qdss_gpio, _, _, _, _, _, _, _, _, _), + [101] = PINGROUP(101, cci_i2c_sda, qdss_gpio, _, _, _, _, _, _, _, _, _), + [102] = PINGROUP(102, cci_i2c_scl, qdss_gpio, _, _, _, _, _, _, _, _, _), + [103] = PINGROUP(103, cci_i2c_sda, qdss_gpio, _, _, _, _, _, _, _, _, _), + [104] = PINGROUP(104, cci_i2c_scl, qdss_gpio, _, _, _, _, _, _, _, _, _), + [105] = PINGROUP(105, cci_i2c_sda, mdp_vsync_s, usb1_dbg, _, _, _, _, _, _, _, _), + [106] = PINGROUP(106, cci_i2c_scl, mdp_vsync_e, usb1_dbg, _, _, _, _, _, _, _, _), + [107] = PINGROUP(107, qdss_gpio, _, _, _, _, _, _, _, _, _, _), + [108] = PINGROUP(108, qdss_gpio, _, _, _, _, _, _, _, _, _, _), + [109] = PINGROUP(109, cci_timer, mdp_vsync_out, qdss_gpio, _, _, _, _, _, _, _, _), + [110] = PINGROUP(110, cci_timer, mdp_vsync_out, qdss_gpio, _, _, _, _, _, _, _, _), + [111] = PINGROUP(111, cci_timer, cci_async_in, mdp_vsync_out, qdss_gpio, _, _, _, _, + _, _, _), + [112] = PINGROUP(112, cci_timer, cci_async_in, mdp_vsync_out, qdss_gpio, _, _, _, _, + _, _, _), + [113] = PINGROUP(113, cci_timer, cci_async_in, mdp_vsync_out, qdss_gpio, _, _, _, _, + _, _, _), + [114] = PINGROUP(114, mdp_vsync_out, mdp_vsync_out, _, _, _, _, _, _, _, _, _), + [115] = PINGROUP(115, mdp_vsync_out, mdp_vsync_out, edp1_lcd, _, _, _, _, _, _, _, _), + [116] = PINGROUP(116, _, _, _, _, _, _, _, _, _, _, _), + [117] = PINGROUP(117, _, _, _, _, _, _, _, _, _, _, _), + [118] = PINGROUP(118, host2wlan_sol, _, _, _, _, _, _, _, _, _, _), + [119] = PINGROUP(119, edp0_hot, edp1_lcd, _, _, _, _, _, _, _, _, _), + [120] = PINGROUP(120, edp0_lcd, _, _, _, _, _, _, _, _, _, _), + [121] = PINGROUP(121, usb0_phy_ps, _, _, _, _, _, _, _, _, _, _), + [122] = PINGROUP(122, usb0_dp, _, _, _, _, _, _, _, _, _, _), + [123] = PINGROUP(123, usb1_phy_ps, _, _, _, _, _, _, _, _, _, _), + [124] = PINGROUP(124, usb1_dp, _, _, _, _, _, _, _, _, _, _), + [125] = PINGROUP(125, usb2_phy_ps, _, _, _, _, _, _, _, _, _, _), + [126] = PINGROUP(126, usb2_dp, _, _, _, _, _, _, _, _, _, _), + [127] = PINGROUP(127, qspi0, sdc4_clk, qup3_se0, _, _, _, _, _, _, _, _), + [128] = PINGROUP(128, qspi0, sdc4_data, qup3_se0, _, _, _, _, _, _, _, _), + [129] = PINGROUP(129, qspi0, sdc4_data, qup3_se0, _, _, _, _, _, _, _, _), + [130] = PINGROUP(130, qspi0, sdc4_data, qup3_se0, _, _, _, _, _, _, _, _), + [131] = PINGROUP(131, qspi0, sdc4_data, qup3_se0, _, _, _, _, _, _, _, _), + [132] = PINGROUP(132, qspi0, sdc4_cmd, qup3_se0, _, _, _, _, _, _, _, _), + [133] = PINGROUP(133, qspi0, tb_trig_sdc4, qup3_se0, _, _, _, _, _, _, _, _), + [134] = PINGROUP(134, audio_ext_mclk0, _, _, _, _, _, _, _, _, _, _), + [135] = PINGROUP(135, i2s0_sck, _, _, _, _, _, _, _, _, _, _), + [136] = PINGROUP(136, i2s0_data, _, _, _, _, _, _, _, _, _, _), + [137] = PINGROUP(137, i2s0_data, tb_trig_sdc2, _, _, _, _, _, _, _, _, _), + [138] = PINGROUP(138, i2s0_ws, tsense_pwm, _, _, _, _, _, _, _, _, _), + [139] = PINGROUP(139, i2s1_sck, tsense_pwm, _, _, _, _, _, _, _, _, _), + [140] = PINGROUP(140, i2s1_data, tsense_pwm, _, _, _, _, _, _, _, _, _), + [141] = PINGROUP(141, i2s1_ws, tsense_therm, _, _, _, _, _, _, _, _, _), + [142] = PINGROUP(142, i2s1_data, audio_ext_mclk1, audio_ref_clk, _, _, _, _, _, _, _, _), + [143] = PINGROUP(143, pcie3a_rst_n, _, _, _, _, _, _, _, _, _, _), + [144] = PINGROUP(144, pcie3a_clk, _, _, _, _, _, _, _, _, _, _), + [145] = PINGROUP(145, _, _, _, _, _, _, _, _, _, _, _), + [146] = PINGROUP(146, _, _, _, _, _, _, _, _, _, _, _), + [147] = PINGROUP(147, pcie4_clk_req_n, _, _, _, _, _, _, _, _, _, _), + [148] = PINGROUP(148, _, _, _, _, _, _, _, _, _, _, _), + [149] = PINGROUP(149, qdss_gpio, _, _, _, _, _, _, _, _, _, _), + [150] = PINGROUP(150, pcie6_clk_req_n, _, _, _, _, _, _, _, _, _, _), + [151] = PINGROUP(151, qdss_gpio, _, _, _, _, _, _, _, _, _, _), + [152] = PINGROUP(152, qdss_gpio, _, _, _, _, _, _, _, _, _, _), + [153] = PINGROUP(153, pcie5_clk_req_n, _, _, _, _, _, _, _, _, _, _), + [154] = PINGROUP(154, _, _, _, _, _, _, _, _, _, _, _), + [155] = PINGROUP(155, _, _, _, _, _, _, _, _, _, _, _), + [156] = PINGROUP(156, pcie3b_clk, _, _, _, _, _, _, _, _, _, _), + [157] = PINGROUP(157, _, _, _, _, _, _, _, _, _, _, _), + [158] = PINGROUP(158, _, _, _, _, _, _, _, _, _, _, _), + [159] = PINGROUP(159, _, _, _, _, _, _, _, _, _, _, _), + [160] = PINGROUP(160, resout_gpio_n, _, _, _, _, _, _, _, _, _, _), + [161] = PINGROUP(161, qdss_cti, _, _, _, _, _, _, _, _, _, _), + [162] = PINGROUP(162, sd_write_protect, qdss_cti, _, _, _, _, _, _, _, _, _), + [163] = PINGROUP(163, usb0_sbrx, prng_rosc, phase_flag, _, atest_char, _, _, _, + _, _, _), + [164] = PINGROUP(164, usb0_sbtx, prng_rosc, phase_flag, _, atest_char, _, _, _, _, _, + _), + [165] = PINGROUP(165, usb0_sbtx, _, _, _, _, _, _, _, _, _, _), + [166] = PINGROUP(166, _, _, _, _, _, _, _, _, _, _, _), + [167] = PINGROUP(167, _, _, _, _, _, _, _, _, _, _, _), + [168] = PINGROUP(168, eusb_ac_en, _, _, _, _, _, _, _, _, _, _), + [169] = PINGROUP(169, eusb_ac_en, _, _, _, _, _, _, _, _, _, _), + [170] = PINGROUP(170, _, _, _, _, _, _, _, _, _, _, _), + [171] = PINGROUP(171, _, _, _, _, _, _, _, _, _, _, _), + [172] = PINGROUP(172, usb1_sbrx, phase_flag, _, atest_char, _, _, _, _, _, _, _), + [173] = PINGROUP(173, usb1_sbtx, cri_trng, phase_flag, _, _, _, _, _, _, _, _), + [174] = PINGROUP(174, usb1_sbtx, _, _, _, _, _, _, _, _, _, _), + [175] = PINGROUP(175, _, _, _, _, _, _, _, _, _, _, _), + [176] = PINGROUP(176, _, _, _, _, _, _, _, _, _, _, _), + [177] = PINGROUP(177, eusb_ac_en, _, _, _, _, _, _, _, _, _, _), + [178] = PINGROUP(178, eusb_ac_en, _, _, _, _, _, _, _, _, _, _), + [179] = PINGROUP(179, _, _, _, _, _, _, _, _, _, _, _), + [180] = PINGROUP(180, _, _, _, _, _, _, _, _, _, _, _), + [181] = PINGROUP(181, usb2_sbrx, _, _, _, _, _, _, _, _, _, _), + [182] = PINGROUP(182, usb2_sbtx, _, _, _, _, _, _, _, _, _, _), + [183] = PINGROUP(183, usb2_sbtx, _, _, _, _, _, _, _, _, _, _), + [184] = PINGROUP(184, phase_flag, _, atest_char, _, _, _, _, _, _, _, _), + [185] = PINGROUP(185, _, _, _, _, _, _, _, _, _, _, _), + [186] = PINGROUP(186, eusb_ac_en, prng_rosc, phase_flag, _, _, _, _, _, _, _, _), + [187] = PINGROUP(187, eusb_ac_en, _, _, _, _, _, _, _, _, _, _), + [188] = PINGROUP(188, prng_rosc, phase_flag, _, atest_char, _, _, _, _, _, _, _), + [189] = PINGROUP(189, _, _, _, _, _, _, _, _, _, _, _), + [190] = PINGROUP(190, _, _, _, _, _, _, _, _, _, _, _), + [191] = PINGROUP(191, _, _, _, _, _, _, _, _, _, _, _), + [192] = PINGROUP(192, _, _, _, _, _, _, _, _, _, _, egpio), + [193] = PINGROUP(193, _, _, _, _, _, _, _, _, _, _, egpio), + [194] = PINGROUP(194, _, _, _, _, _, _, _, _, _, _, egpio), + [195] = PINGROUP(195, _, _, _, _, _, _, _, _, _, _, egpio), + [196] = PINGROUP(196, _, _, _, _, _, _, _, _, _, _, egpio), + [197] = PINGROUP(197, _, _, _, _, _, _, _, _, _, _, egpio), + [198] = PINGROUP(198, _, _, _, _, _, _, _, _, _, _, egpio), + [199] = PINGROUP(199, _, _, _, _, _, _, _, _, _, _, egpio), + [200] = PINGROUP(200, _, _, _, _, _, _, _, _, _, _, egpio), + [201] = PINGROUP(201, _, _, _, _, _, _, _, _, _, _, egpio), + [202] = PINGROUP(202, _, _, _, _, _, _, _, _, _, _, egpio), + [203] = PINGROUP(203, _, _, _, _, _, _, _, _, _, _, egpio), + [204] = PINGROUP(204, _, _, _, _, _, _, _, _, _, _, egpio), + [205] = PINGROUP(205, _, _, _, _, _, _, _, _, _, _, egpio), + [206] = PINGROUP(206, _, _, _, _, _, _, _, _, _, _, egpio), + [207] = PINGROUP(207, _, _, _, _, _, _, _, _, _, _, egpio), + [208] = PINGROUP(208, _, _, _, _, _, _, _, _, _, _, egpio), + [209] = PINGROUP(209, _, _, _, _, _, _, _, _, _, _, egpio), + [210] = PINGROUP(210, _, _, _, _, _, _, _, _, _, _, egpio), + [211] = PINGROUP(211, _, _, _, _, _, _, _, _, _, _, egpio), + [212] = PINGROUP(212, _, _, _, _, _, _, _, _, _, _, egpio), + [213] = PINGROUP(213, _, _, _, _, _, _, _, _, _, _, egpio), + [214] = PINGROUP(214, wcn_sw_ctrl, _, _, _, _, _, _, _, _, _, egpio), + [215] = PINGROUP(215, _, qdss_cti, _, _, _, _, _, _, _, _, egpio), + [216] = PINGROUP(216, _, _, _, _, _, _, _, _, _, _, egpio), + [217] = PINGROUP(217, _, qdss_cti, _, _, _, _, _, _, _, _, egpio), + [218] = PINGROUP(218, _, _, _, _, _, _, _, _, _, _, egpio), + [219] = PINGROUP(219, _, qdss_gpio, _, _, _, _, _, _, _, _, egpio), + [220] = PINGROUP(220, _, qdss_gpio, _, _, _, _, _, _, _, _, egpio), + [221] = PINGROUP(221, wcn_sw, _, qdss_gpio, _, _, _, _, _, _, _, egpio), + [222] = PINGROUP(222, _, qdss_gpio, _, _, _, _, _, _, _, _, egpio), + [223] = PINGROUP(223, _, qdss_gpio, _, _, _, _, _, _, _, _, egpio), + [224] = PINGROUP(224, _, qdss_gpio, _, _, _, _, _, _, _, _, egpio), + [225] = PINGROUP(225, _, qdss_gpio, _, _, _, _, _, _, _, _, egpio), + [226] = PINGROUP(226, _, qdss_gpio, _, _, _, _, _, _, _, _, egpio), + [227] = PINGROUP(227, _, qdss_gpio, _, _, _, _, _, _, _, _, egpio), + [228] = PINGROUP(228, _, qdss_gpio, _, _, _, _, _, _, _, _, egpio), + [229] = PINGROUP(229, _, _, _, _, _, _, _, _, _, _, egpio), + [230] = PINGROUP(230, _, _, _, _, _, _, _, _, _, _, egpio), + [231] = PINGROUP(231, qdss_gpio, _, _, _, _, _, _, _, _, _, egpio), + [232] = PINGROUP(232, qdss_gpio, _, _, _, _, _, _, _, _, _, egpio), + [233] = PINGROUP(233, qdss_gpio, _, _, _, _, _, _, _, _, _, egpio), + [234] = PINGROUP(234, qdss_gpio, _, _, _, _, _, _, _, _, _, egpio), + [235] = PINGROUP(235, asc_cci, qdss_gpio, _, _, _, _, _, _, _, _, egpio), + [236] = PINGROUP(236, asc_cci, qdss_gpio, _, _, _, _, _, _, _, _, egpio), + [237] = PINGROUP(237, qdss_gpio, _, _, _, _, _, _, _, _, _, egpio), + [238] = PINGROUP(238, qdss_gpio, _, _, _, _, _, _, _, _, _, egpio), + [239] = PINGROUP(239, _, _, _, _, _, _, _, _, _, _, egpio), + [240] = PINGROUP(240, _, _, _, _, _, _, _, _, _, _, egpio), + [241] = PINGROUP(241, _, _, _, _, _, _, _, _, _, _, egpio), + [242] = PINGROUP(242, _, _, _, _, _, _, _, _, _, _, egpio), + [243] = PINGROUP(243, _, _, _, _, _, _, _, _, _, _, egpio), + [244] = PINGROUP(244, _, _, _, _, _, _, _, _, _, _, egpio), + [245] = PINGROUP(245, smb_acok_n, _, _, _, _, _, _, _, _, _, _), + [246] = PINGROUP(246, _, _, _, _, _, _, _, _, _, _, _), + [247] = PINGROUP(247, qup3_se0, _, _, _, _, _, _, _, _, _, _), + [248] = PINGROUP(248, pmc_uva_n, _, _, _, _, _, _, _, _, _, _), + [249] = PINGROUP(249, pmc_oca_n, _, _, _, _, _, _, _, _, _, _), + [250] = UFS_RESET(ufs_reset, 0x104004, 0x105000), + [251] = SDC_QDSD_PINGROUP(sdc2_clk, 0xff000, 14, 6), + [252] = SDC_QDSD_PINGROUP(sdc2_cmd, 0xff000, 11, 3), + [253] = SDC_QDSD_PINGROUP(sdc2_data, 0xff000, 9, 0), +}; + +static const struct msm_gpio_wakeirq_map glymur_pdc_map[] = { + { 0, 116 }, { 2, 114 }, { 3, 115 }, { 4, 175 }, { 5, 176 }, + { 7, 111 }, { 11, 129 }, { 13, 130 }, { 15, 112 }, { 19, 113 }, + { 23, 187 }, { 27, 188 }, { 28, 121 }, { 29, 122 }, { 30, 136 }, + { 31, 203 }, { 32, 189 }, { 34, 174 }, { 35, 190 }, { 36, 191 }, + { 39, 124 }, { 43, 192 }, { 47, 193 }, { 51, 123 }, { 53, 133 }, + { 55, 125 }, { 59, 131 }, { 64, 134 }, { 65, 150 }, { 66, 186 }, + { 67, 132 }, { 68, 195 }, { 71, 135 }, { 75, 196 }, { 79, 197 }, + { 83, 198 }, { 84, 181 }, { 85, 199 }, { 87, 200 }, { 91, 201 }, + { 92, 182 }, { 93, 183 }, { 94, 184 }, { 95, 185 }, { 98, 202 }, + { 105, 157 }, { 113, 128 }, { 121, 117 }, { 123, 118 }, { 125, 119 }, + { 129, 120 }, { 131, 126 }, { 132, 160 }, { 133, 194 }, { 134, 127 }, + { 141, 137 }, { 143, 159 }, { 144, 138 }, { 145, 139 }, { 147, 140 }, + { 148, 141 }, { 150, 146 }, { 151, 147 }, { 153, 148 }, { 154, 144 }, + { 156, 149 }, { 157, 151 }, { 163, 142 }, { 172, 143 }, { 181, 145 }, + { 193, 161 }, { 196, 152 }, { 203, 177 }, { 208, 178 }, { 215, 162 }, + { 217, 153 }, { 220, 154 }, { 221, 155 }, { 228, 179 }, { 230, 180 }, + { 232, 206 }, { 234, 172 }, { 235, 173 }, { 242, 158 }, { 244, 156 }, +}; + +static const struct msm_pinctrl_soc_data glymur_tlmm = { + .pins = glymur_pins, + .npins = ARRAY_SIZE(glymur_pins), + .functions = glymur_functions, + .nfunctions = ARRAY_SIZE(glymur_functions), + .groups = glymur_groups, + .ngroups = ARRAY_SIZE(glymur_groups), + .ngpios = 251, + .wakeirq_map = glymur_pdc_map, + .nwakeirq_map = ARRAY_SIZE(glymur_pdc_map), + .egpio_func = 11, +}; + +static const struct of_device_id glymur_tlmm_of_match[] = { + { .compatible = "qcom,glymur-tlmm", .data = &glymur_tlmm }, + { } +}; + +static int glymur_tlmm_probe(struct platform_device *pdev) +{ + return msm_pinctrl_probe(pdev, &glymur_tlmm); +} + +static struct platform_driver glymur_tlmm_driver = { + .driver = { + .name = "glymur-tlmm", + .of_match_table = glymur_tlmm_of_match, + }, + .probe = glymur_tlmm_probe, +}; + +static int __init glymur_tlmm_init(void) +{ + return platform_driver_register(&glymur_tlmm_driver); +} +arch_initcall(glymur_tlmm_init); + +static void __exit glymur_tlmm_exit(void) +{ + platform_driver_unregister(&glymur_tlmm_driver); +} +module_exit(glymur_tlmm_exit); + +MODULE_DESCRIPTION("QTI GLYMUR TLMM driver"); +MODULE_LICENSE("GPL"); +MODULE_DEVICE_TABLE(of, glymur_tlmm_of_match); diff --git a/drivers/pinctrl/qcom/pinctrl-ipq5018.c b/drivers/pinctrl/qcom/pinctrl-ipq5018.c index 10b99d5d8a11..cbf34854f882 100644 --- a/drivers/pinctrl/qcom/pinctrl-ipq5018.c +++ b/drivers/pinctrl/qcom/pinctrl-ipq5018.c @@ -630,7 +630,7 @@ static const struct pinfunction ipq5018_functions[] = { MSM_PIN_FUNCTION(eud_gpio), MSM_PIN_FUNCTION(gcc_plltest), MSM_PIN_FUNCTION(gcc_tlmm), - MSM_PIN_FUNCTION(gpio), + MSM_GPIO_PIN_FUNCTION(gpio), MSM_PIN_FUNCTION(led0), MSM_PIN_FUNCTION(led2), MSM_PIN_FUNCTION(mac0), diff --git a/drivers/pinctrl/qcom/pinctrl-ipq5332.c b/drivers/pinctrl/qcom/pinctrl-ipq5332.c index 1ac2fc09c119..239cbe75f198 100644 --- a/drivers/pinctrl/qcom/pinctrl-ipq5332.c +++ b/drivers/pinctrl/qcom/pinctrl-ipq5332.c @@ -692,7 +692,7 @@ static const struct pinfunction ipq5332_functions[] = { MSM_PIN_FUNCTION(dbg_out), MSM_PIN_FUNCTION(gcc_plltest), MSM_PIN_FUNCTION(gcc_tlmm), - MSM_PIN_FUNCTION(gpio), + MSM_GPIO_PIN_FUNCTION(gpio), MSM_PIN_FUNCTION(lock_det), MSM_PIN_FUNCTION(mac0), MSM_PIN_FUNCTION(mac1), diff --git a/drivers/pinctrl/qcom/pinctrl-ipq5424.c b/drivers/pinctrl/qcom/pinctrl-ipq5424.c index 7ff1f8acc1a3..67b452a033d6 100644 --- a/drivers/pinctrl/qcom/pinctrl-ipq5424.c +++ b/drivers/pinctrl/qcom/pinctrl-ipq5424.c @@ -641,7 +641,7 @@ static const struct pinfunction ipq5424_functions[] = { MSM_PIN_FUNCTION(dbg_out), MSM_PIN_FUNCTION(gcc_plltest), MSM_PIN_FUNCTION(gcc_tlmm), - MSM_PIN_FUNCTION(gpio), + MSM_GPIO_PIN_FUNCTION(gpio), MSM_PIN_FUNCTION(i2c0_scl), MSM_PIN_FUNCTION(i2c0_sda), MSM_PIN_FUNCTION(i2c1_scl), diff --git a/drivers/pinctrl/qcom/pinctrl-ipq6018.c b/drivers/pinctrl/qcom/pinctrl-ipq6018.c index a4ba980252e1..be177fb0a92d 100644 --- a/drivers/pinctrl/qcom/pinctrl-ipq6018.c +++ b/drivers/pinctrl/qcom/pinctrl-ipq6018.c @@ -891,7 +891,7 @@ static const struct pinfunction ipq6018_functions[] = { MSM_PIN_FUNCTION(dbg_out), MSM_PIN_FUNCTION(gcc_plltest), MSM_PIN_FUNCTION(gcc_tlmm), - MSM_PIN_FUNCTION(gpio), + MSM_GPIO_PIN_FUNCTION(gpio), MSM_PIN_FUNCTION(lpass_aud), MSM_PIN_FUNCTION(lpass_aud0), MSM_PIN_FUNCTION(lpass_aud1), diff --git a/drivers/pinctrl/qcom/pinctrl-ipq8074.c b/drivers/pinctrl/qcom/pinctrl-ipq8074.c index 482f13282fc2..e94de9083314 100644 --- a/drivers/pinctrl/qcom/pinctrl-ipq8074.c +++ b/drivers/pinctrl/qcom/pinctrl-ipq8074.c @@ -838,7 +838,7 @@ static const struct pinfunction ipq8074_functions[] = { MSM_PIN_FUNCTION(dbg_out), MSM_PIN_FUNCTION(gcc_plltest), MSM_PIN_FUNCTION(gcc_tlmm), - MSM_PIN_FUNCTION(gpio), + MSM_GPIO_PIN_FUNCTION(gpio), MSM_PIN_FUNCTION(ldo_en), MSM_PIN_FUNCTION(ldo_update), MSM_PIN_FUNCTION(led0), diff --git a/drivers/pinctrl/qcom/pinctrl-ipq9574.c b/drivers/pinctrl/qcom/pinctrl-ipq9574.c index 89c05d8eb550..3ed093ea8eb9 100644 --- a/drivers/pinctrl/qcom/pinctrl-ipq9574.c +++ b/drivers/pinctrl/qcom/pinctrl-ipq9574.c @@ -651,7 +651,7 @@ static const struct pinfunction ipq9574_functions[] = { MSM_PIN_FUNCTION(dwc_ddrphy), MSM_PIN_FUNCTION(gcc_plltest), MSM_PIN_FUNCTION(gcc_tlmm), - MSM_PIN_FUNCTION(gpio), + MSM_GPIO_PIN_FUNCTION(gpio), MSM_PIN_FUNCTION(mac), MSM_PIN_FUNCTION(mdc), MSM_PIN_FUNCTION(mdio), diff --git a/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c b/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c index 57fefeb603f0..1c97ec44aa5f 100644 --- a/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c +++ b/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c @@ -41,13 +41,27 @@ struct lpi_pinctrl { static int lpi_gpio_read(struct lpi_pinctrl *state, unsigned int pin, unsigned int addr) { - return ioread32(state->tlmm_base + LPI_TLMM_REG_OFFSET * pin + addr); + u32 pin_offset; + + if (state->data->flags & LPI_FLAG_USE_PREDEFINED_PIN_OFFSET) + pin_offset = state->data->groups[pin].pin_offset; + else + pin_offset = LPI_TLMM_REG_OFFSET * pin; + + return ioread32(state->tlmm_base + pin_offset + addr); } static int lpi_gpio_write(struct lpi_pinctrl *state, unsigned int pin, unsigned int addr, unsigned int val) { - iowrite32(val, state->tlmm_base + LPI_TLMM_REG_OFFSET * pin + addr); + u32 pin_offset; + + if (state->data->flags & LPI_FLAG_USE_PREDEFINED_PIN_OFFSET) + pin_offset = state->data->groups[pin].pin_offset; + else + pin_offset = LPI_TLMM_REG_OFFSET * pin; + + iowrite32(val, state->tlmm_base + pin_offset + addr); return 0; } @@ -174,7 +188,7 @@ static int lpi_config_get(struct pinctrl_dev *pctldev, arg = 1; break; case PIN_CONFIG_INPUT_ENABLE: - case PIN_CONFIG_OUTPUT: + case PIN_CONFIG_LEVEL: if (is_out) arg = 1; break; @@ -252,7 +266,7 @@ static int lpi_config_set(struct pinctrl_dev *pctldev, unsigned int group, case PIN_CONFIG_INPUT_ENABLE: output_enabled = false; break; - case PIN_CONFIG_OUTPUT: + case PIN_CONFIG_LEVEL: output_enabled = true; value = arg; break; @@ -314,7 +328,7 @@ static int lpi_gpio_direction_output(struct gpio_chip *chip, struct lpi_pinctrl *state = gpiochip_get_data(chip); unsigned long config; - config = pinconf_to_config_packed(PIN_CONFIG_OUTPUT, val); + config = pinconf_to_config_packed(PIN_CONFIG_LEVEL, val); return lpi_config_set(state->ctrl, pin, &config, 1); } @@ -332,7 +346,7 @@ static int lpi_gpio_set(struct gpio_chip *chip, unsigned int pin, int value) struct lpi_pinctrl *state = gpiochip_get_data(chip); unsigned long config; - config = pinconf_to_config_packed(PIN_CONFIG_OUTPUT, value); + config = pinconf_to_config_packed(PIN_CONFIG_LEVEL, value); return lpi_config_set(state->ctrl, pin, &config, 1); } @@ -398,7 +412,7 @@ static const struct gpio_chip lpi_gpio_template = { .direction_input = lpi_gpio_direction_input, .direction_output = lpi_gpio_direction_output, .get = lpi_gpio_get, - .set_rv = lpi_gpio_set, + .set = lpi_gpio_set, .request = gpiochip_generic_request, .free = gpiochip_generic_free, .dbg_show = lpi_gpio_dbg_show, diff --git a/drivers/pinctrl/qcom/pinctrl-lpass-lpi.h b/drivers/pinctrl/qcom/pinctrl-lpass-lpi.h index a9b2f65c1ebe..f48368492861 100644 --- a/drivers/pinctrl/qcom/pinctrl-lpass-lpi.h +++ b/drivers/pinctrl/qcom/pinctrl-lpass-lpi.h @@ -55,6 +55,22 @@ struct pinctrl_pin_desc; LPI_MUX_##f4, \ }, \ .nfuncs = 5, \ + .pin_offset = 0, \ + } + +#define LPI_PINGROUP_OFFSET(id, soff, f1, f2, f3, f4, poff) \ + { \ + .pin = id, \ + .slew_offset = soff, \ + .funcs = (int[]){ \ + LPI_MUX_gpio, \ + LPI_MUX_##f1, \ + LPI_MUX_##f2, \ + LPI_MUX_##f3, \ + LPI_MUX_##f4, \ + }, \ + .nfuncs = 5, \ + .pin_offset = poff, \ } /* @@ -62,6 +78,7 @@ struct pinctrl_pin_desc; * pin configuration. */ #define LPI_FLAG_SLEW_RATE_SAME_REG BIT(0) +#define LPI_FLAG_USE_PREDEFINED_PIN_OFFSET BIT(1) struct lpi_pingroup { unsigned int pin; @@ -69,6 +86,7 @@ struct lpi_pingroup { int slew_offset; unsigned int *funcs; unsigned int nfuncs; + unsigned int pin_offset; }; struct lpi_function { diff --git a/drivers/pinctrl/qcom/pinctrl-mdm9607.c b/drivers/pinctrl/qcom/pinctrl-mdm9607.c index 3e18ba124fed..cef330547ce7 100644 --- a/drivers/pinctrl/qcom/pinctrl-mdm9607.c +++ b/drivers/pinctrl/qcom/pinctrl-mdm9607.c @@ -861,7 +861,7 @@ static const struct pinfunction mdm9607_functions[] = { MSM_PIN_FUNCTION(gcc_plltest), MSM_PIN_FUNCTION(gcc_tlmm), MSM_PIN_FUNCTION(gmac_mdio), - MSM_PIN_FUNCTION(gpio), + MSM_GPIO_PIN_FUNCTION(gpio), MSM_PIN_FUNCTION(gsm0_tx), MSM_PIN_FUNCTION(lcd_rst), MSM_PIN_FUNCTION(ldo_en), diff --git a/drivers/pinctrl/qcom/pinctrl-mdm9615.c b/drivers/pinctrl/qcom/pinctrl-mdm9615.c index bea1ca3d1b7f..729fe3d7e14e 100644 --- a/drivers/pinctrl/qcom/pinctrl-mdm9615.c +++ b/drivers/pinctrl/qcom/pinctrl-mdm9615.c @@ -313,7 +313,7 @@ static const char * const cdc_mclk_groups[] = { }; static const struct pinfunction mdm9615_functions[] = { - MSM_PIN_FUNCTION(gpio), + MSM_GPIO_PIN_FUNCTION(gpio), MSM_PIN_FUNCTION(gsbi2_i2c), MSM_PIN_FUNCTION(gsbi3), MSM_PIN_FUNCTION(gsbi4), diff --git a/drivers/pinctrl/qcom/pinctrl-milos.c b/drivers/pinctrl/qcom/pinctrl-milos.c new file mode 100644 index 000000000000..19abd5233a2c --- /dev/null +++ b/drivers/pinctrl/qcom/pinctrl-milos.c @@ -0,0 +1,1339 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2025, Luca Weiss <luca.weiss@fairphone.com> + */ + +#include <linux/module.h> +#include <linux/of.h> +#include <linux/platform_device.h> + +#include "pinctrl-msm.h" + +#define REG_SIZE 0x1000 + +#define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7, f8, f9, f10, f11) \ + { \ + .grp = PINCTRL_PINGROUP("gpio" #id, \ + gpio##id##_pins, \ + ARRAY_SIZE(gpio##id##_pins)), \ + .funcs = (int[]){ \ + msm_mux_gpio, /* gpio mode */ \ + msm_mux_##f1, \ + msm_mux_##f2, \ + msm_mux_##f3, \ + msm_mux_##f4, \ + msm_mux_##f5, \ + msm_mux_##f6, \ + msm_mux_##f7, \ + msm_mux_##f8, \ + msm_mux_##f9, \ + msm_mux_##f10, \ + msm_mux_##f11 /* egpio mode */ \ + }, \ + .nfuncs = 12, \ + .ctl_reg = REG_SIZE * id, \ + .io_reg = 0x4 + REG_SIZE * id, \ + .intr_cfg_reg = 0x8 + REG_SIZE * id, \ + .intr_status_reg = 0xc + REG_SIZE * id, \ + .intr_target_reg = 0x8 + REG_SIZE * id, \ + .mux_bit = 2, \ + .pull_bit = 0, \ + .drv_bit = 6, \ + .i2c_pull_bit = 13, \ + .egpio_enable = 12, \ + .egpio_present = 11, \ + .oe_bit = 9, \ + .in_bit = 0, \ + .out_bit = 1, \ + .intr_enable_bit = 0, \ + .intr_status_bit = 0, \ + .intr_target_bit = 8, \ + .intr_wakeup_enable_bit = 7, \ + .intr_wakeup_present_bit = 6, \ + .intr_target_kpss_val = 3, \ + .intr_raw_status_bit = 4, \ + .intr_polarity_bit = 1, \ + .intr_detection_bit = 2, \ + .intr_detection_width = 2, \ + } + +#define SDC_QDSD_PINGROUP(pg_name, ctl, pull, drv) \ + { \ + .grp = PINCTRL_PINGROUP(#pg_name, \ + pg_name##_pins, \ + ARRAY_SIZE(pg_name##_pins)), \ + .ctl_reg = ctl, \ + .io_reg = 0, \ + .intr_cfg_reg = 0, \ + .intr_status_reg = 0, \ + .intr_target_reg = 0, \ + .mux_bit = -1, \ + .pull_bit = pull, \ + .drv_bit = drv, \ + .oe_bit = -1, \ + .in_bit = -1, \ + .out_bit = -1, \ + .intr_enable_bit = -1, \ + .intr_status_bit = -1, \ + .intr_target_bit = -1, \ + .intr_raw_status_bit = -1, \ + .intr_polarity_bit = -1, \ + .intr_detection_bit = -1, \ + .intr_detection_width = -1, \ + } + +#define UFS_RESET(pg_name, ctl, io) \ + { \ + .grp = PINCTRL_PINGROUP(#pg_name, \ + pg_name##_pins, \ + ARRAY_SIZE(pg_name##_pins)), \ + .ctl_reg = ctl, \ + .io_reg = io, \ + .intr_cfg_reg = 0, \ + .intr_status_reg = 0, \ + .intr_target_reg = 0, \ + .mux_bit = -1, \ + .pull_bit = 3, \ + .drv_bit = 0, \ + .oe_bit = -1, \ + .in_bit = -1, \ + .out_bit = 0, \ + .intr_enable_bit = -1, \ + .intr_status_bit = -1, \ + .intr_target_bit = -1, \ + .intr_raw_status_bit = -1, \ + .intr_polarity_bit = -1, \ + .intr_detection_bit = -1, \ + .intr_detection_width = -1, \ + } + +static const struct pinctrl_pin_desc milos_pins[] = { + PINCTRL_PIN(0, "GPIO_0"), + PINCTRL_PIN(1, "GPIO_1"), + PINCTRL_PIN(2, "GPIO_2"), + PINCTRL_PIN(3, "GPIO_3"), + PINCTRL_PIN(4, "GPIO_4"), + PINCTRL_PIN(5, "GPIO_5"), + PINCTRL_PIN(6, "GPIO_6"), + PINCTRL_PIN(7, "GPIO_7"), + PINCTRL_PIN(8, "GPIO_8"), + PINCTRL_PIN(9, "GPIO_9"), + PINCTRL_PIN(10, "GPIO_10"), + PINCTRL_PIN(11, "GPIO_11"), + PINCTRL_PIN(12, "GPIO_12"), + PINCTRL_PIN(13, "GPIO_13"), + PINCTRL_PIN(14, "GPIO_14"), + PINCTRL_PIN(15, "GPIO_15"), + PINCTRL_PIN(16, "GPIO_16"), + PINCTRL_PIN(17, "GPIO_17"), + PINCTRL_PIN(18, "GPIO_18"), + PINCTRL_PIN(19, "GPIO_19"), + PINCTRL_PIN(20, "GPIO_20"), + PINCTRL_PIN(21, "GPIO_21"), + PINCTRL_PIN(22, "GPIO_22"), + PINCTRL_PIN(23, "GPIO_23"), + PINCTRL_PIN(24, "GPIO_24"), + PINCTRL_PIN(25, "GPIO_25"), + PINCTRL_PIN(26, "GPIO_26"), + PINCTRL_PIN(27, "GPIO_27"), + PINCTRL_PIN(28, "GPIO_28"), + PINCTRL_PIN(29, "GPIO_29"), + PINCTRL_PIN(30, "GPIO_30"), + PINCTRL_PIN(31, "GPIO_31"), + PINCTRL_PIN(32, "GPIO_32"), + PINCTRL_PIN(33, "GPIO_33"), + PINCTRL_PIN(34, "GPIO_34"), + PINCTRL_PIN(35, "GPIO_35"), + PINCTRL_PIN(36, "GPIO_36"), + PINCTRL_PIN(37, "GPIO_37"), + PINCTRL_PIN(38, "GPIO_38"), + PINCTRL_PIN(39, "GPIO_39"), + PINCTRL_PIN(40, "GPIO_40"), + PINCTRL_PIN(41, "GPIO_41"), + PINCTRL_PIN(42, "GPIO_42"), + PINCTRL_PIN(43, "GPIO_43"), + PINCTRL_PIN(44, "GPIO_44"), + PINCTRL_PIN(45, "GPIO_45"), + PINCTRL_PIN(46, "GPIO_46"), + PINCTRL_PIN(47, "GPIO_47"), + PINCTRL_PIN(48, "GPIO_48"), + PINCTRL_PIN(49, "GPIO_49"), + PINCTRL_PIN(50, "GPIO_50"), + PINCTRL_PIN(51, "GPIO_51"), + PINCTRL_PIN(52, "GPIO_52"), + PINCTRL_PIN(53, "GPIO_53"), + PINCTRL_PIN(54, "GPIO_54"), + PINCTRL_PIN(55, "GPIO_55"), + PINCTRL_PIN(56, "GPIO_56"), + PINCTRL_PIN(57, "GPIO_57"), + PINCTRL_PIN(58, "GPIO_58"), + PINCTRL_PIN(59, "GPIO_59"), + PINCTRL_PIN(60, "GPIO_60"), + PINCTRL_PIN(61, "GPIO_61"), + PINCTRL_PIN(62, "GPIO_62"), + PINCTRL_PIN(63, "GPIO_63"), + PINCTRL_PIN(64, "GPIO_64"), + PINCTRL_PIN(65, "GPIO_65"), + PINCTRL_PIN(66, "GPIO_66"), + PINCTRL_PIN(67, "GPIO_67"), + PINCTRL_PIN(68, "GPIO_68"), + PINCTRL_PIN(69, "GPIO_69"), + PINCTRL_PIN(70, "GPIO_70"), + PINCTRL_PIN(71, "GPIO_71"), + PINCTRL_PIN(72, "GPIO_72"), + PINCTRL_PIN(73, "GPIO_73"), + PINCTRL_PIN(74, "GPIO_74"), + PINCTRL_PIN(75, "GPIO_75"), + PINCTRL_PIN(76, "GPIO_76"), + PINCTRL_PIN(77, "GPIO_77"), + PINCTRL_PIN(78, "GPIO_78"), + PINCTRL_PIN(79, "GPIO_79"), + PINCTRL_PIN(80, "GPIO_80"), + PINCTRL_PIN(81, "GPIO_81"), + PINCTRL_PIN(82, "GPIO_82"), + PINCTRL_PIN(83, "GPIO_83"), + PINCTRL_PIN(84, "GPIO_84"), + PINCTRL_PIN(85, "GPIO_85"), + PINCTRL_PIN(86, "GPIO_86"), + PINCTRL_PIN(87, "GPIO_87"), + PINCTRL_PIN(88, "GPIO_88"), + PINCTRL_PIN(89, "GPIO_89"), + PINCTRL_PIN(90, "GPIO_90"), + PINCTRL_PIN(91, "GPIO_91"), + PINCTRL_PIN(92, "GPIO_92"), + PINCTRL_PIN(93, "GPIO_93"), + PINCTRL_PIN(94, "GPIO_94"), + PINCTRL_PIN(95, "GPIO_95"), + PINCTRL_PIN(96, "GPIO_96"), + PINCTRL_PIN(97, "GPIO_97"), + PINCTRL_PIN(98, "GPIO_98"), + PINCTRL_PIN(99, "GPIO_99"), + PINCTRL_PIN(100, "GPIO_100"), + PINCTRL_PIN(101, "GPIO_101"), + PINCTRL_PIN(102, "GPIO_102"), + PINCTRL_PIN(103, "GPIO_103"), + PINCTRL_PIN(104, "GPIO_104"), + PINCTRL_PIN(105, "GPIO_105"), + PINCTRL_PIN(106, "GPIO_106"), + PINCTRL_PIN(107, "GPIO_107"), + PINCTRL_PIN(108, "GPIO_108"), + PINCTRL_PIN(109, "GPIO_109"), + PINCTRL_PIN(110, "GPIO_110"), + PINCTRL_PIN(111, "GPIO_111"), + PINCTRL_PIN(112, "GPIO_112"), + PINCTRL_PIN(113, "GPIO_113"), + PINCTRL_PIN(114, "GPIO_114"), + PINCTRL_PIN(115, "GPIO_115"), + PINCTRL_PIN(116, "GPIO_116"), + PINCTRL_PIN(117, "GPIO_117"), + PINCTRL_PIN(118, "GPIO_118"), + PINCTRL_PIN(119, "GPIO_119"), + PINCTRL_PIN(120, "GPIO_120"), + PINCTRL_PIN(121, "GPIO_121"), + PINCTRL_PIN(122, "GPIO_122"), + PINCTRL_PIN(123, "GPIO_123"), + PINCTRL_PIN(124, "GPIO_124"), + PINCTRL_PIN(125, "GPIO_125"), + PINCTRL_PIN(126, "GPIO_126"), + PINCTRL_PIN(127, "GPIO_127"), + PINCTRL_PIN(128, "GPIO_128"), + PINCTRL_PIN(129, "GPIO_129"), + PINCTRL_PIN(130, "GPIO_130"), + PINCTRL_PIN(131, "GPIO_131"), + PINCTRL_PIN(132, "GPIO_132"), + PINCTRL_PIN(133, "GPIO_133"), + PINCTRL_PIN(134, "GPIO_134"), + PINCTRL_PIN(135, "GPIO_135"), + PINCTRL_PIN(136, "GPIO_136"), + PINCTRL_PIN(137, "GPIO_137"), + PINCTRL_PIN(138, "GPIO_138"), + PINCTRL_PIN(139, "GPIO_139"), + PINCTRL_PIN(140, "GPIO_140"), + PINCTRL_PIN(141, "GPIO_141"), + PINCTRL_PIN(142, "GPIO_142"), + PINCTRL_PIN(143, "GPIO_143"), + PINCTRL_PIN(144, "GPIO_144"), + PINCTRL_PIN(145, "GPIO_145"), + PINCTRL_PIN(146, "GPIO_146"), + PINCTRL_PIN(147, "GPIO_147"), + PINCTRL_PIN(148, "GPIO_148"), + PINCTRL_PIN(149, "GPIO_149"), + PINCTRL_PIN(150, "GPIO_150"), + PINCTRL_PIN(151, "GPIO_151"), + PINCTRL_PIN(152, "GPIO_152"), + PINCTRL_PIN(153, "GPIO_153"), + PINCTRL_PIN(154, "GPIO_154"), + PINCTRL_PIN(155, "GPIO_155"), + PINCTRL_PIN(156, "GPIO_156"), + PINCTRL_PIN(157, "GPIO_157"), + PINCTRL_PIN(158, "GPIO_158"), + PINCTRL_PIN(159, "GPIO_159"), + PINCTRL_PIN(160, "GPIO_160"), + PINCTRL_PIN(161, "GPIO_161"), + PINCTRL_PIN(162, "GPIO_162"), + PINCTRL_PIN(163, "GPIO_163"), + PINCTRL_PIN(164, "GPIO_164"), + PINCTRL_PIN(165, "GPIO_165"), + PINCTRL_PIN(166, "GPIO_166"), + PINCTRL_PIN(167, "UFS_RESET"), + PINCTRL_PIN(168, "SDC2_CLK"), + PINCTRL_PIN(169, "SDC2_CMD"), + PINCTRL_PIN(170, "SDC2_DATA"), +}; + +#define DECLARE_MSM_GPIO_PINS(pin) \ + static const unsigned int gpio##pin##_pins[] = { pin } +DECLARE_MSM_GPIO_PINS(0); +DECLARE_MSM_GPIO_PINS(1); +DECLARE_MSM_GPIO_PINS(2); +DECLARE_MSM_GPIO_PINS(3); +DECLARE_MSM_GPIO_PINS(4); +DECLARE_MSM_GPIO_PINS(5); +DECLARE_MSM_GPIO_PINS(6); +DECLARE_MSM_GPIO_PINS(7); +DECLARE_MSM_GPIO_PINS(8); +DECLARE_MSM_GPIO_PINS(9); +DECLARE_MSM_GPIO_PINS(10); +DECLARE_MSM_GPIO_PINS(11); +DECLARE_MSM_GPIO_PINS(12); +DECLARE_MSM_GPIO_PINS(13); +DECLARE_MSM_GPIO_PINS(14); +DECLARE_MSM_GPIO_PINS(15); +DECLARE_MSM_GPIO_PINS(16); +DECLARE_MSM_GPIO_PINS(17); +DECLARE_MSM_GPIO_PINS(18); +DECLARE_MSM_GPIO_PINS(19); +DECLARE_MSM_GPIO_PINS(20); +DECLARE_MSM_GPIO_PINS(21); +DECLARE_MSM_GPIO_PINS(22); +DECLARE_MSM_GPIO_PINS(23); +DECLARE_MSM_GPIO_PINS(24); +DECLARE_MSM_GPIO_PINS(25); +DECLARE_MSM_GPIO_PINS(26); +DECLARE_MSM_GPIO_PINS(27); +DECLARE_MSM_GPIO_PINS(28); +DECLARE_MSM_GPIO_PINS(29); +DECLARE_MSM_GPIO_PINS(30); +DECLARE_MSM_GPIO_PINS(31); +DECLARE_MSM_GPIO_PINS(32); +DECLARE_MSM_GPIO_PINS(33); +DECLARE_MSM_GPIO_PINS(34); +DECLARE_MSM_GPIO_PINS(35); +DECLARE_MSM_GPIO_PINS(36); +DECLARE_MSM_GPIO_PINS(37); +DECLARE_MSM_GPIO_PINS(38); +DECLARE_MSM_GPIO_PINS(39); +DECLARE_MSM_GPIO_PINS(40); +DECLARE_MSM_GPIO_PINS(41); +DECLARE_MSM_GPIO_PINS(42); +DECLARE_MSM_GPIO_PINS(43); +DECLARE_MSM_GPIO_PINS(44); +DECLARE_MSM_GPIO_PINS(45); +DECLARE_MSM_GPIO_PINS(46); +DECLARE_MSM_GPIO_PINS(47); +DECLARE_MSM_GPIO_PINS(48); +DECLARE_MSM_GPIO_PINS(49); +DECLARE_MSM_GPIO_PINS(50); +DECLARE_MSM_GPIO_PINS(51); +DECLARE_MSM_GPIO_PINS(52); +DECLARE_MSM_GPIO_PINS(53); +DECLARE_MSM_GPIO_PINS(54); +DECLARE_MSM_GPIO_PINS(55); +DECLARE_MSM_GPIO_PINS(56); +DECLARE_MSM_GPIO_PINS(57); +DECLARE_MSM_GPIO_PINS(58); +DECLARE_MSM_GPIO_PINS(59); +DECLARE_MSM_GPIO_PINS(60); +DECLARE_MSM_GPIO_PINS(61); +DECLARE_MSM_GPIO_PINS(62); +DECLARE_MSM_GPIO_PINS(63); +DECLARE_MSM_GPIO_PINS(64); +DECLARE_MSM_GPIO_PINS(65); +DECLARE_MSM_GPIO_PINS(66); +DECLARE_MSM_GPIO_PINS(67); +DECLARE_MSM_GPIO_PINS(68); +DECLARE_MSM_GPIO_PINS(69); +DECLARE_MSM_GPIO_PINS(70); +DECLARE_MSM_GPIO_PINS(71); +DECLARE_MSM_GPIO_PINS(72); +DECLARE_MSM_GPIO_PINS(73); +DECLARE_MSM_GPIO_PINS(74); +DECLARE_MSM_GPIO_PINS(75); +DECLARE_MSM_GPIO_PINS(76); +DECLARE_MSM_GPIO_PINS(77); +DECLARE_MSM_GPIO_PINS(78); +DECLARE_MSM_GPIO_PINS(79); +DECLARE_MSM_GPIO_PINS(80); +DECLARE_MSM_GPIO_PINS(81); +DECLARE_MSM_GPIO_PINS(82); +DECLARE_MSM_GPIO_PINS(83); +DECLARE_MSM_GPIO_PINS(84); +DECLARE_MSM_GPIO_PINS(85); +DECLARE_MSM_GPIO_PINS(86); +DECLARE_MSM_GPIO_PINS(87); +DECLARE_MSM_GPIO_PINS(88); +DECLARE_MSM_GPIO_PINS(89); +DECLARE_MSM_GPIO_PINS(90); +DECLARE_MSM_GPIO_PINS(91); +DECLARE_MSM_GPIO_PINS(92); +DECLARE_MSM_GPIO_PINS(93); +DECLARE_MSM_GPIO_PINS(94); +DECLARE_MSM_GPIO_PINS(95); +DECLARE_MSM_GPIO_PINS(96); +DECLARE_MSM_GPIO_PINS(97); +DECLARE_MSM_GPIO_PINS(98); +DECLARE_MSM_GPIO_PINS(99); +DECLARE_MSM_GPIO_PINS(100); +DECLARE_MSM_GPIO_PINS(101); +DECLARE_MSM_GPIO_PINS(102); +DECLARE_MSM_GPIO_PINS(103); +DECLARE_MSM_GPIO_PINS(104); +DECLARE_MSM_GPIO_PINS(105); +DECLARE_MSM_GPIO_PINS(106); +DECLARE_MSM_GPIO_PINS(107); +DECLARE_MSM_GPIO_PINS(108); +DECLARE_MSM_GPIO_PINS(109); +DECLARE_MSM_GPIO_PINS(110); +DECLARE_MSM_GPIO_PINS(111); +DECLARE_MSM_GPIO_PINS(112); +DECLARE_MSM_GPIO_PINS(113); +DECLARE_MSM_GPIO_PINS(114); +DECLARE_MSM_GPIO_PINS(115); +DECLARE_MSM_GPIO_PINS(116); +DECLARE_MSM_GPIO_PINS(117); +DECLARE_MSM_GPIO_PINS(118); +DECLARE_MSM_GPIO_PINS(119); +DECLARE_MSM_GPIO_PINS(120); +DECLARE_MSM_GPIO_PINS(121); +DECLARE_MSM_GPIO_PINS(122); +DECLARE_MSM_GPIO_PINS(123); +DECLARE_MSM_GPIO_PINS(124); +DECLARE_MSM_GPIO_PINS(125); +DECLARE_MSM_GPIO_PINS(126); +DECLARE_MSM_GPIO_PINS(127); +DECLARE_MSM_GPIO_PINS(128); +DECLARE_MSM_GPIO_PINS(129); +DECLARE_MSM_GPIO_PINS(130); +DECLARE_MSM_GPIO_PINS(131); +DECLARE_MSM_GPIO_PINS(132); +DECLARE_MSM_GPIO_PINS(133); +DECLARE_MSM_GPIO_PINS(134); +DECLARE_MSM_GPIO_PINS(135); +DECLARE_MSM_GPIO_PINS(136); +DECLARE_MSM_GPIO_PINS(137); +DECLARE_MSM_GPIO_PINS(138); +DECLARE_MSM_GPIO_PINS(139); +DECLARE_MSM_GPIO_PINS(140); +DECLARE_MSM_GPIO_PINS(141); +DECLARE_MSM_GPIO_PINS(142); +DECLARE_MSM_GPIO_PINS(143); +DECLARE_MSM_GPIO_PINS(144); +DECLARE_MSM_GPIO_PINS(145); +DECLARE_MSM_GPIO_PINS(146); +DECLARE_MSM_GPIO_PINS(147); +DECLARE_MSM_GPIO_PINS(148); +DECLARE_MSM_GPIO_PINS(149); +DECLARE_MSM_GPIO_PINS(150); +DECLARE_MSM_GPIO_PINS(151); +DECLARE_MSM_GPIO_PINS(152); +DECLARE_MSM_GPIO_PINS(153); +DECLARE_MSM_GPIO_PINS(154); +DECLARE_MSM_GPIO_PINS(155); +DECLARE_MSM_GPIO_PINS(156); +DECLARE_MSM_GPIO_PINS(157); +DECLARE_MSM_GPIO_PINS(158); +DECLARE_MSM_GPIO_PINS(159); +DECLARE_MSM_GPIO_PINS(160); +DECLARE_MSM_GPIO_PINS(161); +DECLARE_MSM_GPIO_PINS(162); +DECLARE_MSM_GPIO_PINS(163); +DECLARE_MSM_GPIO_PINS(164); +DECLARE_MSM_GPIO_PINS(165); +DECLARE_MSM_GPIO_PINS(166); + +static const unsigned int ufs_reset_pins[] = { 167 }; +static const unsigned int sdc2_clk_pins[] = { 168 }; +static const unsigned int sdc2_cmd_pins[] = { 169 }; +static const unsigned int sdc2_data_pins[] = { 170 }; + +enum milos_functions { + msm_mux_gpio, + msm_mux_aoss_cti, + msm_mux_atest_char, + msm_mux_atest_usb, + msm_mux_audio_ext_mclk0, + msm_mux_audio_ext_mclk1, + msm_mux_audio_ref_clk, + msm_mux_cam_mclk, + msm_mux_cci_async_in0, + msm_mux_cci_i2c_scl, + msm_mux_cci_i2c_sda, + msm_mux_cci_timer, + msm_mux_coex_uart1_rx, + msm_mux_coex_uart1_tx, + msm_mux_dbg_out_clk, + msm_mux_ddr_bist_complete, + msm_mux_ddr_bist_fail, + msm_mux_ddr_bist_start, + msm_mux_ddr_bist_stop, + msm_mux_ddr_pxi0, + msm_mux_ddr_pxi1, + msm_mux_dp0_hot, + msm_mux_egpio, + msm_mux_gcc_gp1, + msm_mux_gcc_gp2, + msm_mux_gcc_gp3, + msm_mux_host2wlan_sol, + msm_mux_i2s0_data0, + msm_mux_i2s0_data1, + msm_mux_i2s0_sck, + msm_mux_i2s0_ws, + msm_mux_ibi_i3c, + msm_mux_jitter_bist, + msm_mux_mdp_vsync, + msm_mux_mdp_vsync0_out, + msm_mux_mdp_vsync1_out, + msm_mux_mdp_vsync2_out, + msm_mux_mdp_vsync3_out, + msm_mux_mdp_vsync_e, + msm_mux_nav_gpio0, + msm_mux_nav_gpio1, + msm_mux_nav_gpio2, + msm_mux_pcie0_clk_req_n, + msm_mux_pcie1_clk_req_n, + msm_mux_phase_flag, + msm_mux_pll_bist_sync, + msm_mux_pll_clk_aux, + msm_mux_prng_rosc0, + msm_mux_prng_rosc1, + msm_mux_prng_rosc2, + msm_mux_prng_rosc3, + msm_mux_qdss_cti, + msm_mux_qdss_gpio, + msm_mux_qlink0_enable, + msm_mux_qlink0_request, + msm_mux_qlink0_wmss, + msm_mux_qlink1_enable, + msm_mux_qlink1_request, + msm_mux_qlink1_wmss, + msm_mux_qspi0, + msm_mux_qup0_se0, + msm_mux_qup0_se1, + msm_mux_qup0_se2, + msm_mux_qup0_se3, + msm_mux_qup0_se4, + msm_mux_qup0_se5, + msm_mux_qup0_se6, + msm_mux_qup1_se0, + msm_mux_qup1_se1, + msm_mux_qup1_se2, + msm_mux_qup1_se3, + msm_mux_qup1_se4, + msm_mux_qup1_se5, + msm_mux_qup1_se6, + msm_mux_resout_gpio_n, + msm_mux_sd_write_protect, + msm_mux_sdc1_clk, + msm_mux_sdc1_cmd, + msm_mux_sdc1_data, + msm_mux_sdc1_rclk, + msm_mux_sdc2_clk, + msm_mux_sdc2_cmd, + msm_mux_sdc2_data, + msm_mux_sdc2_fb_clk, + msm_mux_tb_trig_sdc1, + msm_mux_tb_trig_sdc2, + msm_mux_tgu_ch0_trigout, + msm_mux_tgu_ch1_trigout, + msm_mux_tmess_prng0, + msm_mux_tmess_prng1, + msm_mux_tmess_prng2, + msm_mux_tmess_prng3, + msm_mux_tsense_pwm1, + msm_mux_tsense_pwm2, + msm_mux_uim0_clk, + msm_mux_uim0_data, + msm_mux_uim0_present, + msm_mux_uim0_reset, + msm_mux_uim1_clk_mira, + msm_mux_uim1_clk_mirb, + msm_mux_uim1_data_mira, + msm_mux_uim1_data_mirb, + msm_mux_uim1_present_mira, + msm_mux_uim1_present_mirb, + msm_mux_uim1_reset_mira, + msm_mux_uim1_reset_mirb, + msm_mux_usb0_hs, + msm_mux_usb0_phy_ps, + msm_mux_vfr_0, + msm_mux_vfr_1, + msm_mux_vsense_trigger_mirnat, + msm_mux_wcn_sw, + msm_mux_wcn_sw_ctrl, + msm_mux__, +}; + +static const char *const gpio_groups[] = { + "gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", + "gpio6", "gpio7", "gpio8", "gpio9", "gpio10", "gpio11", + "gpio12", "gpio13", "gpio14", "gpio15", "gpio16", "gpio17", + "gpio18", "gpio19", "gpio20", "gpio21", "gpio22", "gpio23", + "gpio24", "gpio25", "gpio26", "gpio27", "gpio28", "gpio29", + "gpio30", "gpio31", "gpio32", "gpio33", "gpio34", "gpio35", + "gpio36", "gpio37", "gpio38", "gpio39", "gpio40", "gpio41", + "gpio42", "gpio43", "gpio44", "gpio45", "gpio46", "gpio47", + "gpio48", "gpio49", "gpio50", "gpio51", "gpio52", "gpio53", + "gpio54", "gpio55", "gpio56", "gpio57", "gpio58", "gpio59", + "gpio60", "gpio61", "gpio62", "gpio63", "gpio64", "gpio65", + "gpio66", "gpio67", "gpio68", "gpio69", "gpio70", "gpio71", + "gpio72", "gpio73", "gpio74", "gpio75", "gpio76", "gpio77", + "gpio78", "gpio79", "gpio80", "gpio81", "gpio82", "gpio83", + "gpio84", "gpio85", "gpio86", "gpio87", "gpio88", "gpio89", + "gpio90", "gpio91", "gpio92", "gpio93", "gpio94", "gpio95", + "gpio96", "gpio97", "gpio98", "gpio99", "gpio100", "gpio101", + "gpio102", "gpio103", "gpio104", "gpio105", "gpio106", "gpio107", + "gpio108", "gpio109", "gpio110", "gpio111", "gpio112", "gpio113", + "gpio114", "gpio115", "gpio116", "gpio117", "gpio118", "gpio119", + "gpio120", "gpio121", "gpio122", "gpio123", "gpio124", "gpio125", + "gpio126", "gpio127", "gpio128", "gpio129", "gpio130", "gpio131", + "gpio132", "gpio133", "gpio134", "gpio135", "gpio136", "gpio137", + "gpio138", "gpio139", "gpio140", "gpio141", "gpio142", "gpio143", + "gpio144", "gpio145", "gpio146", "gpio147", "gpio148", "gpio149", + "gpio150", "gpio151", "gpio152", "gpio153", "gpio154", "gpio155", + "gpio156", "gpio157", "gpio158", "gpio159", "gpio160", "gpio161", + "gpio162", "gpio163", "gpio164", "gpio165", "gpio166", +}; +static const char *const resout_gpio_n_groups[] = { + "gpio39", +}; +static const char *const sdc1_clk_groups[] = { + "gpio77", +}; +static const char *const sdc1_cmd_groups[] = { + "gpio78", +}; +static const char *const sdc1_data_groups[] = { + "gpio73", "gpio74", "gpio75", "gpio76", "gpio79", "gpio80", + "gpio81", "gpio82", +}; +static const char *const sdc1_rclk_groups[] = { + "gpio72", +}; +static const char *const aoss_cti_groups[] = { + "gpio0", + "gpio1", + "gpio4", + "gpio5", +}; +static const char *const atest_char_groups[] = { + "gpio44", "gpio45", "gpio46", "gpio47", "gpio63", +}; +static const char *const atest_usb_groups[] = { + "gpio23", "gpio24", "gpio60", +}; +static const char *const audio_ext_mclk0_groups[] = { + "gpio23", +}; +static const char *const audio_ext_mclk1_groups[] = { + "gpio24", +}; +static const char *const audio_ref_clk_groups[] = { + "gpio24", +}; +static const char *const cam_mclk_groups[] = { + "gpio83", "gpio84", "gpio85", "gpio86", "gpio87", +}; +static const char *const cci_async_in0_groups[] = { + "gpio86", +}; +static const char *const cci_i2c_scl_groups[] = { + "gpio89", "gpio91", "gpio93", "gpio95", +}; +static const char *const cci_i2c_sda_groups[] = { + "gpio88", "gpio90", "gpio92", "gpio94", +}; +static const char *const cci_timer_groups[] = { + "gpio77", "gpio83", "gpio84", "gpio85", +}; +static const char *const coex_uart1_rx_groups[] = { + "gpio64", +}; +static const char *const coex_uart1_tx_groups[] = { + "gpio63", +}; +static const char *const dbg_out_clk_groups[] = { + "gpio24", +}; +static const char *const ddr_bist_complete_groups[] = { + "gpio137", +}; +static const char *const ddr_bist_fail_groups[] = { + "gpio56", +}; +static const char *const ddr_bist_start_groups[] = { + "gpio133", +}; +static const char *const ddr_bist_stop_groups[] = { + "gpio47", +}; +static const char *const ddr_pxi0_groups[] = { + "gpio23", + "gpio24", +}; +static const char *const ddr_pxi1_groups[] = { + "gpio50", + "gpio51", +}; +static const char *const dp0_hot_groups[] = { + "gpio75", +}; +static const char *const egpio_groups[] = { + "gpio132", "gpio133", "gpio134", "gpio135", "gpio136", "gpio137", + "gpio138", "gpio139", "gpio140", "gpio141", "gpio142", "gpio143", + "gpio144", "gpio145", "gpio146", "gpio147", "gpio148", "gpio149", + "gpio150", "gpio151", "gpio152", "gpio153", "gpio154", "gpio155", + "gpio156", "gpio157", "gpio158", "gpio159", "gpio160", "gpio161", + "gpio162", "gpio163", "gpio164", "gpio165", "gpio166", +}; +static const char *const gcc_gp1_groups[] = { + "gpio29", + "gpio32", +}; +static const char *const gcc_gp2_groups[] = { + "gpio28", + "gpio30", +}; +static const char *const gcc_gp3_groups[] = { + "gpio31", + "gpio33", +}; +static const char *const host2wlan_sol_groups[] = { + "gpio46", +}; +static const char *const i2s0_data0_groups[] = { + "gpio16", +}; +static const char *const i2s0_data1_groups[] = { + "gpio17", +}; +static const char *const i2s0_sck_groups[] = { + "gpio15", +}; +static const char *const i2s0_ws_groups[] = { + "gpio18", +}; +static const char *const ibi_i3c_groups[] = { + "gpio0", "gpio1", "gpio4", "gpio5", + "gpio32", "gpio33", "gpio36", "gpio37", +}; +static const char *const jitter_bist_groups[] = { + "gpio141", +}; +static const char *const mdp_vsync_groups[] = { + "gpio19", + "gpio37", + "gpio72", + "gpio129", +}; +static const char *const mdp_vsync0_out_groups[] = { + "gpio12", +}; +static const char *const mdp_vsync1_out_groups[] = { + "gpio12", +}; +static const char *const mdp_vsync2_out_groups[] = { + "gpio40", +}; +static const char *const mdp_vsync3_out_groups[] = { + "gpio40", +}; +static const char *const mdp_vsync_e_groups[] = { + "gpio45", +}; +static const char *const nav_gpio0_groups[] = { + "gpio124", +}; +static const char *const nav_gpio1_groups[] = { + "gpio125", +}; +static const char *const nav_gpio2_groups[] = { + "gpio126", +}; +static const char *const pcie0_clk_req_n_groups[] = { + "gpio67", +}; +static const char *const pcie1_clk_req_n_groups[] = { + "gpio70", +}; +static const char *const phase_flag_groups[] = { + "gpio8", "gpio9", "gpio11", "gpio12", "gpio13", "gpio14", + "gpio15", "gpio16", "gpio18", "gpio26", "gpio38", "gpio39", + "gpio40", "gpio41", "gpio42", "gpio43", "gpio44", "gpio45", + "gpio46", "gpio47", "gpio48", "gpio49", "gpio63", "gpio64", + "gpio127", "gpio138", "gpio139", "gpio140", "gpio142", "gpio143", + "gpio144", "gpio147", +}; +static const char *const pll_bist_sync_groups[] = { + "gpio26", +}; +static const char *const pll_clk_aux_groups[] = { + "gpio36", +}; +static const char *const prng_rosc0_groups[] = { + "gpio66", +}; +static const char *const prng_rosc1_groups[] = { + "gpio67", +}; +static const char *const prng_rosc2_groups[] = { + "gpio68", +}; +static const char *const prng_rosc3_groups[] = { + "gpio69", +}; +static const char *const qdss_cti_groups[] = { + "gpio4", "gpio5", "gpio6", "gpio7", + "gpio44", "gpio45", "gpio54", "gpio87", +}; +static const char *const qdss_gpio_groups[] = { + "gpio40", "gpio41", "gpio42", "gpio43", "gpio46", "gpio47", + "gpio48", "gpio49", "gpio50", "gpio51", "gpio52", "gpio53", + "gpio83", "gpio84", "gpio85", "gpio86", "gpio88", "gpio89", + "gpio138", "gpio139", "gpio140", "gpio141", "gpio149", "gpio150", + "gpio155", "gpio156", "gpio157", "gpio158", "gpio159", "gpio160", + "gpio161", "gpio162", "gpio163", "gpio164", "gpio165", "gpio166", +}; +static const char *const qlink0_enable_groups[] = { + "gpio105", +}; +static const char *const qlink0_request_groups[] = { + "gpio104", +}; +static const char *const qlink0_wmss_groups[] = { + "gpio106", +}; +static const char *const qlink1_enable_groups[] = { + "gpio108", +}; +static const char *const qlink1_request_groups[] = { + "gpio107", +}; +static const char *const qlink1_wmss_groups[] = { + "gpio109", +}; +static const char *const qspi0_groups[] = { + "gpio8", "gpio9", "gpio10", "gpio11", "gpio12", "gpio13", "gpio14", +}; +static const char *const qup0_se0_groups[] = { + "gpio0", "gpio1", "gpio2", "gpio3", +}; +static const char *const qup0_se1_groups[] = { + "gpio4", "gpio5", "gpio6", "gpio7", +}; +static const char *const qup0_se2_groups[] = { + "gpio8", "gpio9", "gpio10", "gpio11", "gpio12", "gpio13", "gpio14", +}; +static const char *const qup0_se3_groups[] = { + "gpio15", "gpio16", "gpio17", "gpio18", "gpio23", "gpio24", "gpio26", +}; +static const char *const qup0_se4_groups[] = { + "gpio19", "gpio20", "gpio21", "gpio22", +}; +static const char *const qup0_se5_groups[] = { + "gpio23", "gpio24", "gpio25", "gpio26", +}; +static const char *const qup0_se6_groups[] = { + "gpio27", "gpio28", "gpio29", "gpio30", "gpio31", +}; +static const char *const qup1_se0_groups[] = { + "gpio32", "gpio33", "gpio94", "gpio95", +}; +static const char *const qup1_se1_groups[] = { + "gpio36", "gpio37", "gpio38", "gpio39", +}; +static const char *const qup1_se2_groups[] = { + "gpio36", "gpio37", "gpio38", "gpio40", "gpio41", "gpio42", "gpio43", +}; +static const char *const qup1_se3_groups[] = { + "gpio92", "gpio93", "gpio94", "gpio95", +}; +static const char *const qup1_se4_groups[] = { + "gpio48", "gpio49", "gpio50", "gpio51", "gpio52", "gpio53", "gpio54", +}; +static const char *const qup1_se5_groups[] = { + "gpio55", "gpio56", "gpio59", "gpio60", +}; +static const char *const qup1_se6_groups[] = { + "gpio55", "gpio56", "gpio59", "gpio60", "gpio90", "gpio91", +}; +static const char *const sd_write_protect_groups[] = { + "gpio4", +}; +static const char *const sdc2_data_groups[] = { + "gpio34", + "gpio35", + "gpio57", + "gpio58", +}; +static const char *const sdc2_clk_groups[] = { + "gpio62", +}; +static const char *const sdc2_cmd_groups[] = { + "gpio61", +}; +static const char *const sdc2_fb_clk_groups[] = { + "gpio128", +}; +static const char *const tb_trig_sdc1_groups[] = { + "gpio87", +}; +static const char *const tb_trig_sdc2_groups[] = { + "gpio78", +}; +static const char *const tgu_ch0_trigout_groups[] = { + "gpio87", +}; +static const char *const tgu_ch1_trigout_groups[] = { + "gpio88", +}; +static const char *const tmess_prng0_groups[] = { + "gpio86", +}; +static const char *const tmess_prng1_groups[] = { + "gpio83", +}; +static const char *const tmess_prng2_groups[] = { + "gpio84", +}; +static const char *const tmess_prng3_groups[] = { + "gpio85", +}; +static const char *const tsense_pwm1_groups[] = { + "gpio17", +}; +static const char *const tsense_pwm2_groups[] = { + "gpio17", +}; +static const char *const uim0_clk_groups[] = { + "gpio97", +}; +static const char *const uim0_data_groups[] = { + "gpio96", +}; +static const char *const uim0_present_groups[] = { + "gpio99", +}; +static const char *const uim0_reset_groups[] = { + "gpio98", +}; +static const char *const uim1_clk_mira_groups[] = { + "gpio111", +}; +static const char *const uim1_clk_mirb_groups[] = { + "gpio101", +}; +static const char *const uim1_data_mira_groups[] = { + "gpio110", +}; +static const char *const uim1_data_mirb_groups[] = { + "gpio100", +}; +static const char *const uim1_present_mira_groups[] = { + "gpio113", +}; +static const char *const uim1_present_mirb_groups[] = { + "gpio103", +}; +static const char *const uim1_reset_mira_groups[] = { + "gpio112", +}; +static const char *const uim1_reset_mirb_groups[] = { + "gpio102", +}; +static const char *const usb0_hs_groups[] = { + "gpio125", +}; +static const char *const usb0_phy_ps_groups[] = { + "gpio131", +}; +static const char *const vfr_0_groups[] = { + "gpio56", +}; +static const char *const vfr_1_groups[] = { + "gpio126", +}; +static const char *const vsense_trigger_mirnat_groups[] = { + "gpio94", +}; +static const char *const wcn_sw_groups[] = { + "gpio52", +}; +static const char *const wcn_sw_ctrl_groups[] = { + "gpio45", +}; + +static const struct pinfunction milos_functions[] = { + MSM_GPIO_PIN_FUNCTION(gpio), + MSM_PIN_FUNCTION(aoss_cti), + MSM_PIN_FUNCTION(atest_char), + MSM_PIN_FUNCTION(atest_usb), + MSM_PIN_FUNCTION(audio_ext_mclk0), + MSM_PIN_FUNCTION(audio_ext_mclk1), + MSM_PIN_FUNCTION(audio_ref_clk), + MSM_PIN_FUNCTION(cam_mclk), + MSM_PIN_FUNCTION(cci_async_in0), + MSM_PIN_FUNCTION(cci_i2c_scl), + MSM_PIN_FUNCTION(cci_i2c_sda), + MSM_PIN_FUNCTION(cci_timer), + MSM_PIN_FUNCTION(coex_uart1_rx), + MSM_PIN_FUNCTION(coex_uart1_tx), + MSM_PIN_FUNCTION(dbg_out_clk), + MSM_PIN_FUNCTION(ddr_bist_complete), + MSM_PIN_FUNCTION(ddr_bist_fail), + MSM_PIN_FUNCTION(ddr_bist_start), + MSM_PIN_FUNCTION(ddr_bist_stop), + MSM_PIN_FUNCTION(ddr_pxi0), + MSM_PIN_FUNCTION(ddr_pxi1), + MSM_PIN_FUNCTION(dp0_hot), + MSM_PIN_FUNCTION(egpio), + MSM_PIN_FUNCTION(gcc_gp1), + MSM_PIN_FUNCTION(gcc_gp2), + MSM_PIN_FUNCTION(gcc_gp3), + MSM_PIN_FUNCTION(host2wlan_sol), + MSM_PIN_FUNCTION(i2s0_data0), + MSM_PIN_FUNCTION(i2s0_data1), + MSM_PIN_FUNCTION(i2s0_sck), + MSM_PIN_FUNCTION(i2s0_ws), + MSM_PIN_FUNCTION(ibi_i3c), + MSM_PIN_FUNCTION(jitter_bist), + MSM_PIN_FUNCTION(mdp_vsync), + MSM_PIN_FUNCTION(mdp_vsync0_out), + MSM_PIN_FUNCTION(mdp_vsync1_out), + MSM_PIN_FUNCTION(mdp_vsync2_out), + MSM_PIN_FUNCTION(mdp_vsync3_out), + MSM_PIN_FUNCTION(mdp_vsync_e), + MSM_PIN_FUNCTION(nav_gpio0), + MSM_PIN_FUNCTION(nav_gpio1), + MSM_PIN_FUNCTION(nav_gpio2), + MSM_PIN_FUNCTION(pcie0_clk_req_n), + MSM_PIN_FUNCTION(pcie1_clk_req_n), + MSM_PIN_FUNCTION(phase_flag), + MSM_PIN_FUNCTION(pll_bist_sync), + MSM_PIN_FUNCTION(pll_clk_aux), + MSM_PIN_FUNCTION(prng_rosc0), + MSM_PIN_FUNCTION(prng_rosc1), + MSM_PIN_FUNCTION(prng_rosc2), + MSM_PIN_FUNCTION(prng_rosc3), + MSM_PIN_FUNCTION(qdss_cti), + MSM_PIN_FUNCTION(qdss_gpio), + MSM_PIN_FUNCTION(qlink0_enable), + MSM_PIN_FUNCTION(qlink0_request), + MSM_PIN_FUNCTION(qlink0_wmss), + MSM_PIN_FUNCTION(qlink1_enable), + MSM_PIN_FUNCTION(qlink1_request), + MSM_PIN_FUNCTION(qlink1_wmss), + MSM_PIN_FUNCTION(qspi0), + MSM_PIN_FUNCTION(qup0_se0), + MSM_PIN_FUNCTION(qup0_se1), + MSM_PIN_FUNCTION(qup0_se2), + MSM_PIN_FUNCTION(qup0_se3), + MSM_PIN_FUNCTION(qup0_se4), + MSM_PIN_FUNCTION(qup0_se5), + MSM_PIN_FUNCTION(qup0_se6), + MSM_PIN_FUNCTION(qup1_se0), + MSM_PIN_FUNCTION(qup1_se1), + MSM_PIN_FUNCTION(qup1_se2), + MSM_PIN_FUNCTION(qup1_se3), + MSM_PIN_FUNCTION(qup1_se4), + MSM_PIN_FUNCTION(qup1_se5), + MSM_PIN_FUNCTION(qup1_se6), + MSM_PIN_FUNCTION(resout_gpio_n), + MSM_PIN_FUNCTION(sd_write_protect), + MSM_PIN_FUNCTION(sdc1_clk), + MSM_PIN_FUNCTION(sdc1_cmd), + MSM_PIN_FUNCTION(sdc1_data), + MSM_PIN_FUNCTION(sdc1_rclk), + MSM_PIN_FUNCTION(sdc2_clk), + MSM_PIN_FUNCTION(sdc2_cmd), + MSM_PIN_FUNCTION(sdc2_data), + MSM_PIN_FUNCTION(sdc2_fb_clk), + MSM_PIN_FUNCTION(tb_trig_sdc1), + MSM_PIN_FUNCTION(tb_trig_sdc2), + MSM_PIN_FUNCTION(tgu_ch0_trigout), + MSM_PIN_FUNCTION(tgu_ch1_trigout), + MSM_PIN_FUNCTION(tmess_prng0), + MSM_PIN_FUNCTION(tmess_prng1), + MSM_PIN_FUNCTION(tmess_prng2), + MSM_PIN_FUNCTION(tmess_prng3), + MSM_PIN_FUNCTION(tsense_pwm1), + MSM_PIN_FUNCTION(tsense_pwm2), + MSM_PIN_FUNCTION(uim0_clk), + MSM_PIN_FUNCTION(uim0_data), + MSM_PIN_FUNCTION(uim0_present), + MSM_PIN_FUNCTION(uim0_reset), + MSM_PIN_FUNCTION(uim1_clk_mira), + MSM_PIN_FUNCTION(uim1_clk_mirb), + MSM_PIN_FUNCTION(uim1_data_mira), + MSM_PIN_FUNCTION(uim1_data_mirb), + MSM_PIN_FUNCTION(uim1_present_mira), + MSM_PIN_FUNCTION(uim1_present_mirb), + MSM_PIN_FUNCTION(uim1_reset_mira), + MSM_PIN_FUNCTION(uim1_reset_mirb), + MSM_PIN_FUNCTION(usb0_hs), + MSM_PIN_FUNCTION(usb0_phy_ps), + MSM_PIN_FUNCTION(vfr_0), + MSM_PIN_FUNCTION(vfr_1), + MSM_PIN_FUNCTION(vsense_trigger_mirnat), + MSM_PIN_FUNCTION(wcn_sw), + MSM_PIN_FUNCTION(wcn_sw_ctrl), +}; + +/* + * Every pin is maintained as a single group, and missing or non-existing pin + * would be maintained as dummy group to synchronize pin group index with + * pin descriptor registered with pinctrl core. + * Clients would not be able to request these dummy pin groups. + */ +static const struct msm_pingroup milos_groups[] = { + [0] = PINGROUP(0, qup0_se0, ibi_i3c, aoss_cti, _, _, _, _, _, _, _, _), + [1] = PINGROUP(1, qup0_se0, ibi_i3c, aoss_cti, _, _, _, _, _, _, _, _), + [2] = PINGROUP(2, qup0_se0, _, _, _, _, _, _, _, _, _, _), + [3] = PINGROUP(3, qup0_se0, _, _, _, _, _, _, _, _, _, _), + [4] = PINGROUP(4, qup0_se1, ibi_i3c, aoss_cti, sd_write_protect, qdss_cti, _, _, _, _, _, _), + [5] = PINGROUP(5, qup0_se1, ibi_i3c, aoss_cti, qdss_cti, _, _, _, _, _, _, _), + [6] = PINGROUP(6, qup0_se1, qdss_cti, _, _, _, _, _, _, _, _, _), + [7] = PINGROUP(7, qup0_se1, qdss_cti, _, _, _, _, _, _, _, _, _), + [8] = PINGROUP(8, qup0_se2, qspi0, _, phase_flag, _, _, _, _, _, _, _), + [9] = PINGROUP(9, qup0_se2, qspi0, _, phase_flag, _, _, _, _, _, _, _), + [10] = PINGROUP(10, qup0_se2, qspi0, _, _, _, _, _, _, _, _, _), + [11] = PINGROUP(11, qup0_se2, qspi0, _, phase_flag, _, _, _, _, _, _, _), + [12] = PINGROUP(12, qup0_se2, qspi0, mdp_vsync0_out, mdp_vsync1_out, _, phase_flag, _, _, _, _, _), + [13] = PINGROUP(13, qup0_se2, qspi0, _, phase_flag, _, _, _, _, _, _, _), + [14] = PINGROUP(14, qup0_se2, qspi0, _, phase_flag, _, _, _, _, _, _, _), + [15] = PINGROUP(15, qup0_se3, i2s0_sck, _, phase_flag, _, _, _, _, _, _, _), + [16] = PINGROUP(16, qup0_se3, i2s0_data0, _, phase_flag, _, _, _, _, _, _, _), + [17] = PINGROUP(17, qup0_se3, i2s0_data1, tsense_pwm1, tsense_pwm2, _, _, _, _, _, _, _), + [18] = PINGROUP(18, qup0_se3, i2s0_ws, _, phase_flag, _, _, _, _, _, _, _), + [19] = PINGROUP(19, qup0_se4, mdp_vsync, _, _, _, _, _, _, _, _, _), + [20] = PINGROUP(20, qup0_se4, _, _, _, _, _, _, _, _, _, _), + [21] = PINGROUP(21, qup0_se4, _, _, _, _, _, _, _, _, _, _), + [22] = PINGROUP(22, qup0_se4, _, _, _, _, _, _, _, _, _, _), + [23] = PINGROUP(23, qup0_se5, qup0_se3, audio_ext_mclk0, _, atest_usb, ddr_pxi0, _, _, _, _, _), + [24] = PINGROUP(24, qup0_se5, qup0_se3, audio_ext_mclk1, audio_ref_clk, dbg_out_clk, _, atest_usb, ddr_pxi0, _, _, _), + [25] = PINGROUP(25, qup0_se5, _, _, _, _, _, _, _, _, _, _), + [26] = PINGROUP(26, qup0_se5, qup0_se3, pll_bist_sync, _, phase_flag, _, _, _, _, _, _), + [27] = PINGROUP(27, qup0_se6, _, _, _, _, _, _, _, _, _, _), + [28] = PINGROUP(28, qup0_se6, gcc_gp2, _, _, _, _, _, _, _, _, _), + [29] = PINGROUP(29, qup0_se6, gcc_gp1, _, _, _, _, _, _, _, _, _), + [30] = PINGROUP(30, qup0_se6, gcc_gp2, _, _, _, _, _, _, _, _, _), + [31] = PINGROUP(31, qup0_se6, gcc_gp3, _, _, _, _, _, _, _, _, _), + [32] = PINGROUP(32, qup1_se0, ibi_i3c, gcc_gp1, _, _, _, _, _, _, _, _), + [33] = PINGROUP(33, qup1_se0, ibi_i3c, gcc_gp3, _, _, _, _, _, _, _, _), + [34] = PINGROUP(34, sdc2_data, _, _, _, _, _, _, _, _, _, _), + [35] = PINGROUP(35, sdc2_data, _, _, _, _, _, _, _, _, _, _), + [36] = PINGROUP(36, qup1_se1, qup1_se2, ibi_i3c, pll_clk_aux, _, _, _, _, _, _, _), + [37] = PINGROUP(37, qup1_se1, qup1_se2, ibi_i3c, mdp_vsync, _, _, _, _, _, _, _), + [38] = PINGROUP(38, qup1_se1, qup1_se2, _, phase_flag, _, _, _, _, _, _, _), + [39] = PINGROUP(39, qup1_se1, resout_gpio_n, _, phase_flag, _, _, _, _, _, _, _), + [40] = PINGROUP(40, qup1_se2, mdp_vsync2_out, mdp_vsync3_out, _, phase_flag, qdss_gpio, _, _, _, _, _), + [41] = PINGROUP(41, qup1_se2, _, phase_flag, qdss_gpio, _, _, _, _, _, _, _), + [42] = PINGROUP(42, qup1_se2, _, phase_flag, qdss_gpio, _, _, _, _, _, _, _), + [43] = PINGROUP(43, qup1_se2, _, _, phase_flag, qdss_gpio, _, _, _, _, _, _), + [44] = PINGROUP(44, _, _, phase_flag, qdss_cti, atest_char, _, _, _, _, _, _), + [45] = PINGROUP(45, wcn_sw_ctrl, mdp_vsync_e, _, _, phase_flag, qdss_cti, atest_char, _, _, _, _), + [46] = PINGROUP(46, host2wlan_sol, _, phase_flag, qdss_gpio, atest_char, _, _, _, _, _, _), + [47] = PINGROUP(47, ddr_bist_stop, _, phase_flag, qdss_gpio, atest_char, _, _, _, _, _, _), + [48] = PINGROUP(48, qup1_se4, _, phase_flag, qdss_gpio, _, _, _, _, _, _, _), + [49] = PINGROUP(49, qup1_se4, _, phase_flag, qdss_gpio, _, _, _, _, _, _, _), + [50] = PINGROUP(50, qup1_se4, qdss_gpio, ddr_pxi1, _, _, _, _, _, _, _, _), + [51] = PINGROUP(51, qup1_se4, qdss_gpio, ddr_pxi1, _, _, _, _, _, _, _, _), + [52] = PINGROUP(52, qup1_se4, wcn_sw, qdss_gpio, _, _, _, _, _, _, _, _), + [53] = PINGROUP(53, qup1_se4, qdss_gpio, _, _, _, _, _, _, _, _, _), + [54] = PINGROUP(54, qup1_se4, qdss_cti, _, _, _, _, _, _, _, _, _), + [55] = PINGROUP(55, qup1_se5, qup1_se6, _, _, _, _, _, _, _, _, _), + [56] = PINGROUP(56, qup1_se5, qup1_se6, vfr_0, ddr_bist_fail, _, _, _, _, _, _, _), + [57] = PINGROUP(57, sdc2_data, _, _, _, _, _, _, _, _, _, _), + [58] = PINGROUP(58, sdc2_data, _, _, _, _, _, _, _, _, _, _), + [59] = PINGROUP(59, qup1_se6, _, qup1_se5, _, _, _, _, _, _, _, _), + [60] = PINGROUP(60, qup1_se6, _, qup1_se5, atest_usb, _, _, _, _, _, _, _), + [61] = PINGROUP(61, sdc2_cmd, _, _, _, _, _, _, _, _, _, _), + [62] = PINGROUP(62, sdc2_clk, _, _, _, _, _, _, _, _, _, _), + [63] = PINGROUP(63, coex_uart1_tx, _, phase_flag, atest_char, _, _, _, _, _, _, _), + [64] = PINGROUP(64, coex_uart1_rx, _, phase_flag, _, _, _, _, _, _, _, _), + [65] = PINGROUP(65, _, _, _, _, _, _, _, _, _, _, _), + [66] = PINGROUP(66, prng_rosc0, _, _, _, _, _, _, _, _, _, _), + [67] = PINGROUP(67, pcie0_clk_req_n, prng_rosc1, _, _, _, _, _, _, _, _, _), + [68] = PINGROUP(68, prng_rosc2, _, _, _, _, _, _, _, _, _, _), + [69] = PINGROUP(69, prng_rosc3, _, _, _, _, _, _, _, _, _, _), + [70] = PINGROUP(70, pcie1_clk_req_n, _, _, _, _, _, _, _, _, _, _), + [71] = PINGROUP(71, _, _, _, _, _, _, _, _, _, _, _), + [72] = PINGROUP(72, sdc1_rclk, mdp_vsync, _, _, _, _, _, _, _, _, _), + [73] = PINGROUP(73, sdc1_data, _, _, _, _, _, _, _, _, _, _), + [74] = PINGROUP(74, sdc1_data, _, _, _, _, _, _, _, _, _, _), + [75] = PINGROUP(75, sdc1_data, dp0_hot, _, _, _, _, _, _, _, _, _), + [76] = PINGROUP(76, sdc1_data, _, _, _, _, _, _, _, _, _, _), + [77] = PINGROUP(77, sdc1_clk, cci_timer, _, _, _, _, _, _, _, _, _), + [78] = PINGROUP(78, sdc1_cmd, tb_trig_sdc2, _, _, _, _, _, _, _, _, _), + [79] = PINGROUP(79, sdc1_data, _, _, _, _, _, _, _, _, _, _), + [80] = PINGROUP(80, sdc1_data, _, _, _, _, _, _, _, _, _, _), + [81] = PINGROUP(81, sdc1_data, _, _, _, _, _, _, _, _, _, _), + [82] = PINGROUP(82, sdc1_data, _, _, _, _, _, _, _, _, _, _), + [83] = PINGROUP(83, cam_mclk, cci_timer, tmess_prng1, qdss_gpio, _, _, _, _, _, _, _), + [84] = PINGROUP(84, cam_mclk, cci_timer, tmess_prng2, qdss_gpio, _, _, _, _, _, _, _), + [85] = PINGROUP(85, cam_mclk, cci_timer, tmess_prng3, qdss_gpio, _, _, _, _, _, _, _), + [86] = PINGROUP(86, cam_mclk, cci_async_in0, tmess_prng0, qdss_gpio, _, _, _, _, _, _, _), + [87] = PINGROUP(87, cam_mclk, tb_trig_sdc1, tgu_ch0_trigout, qdss_cti, _, _, _, _, _, _, _), + [88] = PINGROUP(88, cci_i2c_sda, tgu_ch1_trigout, _, qdss_gpio, _, _, _, _, _, _, _), + [89] = PINGROUP(89, cci_i2c_scl, _, qdss_gpio, _, _, _, _, _, _, _, _), + [90] = PINGROUP(90, cci_i2c_sda, qup1_se6, _, _, _, _, _, _, _, _, _), + [91] = PINGROUP(91, cci_i2c_scl, qup1_se6, _, _, _, _, _, _, _, _, _), + [92] = PINGROUP(92, cci_i2c_sda, qup1_se3, _, _, _, _, _, _, _, _, _), + [93] = PINGROUP(93, cci_i2c_scl, qup1_se3, _, _, _, _, _, _, _, _, _), + [94] = PINGROUP(94, cci_i2c_sda, qup1_se3, qup1_se0, _, vsense_trigger_mirnat, _, _, _, _, _, _), + [95] = PINGROUP(95, cci_i2c_scl, qup1_se3, qup1_se0, _, _, _, _, _, _, _, _), + [96] = PINGROUP(96, uim0_data, _, _, _, _, _, _, _, _, _, _), + [97] = PINGROUP(97, uim0_clk, _, _, _, _, _, _, _, _, _, _), + [98] = PINGROUP(98, uim0_reset, _, _, _, _, _, _, _, _, _, _), + [99] = PINGROUP(99, uim0_present, _, _, _, _, _, _, _, _, _, _), + [100] = PINGROUP(100, uim1_data_mirb, _, _, _, _, _, _, _, _, _, _), + [101] = PINGROUP(101, uim1_clk_mirb, _, _, _, _, _, _, _, _, _, _), + [102] = PINGROUP(102, uim1_reset_mirb, _, _, _, _, _, _, _, _, _, _), + [103] = PINGROUP(103, uim1_present_mirb, _, _, _, _, _, _, _, _, _, _), + [104] = PINGROUP(104, qlink0_request, _, _, _, _, _, _, _, _, _, _), + [105] = PINGROUP(105, qlink0_enable, _, _, _, _, _, _, _, _, _, _), + [106] = PINGROUP(106, qlink0_wmss, _, _, _, _, _, _, _, _, _, _), + [107] = PINGROUP(107, qlink1_request, _, _, _, _, _, _, _, _, _, _), + [108] = PINGROUP(108, qlink1_enable, _, _, _, _, _, _, _, _, _, _), + [109] = PINGROUP(109, qlink1_wmss, _, _, _, _, _, _, _, _, _, _), + [110] = PINGROUP(110, uim1_data_mira, _, _, _, _, _, _, _, _, _, _), + [111] = PINGROUP(111, uim1_clk_mira, _, _, _, _, _, _, _, _, _, _), + [112] = PINGROUP(112, uim1_reset_mira, _, _, _, _, _, _, _, _, _, _), + [113] = PINGROUP(113, uim1_present_mira, _, _, _, _, _, _, _, _, _, _), + [114] = PINGROUP(114, _, _, _, _, _, _, _, _, _, _, _), + [115] = PINGROUP(115, _, _, _, _, _, _, _, _, _, _, _), + [116] = PINGROUP(116, _, _, _, _, _, _, _, _, _, _, _), + [117] = PINGROUP(117, _, _, _, _, _, _, _, _, _, _, _), + [118] = PINGROUP(118, _, _, _, _, _, _, _, _, _, _, _), + [119] = PINGROUP(119, _, _, _, _, _, _, _, _, _, _, _), + [120] = PINGROUP(120, _, _, _, _, _, _, _, _, _, _, _), + [121] = PINGROUP(121, _, _, _, _, _, _, _, _, _, _, _), + [122] = PINGROUP(122, _, _, _, _, _, _, _, _, _, _, _), + [123] = PINGROUP(123, _, _, _, _, _, _, _, _, _, _, _), + [124] = PINGROUP(124, nav_gpio0, _, _, _, _, _, _, _, _, _, _), + [125] = PINGROUP(125, nav_gpio1, usb0_hs, _, _, _, _, _, _, _, _, _), + [126] = PINGROUP(126, _, nav_gpio2, vfr_1, _, _, _, _, _, _, _, _), + [127] = PINGROUP(127, _, _, phase_flag, _, _, _, _, _, _, _, _), + [128] = PINGROUP(128, sdc2_fb_clk, _, _, _, _, _, _, _, _, _, _), + [129] = PINGROUP(129, mdp_vsync, _, _, _, _, _, _, _, _, _, _), + [130] = PINGROUP(130, _, _, _, _, _, _, _, _, _, _, _), + [131] = PINGROUP(131, usb0_phy_ps, _, _, _, _, _, _, _, _, _, _), + [132] = PINGROUP(132, _, _, _, _, _, _, _, _, _, _, egpio), + [133] = PINGROUP(133, ddr_bist_start, _, _, _, _, _, _, _, _, _, egpio), + [134] = PINGROUP(134, _, _, _, _, _, _, _, _, _, _, egpio), + [135] = PINGROUP(135, _, _, _, _, _, _, _, _, _, _, egpio), + [136] = PINGROUP(136, _, _, _, _, _, _, _, _, _, _, egpio), + [137] = PINGROUP(137, ddr_bist_complete, _, _, _, _, _, _, _, _, _, egpio), + [138] = PINGROUP(138, _, phase_flag, qdss_gpio, _, _, _, _, _, _, _, egpio), + [139] = PINGROUP(139, _, phase_flag, qdss_gpio, _, _, _, _, _, _, _, egpio), + [140] = PINGROUP(140, _, phase_flag, qdss_gpio, _, _, _, _, _, _, _, egpio), + [141] = PINGROUP(141, jitter_bist, qdss_gpio, _, _, _, _, _, _, _, _, egpio), + [142] = PINGROUP(142, _, phase_flag, _, _, _, _, _, _, _, _, egpio), + [143] = PINGROUP(143, _, phase_flag, _, _, _, _, _, _, _, _, egpio), + [144] = PINGROUP(144, _, phase_flag, _, _, _, _, _, _, _, _, egpio), + [145] = PINGROUP(145, _, _, _, _, _, _, _, _, _, _, egpio), + [146] = PINGROUP(146, _, _, _, _, _, _, _, _, _, _, egpio), + [147] = PINGROUP(147, _, phase_flag, _, _, _, _, _, _, _, _, egpio), + [148] = PINGROUP(148, _, _, _, _, _, _, _, _, _, _, egpio), + [149] = PINGROUP(149, _, qdss_gpio, _, _, _, _, _, _, _, _, egpio), + [150] = PINGROUP(150, _, qdss_gpio, _, _, _, _, _, _, _, _, egpio), + [151] = PINGROUP(151, _, _, _, _, _, _, _, _, _, _, egpio), + [152] = PINGROUP(152, _, _, _, _, _, _, _, _, _, _, egpio), + [153] = PINGROUP(153, _, _, _, _, _, _, _, _, _, _, egpio), + [154] = PINGROUP(154, _, _, _, _, _, _, _, _, _, _, egpio), + [155] = PINGROUP(155, _, qdss_gpio, _, _, _, _, _, _, _, _, egpio), + [156] = PINGROUP(156, _, qdss_gpio, _, _, _, _, _, _, _, _, egpio), + [157] = PINGROUP(157, _, qdss_gpio, _, _, _, _, _, _, _, _, egpio), + [158] = PINGROUP(158, qdss_gpio, _, _, _, _, _, _, _, _, _, egpio), + [159] = PINGROUP(159, qdss_gpio, _, _, _, _, _, _, _, _, _, egpio), + [160] = PINGROUP(160, qdss_gpio, _, _, _, _, _, _, _, _, _, egpio), + [161] = PINGROUP(161, qdss_gpio, _, _, _, _, _, _, _, _, _, egpio), + [162] = PINGROUP(162, qdss_gpio, _, _, _, _, _, _, _, _, _, egpio), + [163] = PINGROUP(163, qdss_gpio, _, _, _, _, _, _, _, _, _, egpio), + [164] = PINGROUP(164, qdss_gpio, _, _, _, _, _, _, _, _, _, egpio), + [165] = PINGROUP(165, qdss_gpio, _, _, _, _, _, _, _, _, _, egpio), + [166] = PINGROUP(166, qdss_gpio, _, _, _, _, _, _, _, _, _, egpio), + [167] = UFS_RESET(ufs_reset, 0xb4004, 0xb5000), + [168] = SDC_QDSD_PINGROUP(sdc2_clk, 0xab000, 0, 6), + [169] = SDC_QDSD_PINGROUP(sdc2_cmd, 0xab000, 12, 3), + [170] = SDC_QDSD_PINGROUP(sdc2_data, 0xab000, 9, 0), +}; + +static const struct msm_gpio_wakeirq_map milos_pdc_map[] = { + { 0, 122 }, { 3, 95 }, { 4, 100 }, { 6, 52 }, { 7, 119 }, + { 8, 92 }, { 11, 54 }, { 12, 56 }, { 13, 64 }, { 14, 75 }, + { 15, 82 }, { 18, 89 }, { 19, 90 }, { 22, 93 }, { 23, 94 }, + { 26, 91 }, { 27, 57 }, { 30, 138 }, { 31, 96 }, { 32, 67 }, + { 34, 128 }, { 35, 98 }, { 36, 99 }, { 38, 101 }, { 39, 102 }, + { 40, 69 }, { 43, 103 }, { 44, 104 }, { 45, 126 }, { 47, 59 }, + { 48, 106 }, { 51, 107 }, { 52, 108 }, { 54, 110 }, { 55, 140 }, + { 56, 58 }, { 57, 129 }, { 58, 111 }, { 59, 112 }, { 60, 115 }, + { 61, 113 }, { 62, 114 }, { 64, 105 }, { 65, 55 }, { 67, 116 }, + { 68, 117 }, { 70, 120 }, { 71, 121 }, { 72, 97 }, { 73, 109 }, + { 74, 118 }, { 75, 132 }, { 76, 144 }, { 77, 127 }, { 78, 133 }, + { 79, 134 }, { 80, 135 }, { 81, 124 }, { 82, 136 }, { 87, 60 }, + { 91, 123 }, { 92, 125 }, { 95, 139 }, { 99, 53 }, { 103, 61 }, + { 104, 71 }, { 107, 137 }, { 113, 51 }, { 124, 72 }, { 125, 62 }, + { 126, 73 }, { 128, 63 }, { 129, 130 }, { 130, 65 }, { 131, 66 }, + { 133, 68 }, { 136, 70 }, { 143, 78 }, { 144, 79 }, { 145, 142 }, + { 148, 81 }, { 149, 76 }, { 150, 83 }, { 151, 84 }, { 153, 74 }, + { 155, 131 }, { 158, 85 }, { 159, 77 }, { 161, 80 }, { 162, 143 }, + { 163, 86 }, { 164, 87 }, { 166, 88 }, +}; + +static const struct msm_pinctrl_soc_data milos_tlmm = { + .pins = milos_pins, + .npins = ARRAY_SIZE(milos_pins), + .functions = milos_functions, + .nfunctions = ARRAY_SIZE(milos_functions), + .groups = milos_groups, + .ngroups = ARRAY_SIZE(milos_groups), + .ngpios = 168, + .wakeirq_map = milos_pdc_map, + .nwakeirq_map = ARRAY_SIZE(milos_pdc_map), + .egpio_func = 11, +}; + +static int milos_tlmm_probe(struct platform_device *pdev) +{ + return msm_pinctrl_probe(pdev, &milos_tlmm); +} + +static const struct of_device_id milos_tlmm_of_match[] = { + { .compatible = "qcom,milos-tlmm" }, + { /* sentinel */ } +}; + +static struct platform_driver milos_tlmm_driver = { + .driver = { + .name = "milos-tlmm", + .of_match_table = milos_tlmm_of_match, + }, + .probe = milos_tlmm_probe, +}; + +static int __init milos_tlmm_init(void) +{ + return platform_driver_register(&milos_tlmm_driver); +} +arch_initcall(milos_tlmm_init); + +static void __exit milos_tlmm_exit(void) +{ + platform_driver_unregister(&milos_tlmm_driver); +} +module_exit(milos_tlmm_exit); + +MODULE_DESCRIPTION("QTI Milos TLMM driver"); +MODULE_LICENSE("GPL"); +MODULE_DEVICE_TABLE(of, milos_tlmm_of_match); diff --git a/drivers/pinctrl/qcom/pinctrl-msm.c b/drivers/pinctrl/qcom/pinctrl-msm.c index f713c80d7f3e..67525d542c5b 100644 --- a/drivers/pinctrl/qcom/pinctrl-msm.c +++ b/drivers/pinctrl/qcom/pinctrl-msm.c @@ -31,6 +31,7 @@ #include "../core.h" #include "../pinconf.h" #include "../pinctrl-utils.h" +#include "../pinmux.h" #include "pinctrl-msm.h" @@ -150,33 +151,6 @@ static int msm_pinmux_request(struct pinctrl_dev *pctldev, unsigned offset) return gpiochip_line_is_valid(chip, offset) ? 0 : -EINVAL; } -static int msm_get_functions_count(struct pinctrl_dev *pctldev) -{ - struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); - - return pctrl->soc->nfunctions; -} - -static const char *msm_get_function_name(struct pinctrl_dev *pctldev, - unsigned function) -{ - struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); - - return pctrl->soc->functions[function].name; -} - -static int msm_get_function_groups(struct pinctrl_dev *pctldev, - unsigned function, - const char * const **groups, - unsigned * const num_groups) -{ - struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); - - *groups = pctrl->soc->functions[function].groups; - *num_groups = pctrl->soc->functions[function].ngroups; - return 0; -} - static int msm_pinmux_set_mux(struct pinctrl_dev *pctldev, unsigned function, unsigned group) @@ -288,11 +262,13 @@ static int msm_pinmux_request_gpio(struct pinctrl_dev *pctldev, static const struct pinmux_ops msm_pinmux_ops = { .request = msm_pinmux_request, - .get_functions_count = msm_get_functions_count, - .get_function_name = msm_get_function_name, - .get_function_groups = msm_get_function_groups, + .get_functions_count = pinmux_generic_get_function_count, + .get_function_name = pinmux_generic_get_function_name, + .get_function_groups = pinmux_generic_get_function_groups, + .function_is_gpio = pinmux_generic_function_is_gpio, .gpio_request_enable = msm_pinmux_request_gpio, .set_mux = msm_pinmux_set_mux, + .strict = true, }; static int msm_config_reg(struct msm_pinctrl *pctrl, @@ -319,7 +295,7 @@ static int msm_config_reg(struct msm_pinctrl *pctrl, *bit = g->drv_bit; *mask = 7; break; - case PIN_CONFIG_OUTPUT: + case PIN_CONFIG_LEVEL: case PIN_CONFIG_INPUT_ENABLE: case PIN_CONFIG_OUTPUT_ENABLE: *bit = g->oe_bit; @@ -409,7 +385,7 @@ static int msm_config_group_get(struct pinctrl_dev *pctldev, case PIN_CONFIG_DRIVE_STRENGTH: arg = msm_regval_to_drive(arg); break; - case PIN_CONFIG_OUTPUT: + case PIN_CONFIG_LEVEL: /* Pin is not output */ if (!arg) return -EINVAL; @@ -488,7 +464,7 @@ static int msm_config_group_set(struct pinctrl_dev *pctldev, else arg = (arg / 2) - 1; break; - case PIN_CONFIG_OUTPUT: + case PIN_CONFIG_LEVEL: /* set output value */ raw_spin_lock_irqsave(&pctrl->lock, flags); val = msm_readl_io(pctrl, g); @@ -792,7 +768,7 @@ static const struct gpio_chip msm_gpio_template = { .direction_output = msm_gpio_direction_output, .get_direction = msm_gpio_get_direction, .get = msm_gpio_get, - .set_rv = msm_gpio_set, + .set = msm_gpio_set, .request = gpiochip_generic_request, .free = gpiochip_generic_free, .dbg_show = msm_gpio_dbg_show, @@ -1552,6 +1528,7 @@ EXPORT_SYMBOL(msm_pinctrl_dev_pm_ops); int msm_pinctrl_probe(struct platform_device *pdev, const struct msm_pinctrl_soc_data *soc_data) { + const struct pinfunction *func; struct msm_pinctrl *pctrl; struct resource *res; int ret; @@ -1606,6 +1583,14 @@ int msm_pinctrl_probe(struct platform_device *pdev, return PTR_ERR(pctrl->pctrl); } + for (i = 0; i < soc_data->nfunctions; i++) { + func = &soc_data->functions[i]; + + ret = pinmux_generic_add_pinfunction(pctrl->pctrl, func, NULL); + if (ret < 0) + return ret; + } + ret = msm_gpio_init(pctrl); if (ret) return ret; diff --git a/drivers/pinctrl/qcom/pinctrl-msm.h b/drivers/pinctrl/qcom/pinctrl-msm.h index d7dc0947bb16..4625fa5320a9 100644 --- a/drivers/pinctrl/qcom/pinctrl-msm.h +++ b/drivers/pinctrl/qcom/pinctrl-msm.h @@ -29,6 +29,11 @@ struct pinctrl_pin_desc; fname##_groups, \ ARRAY_SIZE(fname##_groups)) +#define MSM_GPIO_PIN_FUNCTION(fname) \ + [msm_mux_##fname] = PINCTRL_GPIO_PINFUNCTION(#fname, \ + fname##_groups, \ + ARRAY_SIZE(fname##_groups)) + #define QCA_PIN_FUNCTION(fname) \ [qca_mux_##fname] = PINCTRL_PINFUNCTION(#fname, \ fname##_groups, \ diff --git a/drivers/pinctrl/qcom/pinctrl-msm8226.c b/drivers/pinctrl/qcom/pinctrl-msm8226.c index f9a957347340..a81aa092ef12 100644 --- a/drivers/pinctrl/qcom/pinctrl-msm8226.c +++ b/drivers/pinctrl/qcom/pinctrl-msm8226.c @@ -483,7 +483,7 @@ static const struct pinfunction msm8226_functions[] = { MSM_PIN_FUNCTION(cci_i2c0), MSM_PIN_FUNCTION(gp0_clk), MSM_PIN_FUNCTION(gp1_clk), - MSM_PIN_FUNCTION(gpio), + MSM_GPIO_PIN_FUNCTION(gpio), MSM_PIN_FUNCTION(sdc3), MSM_PIN_FUNCTION(wlan), }; diff --git a/drivers/pinctrl/qcom/pinctrl-msm8660.c b/drivers/pinctrl/qcom/pinctrl-msm8660.c index 4dbc19ffd80e..5ded00396cd9 100644 --- a/drivers/pinctrl/qcom/pinctrl-msm8660.c +++ b/drivers/pinctrl/qcom/pinctrl-msm8660.c @@ -714,7 +714,7 @@ static const char * const ebi2_groups[] = { }; static const struct pinfunction msm8660_functions[] = { - MSM_PIN_FUNCTION(gpio), + MSM_GPIO_PIN_FUNCTION(gpio), MSM_PIN_FUNCTION(cam_mclk), MSM_PIN_FUNCTION(dsub), MSM_PIN_FUNCTION(ext_gps), diff --git a/drivers/pinctrl/qcom/pinctrl-msm8909.c b/drivers/pinctrl/qcom/pinctrl-msm8909.c index 0aa4f77b774f..544a52fb8f3d 100644 --- a/drivers/pinctrl/qcom/pinctrl-msm8909.c +++ b/drivers/pinctrl/qcom/pinctrl-msm8909.c @@ -696,7 +696,7 @@ static const struct pinfunction msm8909_functions[] = { MSM_PIN_FUNCTION(gcc_gp3_clk_a), MSM_PIN_FUNCTION(gcc_gp3_clk_b), MSM_PIN_FUNCTION(gcc_plltest), - MSM_PIN_FUNCTION(gpio), + MSM_GPIO_PIN_FUNCTION(gpio), MSM_PIN_FUNCTION(gsm0_tx), MSM_PIN_FUNCTION(ldo_en), MSM_PIN_FUNCTION(ldo_update), diff --git a/drivers/pinctrl/qcom/pinctrl-msm8916.c b/drivers/pinctrl/qcom/pinctrl-msm8916.c index 0dfc6dd33d58..b1b6934bb4b6 100644 --- a/drivers/pinctrl/qcom/pinctrl-msm8916.c +++ b/drivers/pinctrl/qcom/pinctrl-msm8916.c @@ -743,7 +743,7 @@ static const struct pinfunction msm8916_functions[] = { MSM_PIN_FUNCTION(gcc_gp2_clk_b), MSM_PIN_FUNCTION(gcc_gp3_clk_a), MSM_PIN_FUNCTION(gcc_gp3_clk_b), - MSM_PIN_FUNCTION(gpio), + MSM_GPIO_PIN_FUNCTION(gpio), MSM_PIN_FUNCTION(gsm0_tx0), MSM_PIN_FUNCTION(gsm0_tx1), MSM_PIN_FUNCTION(gsm1_tx0), diff --git a/drivers/pinctrl/qcom/pinctrl-msm8917.c b/drivers/pinctrl/qcom/pinctrl-msm8917.c index 2e1a94ab18b2..f23d92d6615b 100644 --- a/drivers/pinctrl/qcom/pinctrl-msm8917.c +++ b/drivers/pinctrl/qcom/pinctrl-msm8917.c @@ -1302,7 +1302,7 @@ static const struct pinfunction msm8917_functions[] = { MSM_PIN_FUNCTION(gcc_gp3_clk_b), MSM_PIN_FUNCTION(gcc_plltest), MSM_PIN_FUNCTION(gcc_tlmm), - MSM_PIN_FUNCTION(gpio), + MSM_GPIO_PIN_FUNCTION(gpio), MSM_PIN_FUNCTION(gsm0_tx), MSM_PIN_FUNCTION(key_focus), MSM_PIN_FUNCTION(key_snapshot), diff --git a/drivers/pinctrl/qcom/pinctrl-msm8953.c b/drivers/pinctrl/qcom/pinctrl-msm8953.c index 956383341a7a..67db062fdf56 100644 --- a/drivers/pinctrl/qcom/pinctrl-msm8953.c +++ b/drivers/pinctrl/qcom/pinctrl-msm8953.c @@ -1533,7 +1533,7 @@ static const struct pinfunction msm8953_functions[] = { MSM_PIN_FUNCTION(gcc_gp3_clk_b), MSM_PIN_FUNCTION(gcc_plltest), MSM_PIN_FUNCTION(gcc_tlmm), - MSM_PIN_FUNCTION(gpio), + MSM_GPIO_PIN_FUNCTION(gpio), MSM_PIN_FUNCTION(gsm0_tx), MSM_PIN_FUNCTION(gsm1_tx), MSM_PIN_FUNCTION(gyro_int), diff --git a/drivers/pinctrl/qcom/pinctrl-msm8960.c b/drivers/pinctrl/qcom/pinctrl-msm8960.c index a937ea867de7..2fb15208aba0 100644 --- a/drivers/pinctrl/qcom/pinctrl-msm8960.c +++ b/drivers/pinctrl/qcom/pinctrl-msm8960.c @@ -974,7 +974,7 @@ static const struct pinfunction msm8960_functions[] = { MSM_PIN_FUNCTION(gp_pdm_1b), MSM_PIN_FUNCTION(gp_pdm_2a), MSM_PIN_FUNCTION(gp_pdm_2b), - MSM_PIN_FUNCTION(gpio), + MSM_GPIO_PIN_FUNCTION(gpio), MSM_PIN_FUNCTION(gsbi1), MSM_PIN_FUNCTION(gsbi1_spi_cs1_n), MSM_PIN_FUNCTION(gsbi1_spi_cs2a_n), diff --git a/drivers/pinctrl/qcom/pinctrl-msm8976.c b/drivers/pinctrl/qcom/pinctrl-msm8976.c index 3bcb03387781..345539b9e696 100644 --- a/drivers/pinctrl/qcom/pinctrl-msm8976.c +++ b/drivers/pinctrl/qcom/pinctrl-msm8976.c @@ -812,7 +812,7 @@ static const char * const ss_switch_groups[] = { }; static const struct pinfunction msm8976_functions[] = { - MSM_PIN_FUNCTION(gpio), + MSM_GPIO_PIN_FUNCTION(gpio), MSM_PIN_FUNCTION(blsp_spi1), MSM_PIN_FUNCTION(smb_int), MSM_PIN_FUNCTION(blsp_i2c1), diff --git a/drivers/pinctrl/qcom/pinctrl-msm8994.c b/drivers/pinctrl/qcom/pinctrl-msm8994.c index 7a3b6cbccb68..94e042d1f4b2 100644 --- a/drivers/pinctrl/qcom/pinctrl-msm8994.c +++ b/drivers/pinctrl/qcom/pinctrl-msm8994.c @@ -1071,7 +1071,7 @@ static const struct pinfunction msm8994_functions[] = { MSM_PIN_FUNCTION(uim2), MSM_PIN_FUNCTION(uim3), MSM_PIN_FUNCTION(uim4), - MSM_PIN_FUNCTION(gpio), + MSM_GPIO_PIN_FUNCTION(gpio), }; static const struct msm_pingroup msm8994_groups[] = { diff --git a/drivers/pinctrl/qcom/pinctrl-msm8996.c b/drivers/pinctrl/qcom/pinctrl-msm8996.c index d86d83106d3b..e5b55693d023 100644 --- a/drivers/pinctrl/qcom/pinctrl-msm8996.c +++ b/drivers/pinctrl/qcom/pinctrl-msm8996.c @@ -1532,7 +1532,7 @@ static const struct pinfunction msm8996_functions[] = { MSM_PIN_FUNCTION(gcc_gp2_clk_b), MSM_PIN_FUNCTION(gcc_gp3_clk_a), MSM_PIN_FUNCTION(gcc_gp3_clk_b), - MSM_PIN_FUNCTION(gpio), + MSM_GPIO_PIN_FUNCTION(gpio), MSM_PIN_FUNCTION(gsm_tx), MSM_PIN_FUNCTION(hdmi_cec), MSM_PIN_FUNCTION(hdmi_ddc), diff --git a/drivers/pinctrl/qcom/pinctrl-msm8998.c b/drivers/pinctrl/qcom/pinctrl-msm8998.c index 1daee815888f..b727593af34a 100644 --- a/drivers/pinctrl/qcom/pinctrl-msm8998.c +++ b/drivers/pinctrl/qcom/pinctrl-msm8998.c @@ -1160,7 +1160,7 @@ static const char * const mss_lte_groups[] = { }; static const struct pinfunction msm8998_functions[] = { - MSM_PIN_FUNCTION(gpio), + MSM_GPIO_PIN_FUNCTION(gpio), MSM_PIN_FUNCTION(adsp_ext), MSM_PIN_FUNCTION(agera_pll), MSM_PIN_FUNCTION(atest_char), diff --git a/drivers/pinctrl/qcom/pinctrl-msm8x74.c b/drivers/pinctrl/qcom/pinctrl-msm8x74.c index 8253aa25775b..202bec003e96 100644 --- a/drivers/pinctrl/qcom/pinctrl-msm8x74.c +++ b/drivers/pinctrl/qcom/pinctrl-msm8x74.c @@ -778,7 +778,7 @@ static const char * const slimbus_groups[] = { "gpio70", "gpio71" }; static const char * const hsic_ctl_groups[] = { "hsic_strobe", "hsic_data" }; static const struct pinfunction msm8x74_functions[] = { - MSM_PIN_FUNCTION(gpio), + MSM_GPIO_PIN_FUNCTION(gpio), MSM_PIN_FUNCTION(cci_i2c0), MSM_PIN_FUNCTION(cci_i2c1), MSM_PIN_FUNCTION(uim1), diff --git a/drivers/pinctrl/qcom/pinctrl-qcm2290.c b/drivers/pinctrl/qcom/pinctrl-qcm2290.c index eeeec6434f6a..38200957451e 100644 --- a/drivers/pinctrl/qcom/pinctrl-qcm2290.c +++ b/drivers/pinctrl/qcom/pinctrl-qcm2290.c @@ -870,11 +870,11 @@ static const struct pinfunction qcm2290_functions[] = { MSM_PIN_FUNCTION(ddr_pxi1), MSM_PIN_FUNCTION(ddr_pxi2), MSM_PIN_FUNCTION(ddr_pxi3), - MSM_PIN_FUNCTION(egpio), + MSM_GPIO_PIN_FUNCTION(egpio), MSM_PIN_FUNCTION(gcc_gp1), MSM_PIN_FUNCTION(gcc_gp2), MSM_PIN_FUNCTION(gcc_gp3), - MSM_PIN_FUNCTION(gpio), + MSM_GPIO_PIN_FUNCTION(gpio), MSM_PIN_FUNCTION(gp_pdm0), MSM_PIN_FUNCTION(gp_pdm1), MSM_PIN_FUNCTION(gp_pdm2), diff --git a/drivers/pinctrl/qcom/pinctrl-qcs404.c b/drivers/pinctrl/qcom/pinctrl-qcs404.c index 54e3b4435349..0b8db2c7e58a 100644 --- a/drivers/pinctrl/qcom/pinctrl-qcs404.c +++ b/drivers/pinctrl/qcom/pinctrl-qcs404.c @@ -1296,7 +1296,7 @@ static const char * const i2s_3_ws_a_groups[] = { }; static const struct pinfunction qcs404_functions[] = { - MSM_PIN_FUNCTION(gpio), + MSM_GPIO_PIN_FUNCTION(gpio), MSM_PIN_FUNCTION(hdmi_tx), MSM_PIN_FUNCTION(hdmi_ddc), MSM_PIN_FUNCTION(blsp_uart_tx_a2), diff --git a/drivers/pinctrl/qcom/pinctrl-qcs615.c b/drivers/pinctrl/qcom/pinctrl-qcs615.c index 2a943bc46a62..4dfa820d4e77 100644 --- a/drivers/pinctrl/qcom/pinctrl-qcs615.c +++ b/drivers/pinctrl/qcom/pinctrl-qcs615.c @@ -819,7 +819,7 @@ static const char *const wsa_data_groups[] = { }; static const struct pinfunction qcs615_functions[] = { - MSM_PIN_FUNCTION(gpio), + MSM_GPIO_PIN_FUNCTION(gpio), MSM_PIN_FUNCTION(adsp_ext), MSM_PIN_FUNCTION(agera_pll), MSM_PIN_FUNCTION(aoss_cti), diff --git a/drivers/pinctrl/qcom/pinctrl-qcs8300.c b/drivers/pinctrl/qcom/pinctrl-qcs8300.c index d6437e26392b..f1af1a620684 100644 --- a/drivers/pinctrl/qcom/pinctrl-qcs8300.c +++ b/drivers/pinctrl/qcom/pinctrl-qcs8300.c @@ -929,7 +929,7 @@ static const char *const vsense_trigger_groups[] = { }; static const struct pinfunction qcs8300_functions[] = { - MSM_PIN_FUNCTION(gpio), + MSM_GPIO_PIN_FUNCTION(gpio), MSM_PIN_FUNCTION(aoss_cti), MSM_PIN_FUNCTION(atest_char), MSM_PIN_FUNCTION(atest_usb2), @@ -949,7 +949,7 @@ static const struct pinfunction qcs8300_functions[] = { MSM_PIN_FUNCTION(edp0_hot), MSM_PIN_FUNCTION(edp0_lcd), MSM_PIN_FUNCTION(edp1_lcd), - MSM_PIN_FUNCTION(egpio), + MSM_GPIO_PIN_FUNCTION(egpio), MSM_PIN_FUNCTION(emac0_mcg0), MSM_PIN_FUNCTION(emac0_mcg1), MSM_PIN_FUNCTION(emac0_mcg2), diff --git a/drivers/pinctrl/qcom/pinctrl-qdu1000.c b/drivers/pinctrl/qcom/pinctrl-qdu1000.c index eacb89fa3888..7c535698a780 100644 --- a/drivers/pinctrl/qcom/pinctrl-qdu1000.c +++ b/drivers/pinctrl/qcom/pinctrl-qdu1000.c @@ -904,7 +904,7 @@ static const char * const vsense_trigger_groups[] = { }; static const struct pinfunction qdu1000_functions[] = { - MSM_PIN_FUNCTION(gpio), + MSM_GPIO_PIN_FUNCTION(gpio), MSM_PIN_FUNCTION(cmo_pri), MSM_PIN_FUNCTION(si5518_int), MSM_PIN_FUNCTION(atest_char), diff --git a/drivers/pinctrl/qcom/pinctrl-sa8775p.c b/drivers/pinctrl/qcom/pinctrl-sa8775p.c index 1b62eb3e6620..53f28b9c49ba 100644 --- a/drivers/pinctrl/qcom/pinctrl-sa8775p.c +++ b/drivers/pinctrl/qcom/pinctrl-sa8775p.c @@ -1181,7 +1181,7 @@ static const char * const vsense_trigger_groups[] = { }; static const struct pinfunction sa8775p_functions[] = { - MSM_PIN_FUNCTION(gpio), + MSM_GPIO_PIN_FUNCTION(gpio), MSM_PIN_FUNCTION(atest_char), MSM_PIN_FUNCTION(atest_usb2), MSM_PIN_FUNCTION(audio_ref), @@ -1217,7 +1217,7 @@ static const struct pinfunction sa8775p_functions[] = { MSM_PIN_FUNCTION(edp2_lcd), MSM_PIN_FUNCTION(edp3_hot), MSM_PIN_FUNCTION(edp3_lcd), - MSM_PIN_FUNCTION(egpio), + MSM_GPIO_PIN_FUNCTION(egpio), MSM_PIN_FUNCTION(emac0_mcg0), MSM_PIN_FUNCTION(emac0_mcg1), MSM_PIN_FUNCTION(emac0_mcg2), diff --git a/drivers/pinctrl/qcom/pinctrl-sar2130p.c b/drivers/pinctrl/qcom/pinctrl-sar2130p.c index 3dd1b5e5cfee..4a53f4ee2041 100644 --- a/drivers/pinctrl/qcom/pinctrl-sar2130p.c +++ b/drivers/pinctrl/qcom/pinctrl-sar2130p.c @@ -1128,7 +1128,7 @@ static const char * const vsense_trigger_groups[] = { }; static const struct pinfunction sar2130p_functions[] = { - MSM_PIN_FUNCTION(gpio), + MSM_GPIO_PIN_FUNCTION(gpio), MSM_PIN_FUNCTION(qup0), MSM_PIN_FUNCTION(ibi_i3c), MSM_PIN_FUNCTION(jitter_bist), diff --git a/drivers/pinctrl/qcom/pinctrl-sc7180.c b/drivers/pinctrl/qcom/pinctrl-sc7180.c index c43fe10b71ad..3eae51472b13 100644 --- a/drivers/pinctrl/qcom/pinctrl-sc7180.c +++ b/drivers/pinctrl/qcom/pinctrl-sc7180.c @@ -903,7 +903,7 @@ static const struct pinfunction sc7180_functions[] = { MSM_PIN_FUNCTION(gcc_gp1), MSM_PIN_FUNCTION(gcc_gp2), MSM_PIN_FUNCTION(gcc_gp3), - MSM_PIN_FUNCTION(gpio), + MSM_GPIO_PIN_FUNCTION(gpio), MSM_PIN_FUNCTION(gp_pdm0), MSM_PIN_FUNCTION(gp_pdm1), MSM_PIN_FUNCTION(gp_pdm2), diff --git a/drivers/pinctrl/qcom/pinctrl-sc7280.c b/drivers/pinctrl/qcom/pinctrl-sc7280.c index 1b070e9d41f5..44e09608aad0 100644 --- a/drivers/pinctrl/qcom/pinctrl-sc7280.c +++ b/drivers/pinctrl/qcom/pinctrl-sc7280.c @@ -1153,11 +1153,11 @@ static const struct pinfunction sc7280_functions[] = { MSM_PIN_FUNCTION(dp_lcd), MSM_PIN_FUNCTION(edp_hot), MSM_PIN_FUNCTION(edp_lcd), - MSM_PIN_FUNCTION(egpio), + MSM_GPIO_PIN_FUNCTION(egpio), MSM_PIN_FUNCTION(gcc_gp1), MSM_PIN_FUNCTION(gcc_gp2), MSM_PIN_FUNCTION(gcc_gp3), - MSM_PIN_FUNCTION(gpio), + MSM_GPIO_PIN_FUNCTION(gpio), MSM_PIN_FUNCTION(host2wlan_sol), MSM_PIN_FUNCTION(ibi_i3c), MSM_PIN_FUNCTION(jitter_bist), diff --git a/drivers/pinctrl/qcom/pinctrl-sc8180x.c b/drivers/pinctrl/qcom/pinctrl-sc8180x.c index 26dd165d1543..d9f9e3dd9dd1 100644 --- a/drivers/pinctrl/qcom/pinctrl-sc8180x.c +++ b/drivers/pinctrl/qcom/pinctrl-sc8180x.c @@ -1272,7 +1272,7 @@ static const struct pinfunction sc8180x_functions[] = { MSM_PIN_FUNCTION(gcc_gp3), MSM_PIN_FUNCTION(gcc_gp4), MSM_PIN_FUNCTION(gcc_gp5), - MSM_PIN_FUNCTION(gpio), + MSM_GPIO_PIN_FUNCTION(gpio), MSM_PIN_FUNCTION(gps), MSM_PIN_FUNCTION(grfc), MSM_PIN_FUNCTION(hs1_mi2s), @@ -1634,7 +1634,7 @@ static int sc8180x_pinctrl_add_tile_resources(struct platform_device *pdev) return 0; /* Allocate for new resources */ - nres = devm_kzalloc(&pdev->dev, sizeof(*nres) * nres_num, GFP_KERNEL); + nres = devm_kcalloc(&pdev->dev, nres_num, sizeof(*nres), GFP_KERNEL); if (!nres) return -ENOMEM; diff --git a/drivers/pinctrl/qcom/pinctrl-sc8280xp.c b/drivers/pinctrl/qcom/pinctrl-sc8280xp.c index 6ccd7e5648d4..cf8297e8b8f8 100644 --- a/drivers/pinctrl/qcom/pinctrl-sc8280xp.c +++ b/drivers/pinctrl/qcom/pinctrl-sc8280xp.c @@ -1506,7 +1506,7 @@ static const struct pinfunction sc8280xp_functions[] = { MSM_PIN_FUNCTION(edp2_lcd), MSM_PIN_FUNCTION(edp3_lcd), MSM_PIN_FUNCTION(edp_hot), - MSM_PIN_FUNCTION(egpio), + MSM_GPIO_PIN_FUNCTION(egpio), MSM_PIN_FUNCTION(emac0_dll), MSM_PIN_FUNCTION(emac0_mcg0), MSM_PIN_FUNCTION(emac0_mcg1), @@ -1527,7 +1527,7 @@ static const struct pinfunction sc8280xp_functions[] = { MSM_PIN_FUNCTION(gcc_gp3), MSM_PIN_FUNCTION(gcc_gp4), MSM_PIN_FUNCTION(gcc_gp5), - MSM_PIN_FUNCTION(gpio), + MSM_GPIO_PIN_FUNCTION(gpio), MSM_PIN_FUNCTION(hs1_mi2s), MSM_PIN_FUNCTION(hs2_mi2s), MSM_PIN_FUNCTION(hs3_mi2s), diff --git a/drivers/pinctrl/qcom/pinctrl-sdm660-lpass-lpi.c b/drivers/pinctrl/qcom/pinctrl-sdm660-lpass-lpi.c new file mode 100644 index 000000000000..d93af5f0e8d3 --- /dev/null +++ b/drivers/pinctrl/qcom/pinctrl-sdm660-lpass-lpi.c @@ -0,0 +1,160 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * This driver is solely based on the limited information in downstream code. + * Any verification with schematics would be greatly appreciated. + * + * Copyright (c) 2023, Richard Acayan. All rights reserved. + */ + +#include <linux/kernel.h> +#include <linux/module.h> +#include <linux/of.h> +#include <linux/platform_device.h> +#include <linux/pinctrl/pinctrl.h> + +#include "pinctrl-lpass-lpi.h" + +enum lpass_lpi_functions { + LPI_MUX_comp_rx, + LPI_MUX_dmic1_clk, + LPI_MUX_dmic1_data, + LPI_MUX_dmic2_clk, + LPI_MUX_dmic2_data, + LPI_MUX_mclk0, + LPI_MUX_pdm_tx, + LPI_MUX_pdm_clk, + LPI_MUX_pdm_rx, + LPI_MUX_pdm_sync, + + LPI_MUX_gpio, + LPI_MUX__, +}; + +static const struct pinctrl_pin_desc sdm660_lpi_pinctrl_pins[] = { + PINCTRL_PIN(0, "gpio0"), + PINCTRL_PIN(1, "gpio1"), + PINCTRL_PIN(2, "gpio2"), + PINCTRL_PIN(3, "gpio3"), + PINCTRL_PIN(4, "gpio4"), + PINCTRL_PIN(5, "gpio5"), + PINCTRL_PIN(6, "gpio6"), + PINCTRL_PIN(7, "gpio7"), + PINCTRL_PIN(8, "gpio8"), + PINCTRL_PIN(9, "gpio9"), + PINCTRL_PIN(10, "gpio10"), + PINCTRL_PIN(11, "gpio11"), + PINCTRL_PIN(12, "gpio12"), + PINCTRL_PIN(13, "gpio13"), + PINCTRL_PIN(14, "gpio14"), + PINCTRL_PIN(15, "gpio15"), + PINCTRL_PIN(16, "gpio16"), + PINCTRL_PIN(17, "gpio17"), + PINCTRL_PIN(18, "gpio18"), + PINCTRL_PIN(19, "gpio19"), + PINCTRL_PIN(20, "gpio20"), + PINCTRL_PIN(21, "gpio21"), + PINCTRL_PIN(22, "gpio22"), + PINCTRL_PIN(23, "gpio23"), + PINCTRL_PIN(24, "gpio24"), + PINCTRL_PIN(25, "gpio25"), + PINCTRL_PIN(26, "gpio26"), + PINCTRL_PIN(27, "gpio27"), + PINCTRL_PIN(28, "gpio28"), + PINCTRL_PIN(29, "gpio29"), + PINCTRL_PIN(30, "gpio30"), + PINCTRL_PIN(31, "gpio31"), +}; + +static const char * const comp_rx_groups[] = { "gpio22", "gpio24" }; +static const char * const dmic1_clk_groups[] = { "gpio26" }; +static const char * const dmic1_data_groups[] = { "gpio27" }; +static const char * const dmic2_clk_groups[] = { "gpio28" }; +static const char * const dmic2_data_groups[] = { "gpio29" }; +static const char * const mclk0_groups[] = { "gpio18" }; +static const char * const pdm_tx_groups[] = { "gpio20" }; +static const char * const pdm_clk_groups[] = { "gpio18" }; +static const char * const pdm_rx_groups[] = { "gpio21", "gpio23", "gpio25" }; +static const char * const pdm_sync_groups[] = { "gpio19" }; + +const struct lpi_pingroup sdm660_lpi_pinctrl_groups[] = { + LPI_PINGROUP_OFFSET(0, LPI_NO_SLEW, _, _, _, _, 0x0000), + LPI_PINGROUP_OFFSET(1, LPI_NO_SLEW, _, _, _, _, 0x1000), + LPI_PINGROUP_OFFSET(2, LPI_NO_SLEW, _, _, _, _, 0x2000), + LPI_PINGROUP_OFFSET(3, LPI_NO_SLEW, _, _, _, _, 0x2010), + LPI_PINGROUP_OFFSET(4, LPI_NO_SLEW, _, _, _, _, 0x3000), + LPI_PINGROUP_OFFSET(5, LPI_NO_SLEW, _, _, _, _, 0x3010), + LPI_PINGROUP_OFFSET(6, LPI_NO_SLEW, _, _, _, _, 0x4000), + LPI_PINGROUP_OFFSET(7, LPI_NO_SLEW, _, _, _, _, 0x4010), + LPI_PINGROUP_OFFSET(8, LPI_NO_SLEW, _, _, _, _, 0x5000), + LPI_PINGROUP_OFFSET(9, LPI_NO_SLEW, _, _, _, _, 0x5010), + LPI_PINGROUP_OFFSET(10, LPI_NO_SLEW, _, _, _, _, 0x5020), + LPI_PINGROUP_OFFSET(11, LPI_NO_SLEW, _, _, _, _, 0x5030), + LPI_PINGROUP_OFFSET(12, LPI_NO_SLEW, _, _, _, _, 0x6000), + LPI_PINGROUP_OFFSET(13, LPI_NO_SLEW, _, _, _, _, 0x6010), + LPI_PINGROUP_OFFSET(14, LPI_NO_SLEW, _, _, _, _, 0x7000), + LPI_PINGROUP_OFFSET(15, LPI_NO_SLEW, _, _, _, _, 0x7010), + LPI_PINGROUP_OFFSET(16, LPI_NO_SLEW, _, _, _, _, 0x5040), + LPI_PINGROUP_OFFSET(17, LPI_NO_SLEW, _, _, _, _, 0x5050), + + LPI_PINGROUP_OFFSET(18, LPI_NO_SLEW, pdm_clk, mclk0, _, _, 0x8000), + LPI_PINGROUP_OFFSET(19, LPI_NO_SLEW, pdm_sync, _, _, _, 0x8010), + LPI_PINGROUP_OFFSET(20, LPI_NO_SLEW, pdm_tx, _, _, _, 0x8020), + LPI_PINGROUP_OFFSET(21, LPI_NO_SLEW, pdm_rx, _, _, _, 0x8030), + LPI_PINGROUP_OFFSET(22, LPI_NO_SLEW, comp_rx, _, _, _, 0x8040), + LPI_PINGROUP_OFFSET(23, LPI_NO_SLEW, pdm_rx, _, _, _, 0x8050), + LPI_PINGROUP_OFFSET(24, LPI_NO_SLEW, comp_rx, _, _, _, 0x8060), + LPI_PINGROUP_OFFSET(25, LPI_NO_SLEW, pdm_rx, _, _, _, 0x8070), + LPI_PINGROUP_OFFSET(26, LPI_NO_SLEW, dmic1_clk, _, _, _, 0x9000), + LPI_PINGROUP_OFFSET(27, LPI_NO_SLEW, dmic1_data, _, _, _, 0x9010), + LPI_PINGROUP_OFFSET(28, LPI_NO_SLEW, dmic2_clk, _, _, _, 0xa000), + LPI_PINGROUP_OFFSET(29, LPI_NO_SLEW, dmic2_data, _, _, _, 0xa010), + + LPI_PINGROUP_OFFSET(30, LPI_NO_SLEW, _, _, _, _, 0xb000), + LPI_PINGROUP_OFFSET(31, LPI_NO_SLEW, _, _, _, _, 0xb010), +}; + +const struct lpi_function sdm660_lpi_pinctrl_functions[] = { + LPI_FUNCTION(comp_rx), + LPI_FUNCTION(dmic1_clk), + LPI_FUNCTION(dmic1_data), + LPI_FUNCTION(dmic2_clk), + LPI_FUNCTION(dmic2_data), + LPI_FUNCTION(mclk0), + LPI_FUNCTION(pdm_tx), + LPI_FUNCTION(pdm_clk), + LPI_FUNCTION(pdm_rx), + LPI_FUNCTION(pdm_sync), +}; + +static const struct lpi_pinctrl_variant_data sdm660_lpi_pinctrl_data = { + .pins = sdm660_lpi_pinctrl_pins, + .npins = ARRAY_SIZE(sdm660_lpi_pinctrl_pins), + .groups = sdm660_lpi_pinctrl_groups, + .ngroups = ARRAY_SIZE(sdm660_lpi_pinctrl_groups), + .functions = sdm660_lpi_pinctrl_functions, + .nfunctions = ARRAY_SIZE(sdm660_lpi_pinctrl_functions), + .flags = LPI_FLAG_SLEW_RATE_SAME_REG | LPI_FLAG_USE_PREDEFINED_PIN_OFFSET +}; + +static const struct of_device_id sdm660_lpi_pinctrl_of_match[] = { + { + .compatible = "qcom,sdm660-lpass-lpi-pinctrl", + .data = &sdm660_lpi_pinctrl_data, + }, + { } +}; +MODULE_DEVICE_TABLE(of, sdm660_lpi_pinctrl_of_match); + +static struct platform_driver sdm660_lpi_pinctrl_driver = { + .driver = { + .name = "qcom-sdm660-lpass-lpi-pinctrl", + .of_match_table = sdm660_lpi_pinctrl_of_match, + }, + .probe = lpi_pinctrl_probe, + .remove = lpi_pinctrl_remove, +}; +module_platform_driver(sdm660_lpi_pinctrl_driver); + +MODULE_AUTHOR("Richard Acayan <mailingradian@gmail.com>"); +MODULE_DESCRIPTION("QTI SDM660 LPI GPIO pin control driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/pinctrl/qcom/pinctrl-sdm660.c b/drivers/pinctrl/qcom/pinctrl-sdm660.c index 1a78288f1bc8..687d986de75c 100644 --- a/drivers/pinctrl/qcom/pinctrl-sdm660.c +++ b/drivers/pinctrl/qcom/pinctrl-sdm660.c @@ -1157,7 +1157,7 @@ static const struct pinfunction sdm660_functions[] = { MSM_PIN_FUNCTION(gcc_gp1), MSM_PIN_FUNCTION(gcc_gp2), MSM_PIN_FUNCTION(gcc_gp3), - MSM_PIN_FUNCTION(gpio), + MSM_GPIO_PIN_FUNCTION(gpio), MSM_PIN_FUNCTION(gps_tx_a), MSM_PIN_FUNCTION(gps_tx_b), MSM_PIN_FUNCTION(gps_tx_c), diff --git a/drivers/pinctrl/qcom/pinctrl-sdm670.c b/drivers/pinctrl/qcom/pinctrl-sdm670.c index 0fe1fa94cd6d..486b72edf7b4 100644 --- a/drivers/pinctrl/qcom/pinctrl-sdm670.c +++ b/drivers/pinctrl/qcom/pinctrl-sdm670.c @@ -991,7 +991,7 @@ static const char * const mss_lte_groups[] = { }; static const struct pinfunction sdm670_functions[] = { - MSM_PIN_FUNCTION(gpio), + MSM_GPIO_PIN_FUNCTION(gpio), MSM_PIN_FUNCTION(adsp_ext), MSM_PIN_FUNCTION(agera_pll), MSM_PIN_FUNCTION(atest_char), diff --git a/drivers/pinctrl/qcom/pinctrl-sdm845.c b/drivers/pinctrl/qcom/pinctrl-sdm845.c index 0446e291aa48..4cf8575797a0 100644 --- a/drivers/pinctrl/qcom/pinctrl-sdm845.c +++ b/drivers/pinctrl/qcom/pinctrl-sdm845.c @@ -976,7 +976,7 @@ static const char * const tsif1_sync_groups[] = { }; static const struct pinfunction sdm845_functions[] = { - MSM_PIN_FUNCTION(gpio), + MSM_GPIO_PIN_FUNCTION(gpio), MSM_PIN_FUNCTION(adsp_ext), MSM_PIN_FUNCTION(agera_pll), MSM_PIN_FUNCTION(atest_char), diff --git a/drivers/pinctrl/qcom/pinctrl-sdx55.c b/drivers/pinctrl/qcom/pinctrl-sdx55.c index 2c17bf889146..79a7010b73f1 100644 --- a/drivers/pinctrl/qcom/pinctrl-sdx55.c +++ b/drivers/pinctrl/qcom/pinctrl-sdx55.c @@ -796,7 +796,7 @@ static const struct pinfunction sdx55_functions[] = { MSM_PIN_FUNCTION(gcc_gp2), MSM_PIN_FUNCTION(gcc_gp3), MSM_PIN_FUNCTION(gcc_plltest), - MSM_PIN_FUNCTION(gpio), + MSM_GPIO_PIN_FUNCTION(gpio), MSM_PIN_FUNCTION(i2s_mclk), MSM_PIN_FUNCTION(jitter_bist), MSM_PIN_FUNCTION(ldo_en), diff --git a/drivers/pinctrl/qcom/pinctrl-sdx65.c b/drivers/pinctrl/qcom/pinctrl-sdx65.c index 85b5c0206dbd..cc8a99a6a91e 100644 --- a/drivers/pinctrl/qcom/pinctrl-sdx65.c +++ b/drivers/pinctrl/qcom/pinctrl-sdx65.c @@ -732,7 +732,7 @@ static const struct pinfunction sdx65_functions[] = { MSM_PIN_FUNCTION(gcc_gp2), MSM_PIN_FUNCTION(gcc_gp3), MSM_PIN_FUNCTION(gcc_plltest), - MSM_PIN_FUNCTION(gpio), + MSM_GPIO_PIN_FUNCTION(gpio), MSM_PIN_FUNCTION(i2s_mclk), MSM_PIN_FUNCTION(jitter_bist), MSM_PIN_FUNCTION(ldo_en), diff --git a/drivers/pinctrl/qcom/pinctrl-sdx75.c b/drivers/pinctrl/qcom/pinctrl-sdx75.c index ab13a3a57a83..4078d83d818c 100644 --- a/drivers/pinctrl/qcom/pinctrl-sdx75.c +++ b/drivers/pinctrl/qcom/pinctrl-sdx75.c @@ -852,7 +852,7 @@ static const struct pinfunction sdx75_functions[] = { MSM_PIN_FUNCTION(gcc_gp2_clk), MSM_PIN_FUNCTION(gcc_gp3_clk), MSM_PIN_FUNCTION(gcc_plltest), - MSM_PIN_FUNCTION(gpio), + MSM_GPIO_PIN_FUNCTION(gpio), MSM_PIN_FUNCTION(i2s_mclk), MSM_PIN_FUNCTION(jitter_bist), MSM_PIN_FUNCTION(ldo_en), diff --git a/drivers/pinctrl/qcom/pinctrl-sm4450.c b/drivers/pinctrl/qcom/pinctrl-sm4450.c index 1ecdf1ab4f27..d51e271e3361 100644 --- a/drivers/pinctrl/qcom/pinctrl-sm4450.c +++ b/drivers/pinctrl/qcom/pinctrl-sm4450.c @@ -722,7 +722,7 @@ static const char * const wlan1_adc_dtest1_groups[] = { }; static const struct pinfunction sm4450_functions[] = { - MSM_PIN_FUNCTION(gpio), + MSM_GPIO_PIN_FUNCTION(gpio), MSM_PIN_FUNCTION(atest_char), MSM_PIN_FUNCTION(atest_usb0), MSM_PIN_FUNCTION(audio_ref_clk), diff --git a/drivers/pinctrl/qcom/pinctrl-sm6115.c b/drivers/pinctrl/qcom/pinctrl-sm6115.c index c273efa43996..06700685ea2a 100644 --- a/drivers/pinctrl/qcom/pinctrl-sm6115.c +++ b/drivers/pinctrl/qcom/pinctrl-sm6115.c @@ -687,7 +687,7 @@ static const struct pinfunction sm6115_functions[] = { MSM_PIN_FUNCTION(gcc_gp1), MSM_PIN_FUNCTION(gcc_gp2), MSM_PIN_FUNCTION(gcc_gp3), - MSM_PIN_FUNCTION(gpio), + MSM_GPIO_PIN_FUNCTION(gpio), MSM_PIN_FUNCTION(gp_pdm0), MSM_PIN_FUNCTION(gp_pdm1), MSM_PIN_FUNCTION(gp_pdm2), diff --git a/drivers/pinctrl/qcom/pinctrl-sm6125.c b/drivers/pinctrl/qcom/pinctrl-sm6125.c index 5092f20e0c1b..5d3d1e402345 100644 --- a/drivers/pinctrl/qcom/pinctrl-sm6125.c +++ b/drivers/pinctrl/qcom/pinctrl-sm6125.c @@ -943,7 +943,7 @@ static const char * const dmic1_data_groups[] = { static const struct pinfunction sm6125_functions[] = { MSM_PIN_FUNCTION(qup00), - MSM_PIN_FUNCTION(gpio), + MSM_GPIO_PIN_FUNCTION(gpio), MSM_PIN_FUNCTION(qdss), MSM_PIN_FUNCTION(qup01), MSM_PIN_FUNCTION(qup02), diff --git a/drivers/pinctrl/qcom/pinctrl-sm6350.c b/drivers/pinctrl/qcom/pinctrl-sm6350.c index ba4686c86c54..220fb582cac9 100644 --- a/drivers/pinctrl/qcom/pinctrl-sm6350.c +++ b/drivers/pinctrl/qcom/pinctrl-sm6350.c @@ -1048,7 +1048,7 @@ static const struct pinfunction sm6350_functions[] = { MSM_PIN_FUNCTION(gp_pdm0), MSM_PIN_FUNCTION(gp_pdm1), MSM_PIN_FUNCTION(gp_pdm2), - MSM_PIN_FUNCTION(gpio), + MSM_GPIO_PIN_FUNCTION(gpio), MSM_PIN_FUNCTION(gps_tx), MSM_PIN_FUNCTION(ibi_i3c), MSM_PIN_FUNCTION(jitter_bist), diff --git a/drivers/pinctrl/qcom/pinctrl-sm6375.c b/drivers/pinctrl/qcom/pinctrl-sm6375.c index 49031571e65e..08b8ef6efaf0 100644 --- a/drivers/pinctrl/qcom/pinctrl-sm6375.c +++ b/drivers/pinctrl/qcom/pinctrl-sm6375.c @@ -1172,7 +1172,7 @@ static const struct pinfunction sm6375_functions[] = { MSM_PIN_FUNCTION(gp_pdm0), MSM_PIN_FUNCTION(gp_pdm1), MSM_PIN_FUNCTION(gp_pdm2), - MSM_PIN_FUNCTION(gpio), + MSM_GPIO_PIN_FUNCTION(gpio), MSM_PIN_FUNCTION(gps_tx), MSM_PIN_FUNCTION(ibi_i3c), MSM_PIN_FUNCTION(jitter_bist), diff --git a/drivers/pinctrl/qcom/pinctrl-sm7150.c b/drivers/pinctrl/qcom/pinctrl-sm7150.c index 6e89966cd70e..78dd8153a4d4 100644 --- a/drivers/pinctrl/qcom/pinctrl-sm7150.c +++ b/drivers/pinctrl/qcom/pinctrl-sm7150.c @@ -960,7 +960,7 @@ static const char * const wsa_data_groups[] = { }; static const struct pinfunction sm7150_functions[] = { - MSM_PIN_FUNCTION(gpio), + MSM_GPIO_PIN_FUNCTION(gpio), MSM_PIN_FUNCTION(adsp_ext), MSM_PIN_FUNCTION(agera_pll), MSM_PIN_FUNCTION(aoss_cti), diff --git a/drivers/pinctrl/qcom/pinctrl-sm8150.c b/drivers/pinctrl/qcom/pinctrl-sm8150.c index 794ed99463f7..ad861cd66958 100644 --- a/drivers/pinctrl/qcom/pinctrl-sm8150.c +++ b/drivers/pinctrl/qcom/pinctrl-sm8150.c @@ -1217,7 +1217,7 @@ static const struct pinfunction sm8150_functions[] = { MSM_PIN_FUNCTION(gcc_gp1), MSM_PIN_FUNCTION(gcc_gp2), MSM_PIN_FUNCTION(gcc_gp3), - MSM_PIN_FUNCTION(gpio), + MSM_GPIO_PIN_FUNCTION(gpio), MSM_PIN_FUNCTION(hs1_mi2s), MSM_PIN_FUNCTION(hs2_mi2s), MSM_PIN_FUNCTION(hs3_mi2s), diff --git a/drivers/pinctrl/qcom/pinctrl-sm8250.c b/drivers/pinctrl/qcom/pinctrl-sm8250.c index fb6f005d64f5..f05361f3100d 100644 --- a/drivers/pinctrl/qcom/pinctrl-sm8250.c +++ b/drivers/pinctrl/qcom/pinctrl-sm8250.c @@ -49,6 +49,8 @@ enum { .mux_bit = 2, \ .pull_bit = 0, \ .drv_bit = 6, \ + .egpio_enable = 12, \ + .egpio_present = 11, \ .oe_bit = 9, \ .in_bit = 0, \ .out_bit = 1, \ @@ -511,6 +513,7 @@ enum sm8250_functions { msm_mux_ddr_pxi2, msm_mux_ddr_pxi3, msm_mux_dp_hot, + msm_mux_egpio, msm_mux_dp_lcd, msm_mux_gcc_gp1, msm_mux_gcc_gp2, @@ -830,6 +833,14 @@ static const char * const gpio_groups[] = { "gpio171", "gpio172", "gpio173", "gpio174", "gpio175", "gpio176", "gpio177", "gpio178", "gpio179", }; +static const char * const egpio_groups[] = { + "gpio146", "gpio147", "gpio148", "gpio149", "gpio150", "gpio151", + "gpio152", "gpio153", "gpio154", "gpio155", "gpio156", "gpio157", + "gpio158", "gpio159", "gpio160", "gpio161", "gpio162", "gpio163", + "gpio164", "gpio165", "gpio166", "gpio167", "gpio168", "gpio169", + "gpio170", "gpio171", "gpio172", "gpio173", "gpio174", "gpio175", + "gpio176", "gpio177", "gpio178", "gpio179", +}; static const char * const qdss_cti_groups[] = { "gpio0", "gpio2", "gpio2", "gpio44", "gpio45", "gpio46", "gpio92", "gpio93", @@ -1018,10 +1029,11 @@ static const struct pinfunction sm8250_functions[] = { MSM_PIN_FUNCTION(ddr_pxi3), MSM_PIN_FUNCTION(dp_hot), MSM_PIN_FUNCTION(dp_lcd), + MSM_PIN_FUNCTION(egpio), MSM_PIN_FUNCTION(gcc_gp1), MSM_PIN_FUNCTION(gcc_gp2), MSM_PIN_FUNCTION(gcc_gp3), - MSM_PIN_FUNCTION(gpio), + MSM_GPIO_PIN_FUNCTION(gpio), MSM_PIN_FUNCTION(ibi_i3c), MSM_PIN_FUNCTION(jitter_bist), MSM_PIN_FUNCTION(lpass_slimbus), @@ -1265,40 +1277,40 @@ static const struct msm_pingroup sm8250_groups[] = { [143] = PINGROUP(143, WEST, lpass_slimbus, mi2s1_data0, ddr_bist, _, _, _, _, _, _), [144] = PINGROUP(144, WEST, lpass_slimbus, mi2s1_data1, ddr_bist, _, _, _, _, _, _), [145] = PINGROUP(145, WEST, lpass_slimbus, mi2s1_ws, _, _, _, _, _, _, _), - [146] = PINGROUP(146, WEST, _, _, _, _, _, _, _, _, _), - [147] = PINGROUP(147, WEST, _, _, _, _, _, _, _, _, _), - [148] = PINGROUP(148, WEST, _, _, _, _, _, _, _, _, _), - [149] = PINGROUP(149, WEST, _, _, _, _, _, _, _, _, _), - [150] = PINGROUP(150, WEST, _, _, _, _, _, _, _, _, _), - [151] = PINGROUP(151, WEST, _, _, _, _, _, _, _, _, _), - [152] = PINGROUP(152, WEST, _, _, _, _, _, _, _, _, _), - [153] = PINGROUP(153, WEST, _, _, _, _, _, _, _, _, _), - [154] = PINGROUP(154, WEST, _, _, _, _, _, _, _, _, _), - [155] = PINGROUP(155, WEST, _, _, _, _, _, _, _, _, _), - [156] = PINGROUP(156, WEST, _, _, _, _, _, _, _, _, _), - [157] = PINGROUP(157, WEST, _, _, _, _, _, _, _, _, _), - [158] = PINGROUP(158, WEST, _, _, _, _, _, _, _, _, _), - [159] = PINGROUP(159, WEST, cri_trng0, _, _, _, _, _, _, _, _), - [160] = PINGROUP(160, WEST, cri_trng1, qdss_gpio, _, _, _, _, _, _, _), - [161] = PINGROUP(161, WEST, cri_trng, qdss_gpio, _, _, _, _, _, _, _), - [162] = PINGROUP(162, WEST, sp_cmu, qdss_gpio, _, _, _, _, _, _, _), - [163] = PINGROUP(163, WEST, prng_rosc, qdss_gpio, _, _, _, _, _, _, _), - [164] = PINGROUP(164, WEST, qdss_gpio, _, _, _, _, _, _, _, _), - [165] = PINGROUP(165, WEST, qdss_gpio, _, _, _, _, _, _, _, _), - [166] = PINGROUP(166, WEST, qdss_gpio, _, _, _, _, _, _, _, _), - [167] = PINGROUP(167, WEST, qdss_gpio, _, _, _, _, _, _, _, _), - [168] = PINGROUP(168, WEST, qdss_gpio, _, _, _, _, _, _, _, _), - [169] = PINGROUP(169, WEST, qdss_gpio, _, _, _, _, _, _, _, _), - [170] = PINGROUP(170, WEST, qdss_gpio, _, _, _, _, _, _, _, _), - [171] = PINGROUP(171, WEST, qdss_gpio, _, _, _, _, _, _, _, _), - [172] = PINGROUP(172, WEST, qdss_gpio, _, _, _, _, _, _, _, _), - [173] = PINGROUP(173, WEST, qdss_gpio, _, _, _, _, _, _, _, _), - [174] = PINGROUP(174, WEST, qdss_gpio, _, _, _, _, _, _, _, _), - [175] = PINGROUP(175, WEST, qdss_gpio, _, _, _, _, _, _, _, _), - [176] = PINGROUP(176, WEST, qdss_gpio, _, _, _, _, _, _, _, _), - [177] = PINGROUP(177, WEST, qdss_gpio, _, _, _, _, _, _, _, _), - [178] = PINGROUP(178, WEST, _, _, _, _, _, _, _, _, _), - [179] = PINGROUP(179, WEST, _, _, _, _, _, _, _, _, _), + [146] = PINGROUP(146, WEST, _, _, _, _, _, _, _, _, egpio), + [147] = PINGROUP(147, WEST, _, _, _, _, _, _, _, _, egpio), + [148] = PINGROUP(148, WEST, _, _, _, _, _, _, _, _, egpio), + [149] = PINGROUP(149, WEST, _, _, _, _, _, _, _, _, egpio), + [150] = PINGROUP(150, WEST, _, _, _, _, _, _, _, _, egpio), + [151] = PINGROUP(151, WEST, _, _, _, _, _, _, _, _, egpio), + [152] = PINGROUP(152, WEST, _, _, _, _, _, _, _, _, egpio), + [153] = PINGROUP(153, WEST, _, _, _, _, _, _, _, _, egpio), + [154] = PINGROUP(154, WEST, _, _, _, _, _, _, _, _, egpio), + [155] = PINGROUP(155, WEST, _, _, _, _, _, _, _, _, egpio), + [156] = PINGROUP(156, WEST, _, _, _, _, _, _, _, _, egpio), + [157] = PINGROUP(157, WEST, _, _, _, _, _, _, _, _, egpio), + [158] = PINGROUP(158, WEST, _, _, _, _, _, _, _, _, egpio), + [159] = PINGROUP(159, WEST, cri_trng0, _, _, _, _, _, _, _, egpio), + [160] = PINGROUP(160, WEST, cri_trng1, qdss_gpio, _, _, _, _, _, _, egpio), + [161] = PINGROUP(161, WEST, cri_trng, qdss_gpio, _, _, _, _, _, _, egpio), + [162] = PINGROUP(162, WEST, sp_cmu, qdss_gpio, _, _, _, _, _, _, egpio), + [163] = PINGROUP(163, WEST, prng_rosc, qdss_gpio, _, _, _, _, _, _, egpio), + [164] = PINGROUP(164, WEST, qdss_gpio, _, _, _, _, _, _, _, egpio), + [165] = PINGROUP(165, WEST, qdss_gpio, _, _, _, _, _, _, _, egpio), + [166] = PINGROUP(166, WEST, qdss_gpio, _, _, _, _, _, _, _, egpio), + [167] = PINGROUP(167, WEST, qdss_gpio, _, _, _, _, _, _, _, egpio), + [168] = PINGROUP(168, WEST, qdss_gpio, _, _, _, _, _, _, _, egpio), + [169] = PINGROUP(169, WEST, qdss_gpio, _, _, _, _, _, _, _, egpio), + [170] = PINGROUP(170, WEST, qdss_gpio, _, _, _, _, _, _, _, egpio), + [171] = PINGROUP(171, WEST, qdss_gpio, _, _, _, _, _, _, _, egpio), + [172] = PINGROUP(172, WEST, qdss_gpio, _, _, _, _, _, _, _, egpio), + [173] = PINGROUP(173, WEST, qdss_gpio, _, _, _, _, _, _, _, egpio), + [174] = PINGROUP(174, WEST, qdss_gpio, _, _, _, _, _, _, _, egpio), + [175] = PINGROUP(175, WEST, qdss_gpio, _, _, _, _, _, _, _, egpio), + [176] = PINGROUP(176, WEST, qdss_gpio, _, _, _, _, _, _, _, egpio), + [177] = PINGROUP(177, WEST, qdss_gpio, _, _, _, _, _, _, _, egpio), + [178] = PINGROUP(178, WEST, _, _, _, _, _, _, _, _, egpio), + [179] = PINGROUP(179, WEST, _, _, _, _, _, _, _, _, egpio), [180] = UFS_RESET(ufs_reset, 0xb8000), [181] = SDC_PINGROUP(sdc2_clk, 0xb7000, 14, 6), [182] = SDC_PINGROUP(sdc2_cmd, 0xb7000, 11, 3), @@ -1333,6 +1345,7 @@ static const struct msm_pinctrl_soc_data sm8250_pinctrl = { .ntiles = ARRAY_SIZE(sm8250_tiles), .wakeirq_map = sm8250_pdc_map, .nwakeirq_map = ARRAY_SIZE(sm8250_pdc_map), + .egpio_func = 9, }; static int sm8250_pinctrl_probe(struct platform_device *pdev) diff --git a/drivers/pinctrl/qcom/pinctrl-sm8350.c b/drivers/pinctrl/qcom/pinctrl-sm8350.c index c8a3f39ce6f1..99949b552021 100644 --- a/drivers/pinctrl/qcom/pinctrl-sm8350.c +++ b/drivers/pinctrl/qcom/pinctrl-sm8350.c @@ -1267,7 +1267,7 @@ static const struct pinfunction sm8350_functions[] = { MSM_PIN_FUNCTION(gcc_gp1), MSM_PIN_FUNCTION(gcc_gp2), MSM_PIN_FUNCTION(gcc_gp3), - MSM_PIN_FUNCTION(gpio), + MSM_GPIO_PIN_FUNCTION(gpio), MSM_PIN_FUNCTION(ibi_i3c), MSM_PIN_FUNCTION(jitter_bist), MSM_PIN_FUNCTION(lpass_slimbus), diff --git a/drivers/pinctrl/qcom/pinctrl-sm8450.c b/drivers/pinctrl/qcom/pinctrl-sm8450.c index f2e52d5a0f93..9889fc5dc2cd 100644 --- a/drivers/pinctrl/qcom/pinctrl-sm8450.c +++ b/drivers/pinctrl/qcom/pinctrl-sm8450.c @@ -1269,7 +1269,7 @@ static const char * const vsense_trigger_groups[] = { }; static const struct pinfunction sm8450_functions[] = { - MSM_PIN_FUNCTION(gpio), + MSM_GPIO_PIN_FUNCTION(gpio), MSM_PIN_FUNCTION(aon_cam), MSM_PIN_FUNCTION(atest_char), MSM_PIN_FUNCTION(atest_usb), @@ -1291,7 +1291,7 @@ static const struct pinfunction sm8450_functions[] = { MSM_PIN_FUNCTION(ddr_pxi2), MSM_PIN_FUNCTION(ddr_pxi3), MSM_PIN_FUNCTION(dp_hot), - MSM_PIN_FUNCTION(egpio), + MSM_GPIO_PIN_FUNCTION(egpio), MSM_PIN_FUNCTION(gcc_gp1), MSM_PIN_FUNCTION(gcc_gp2), MSM_PIN_FUNCTION(gcc_gp3), diff --git a/drivers/pinctrl/qcom/pinctrl-sm8550.c b/drivers/pinctrl/qcom/pinctrl-sm8550.c index 1b4496cb39eb..10a62031fdfd 100644 --- a/drivers/pinctrl/qcom/pinctrl-sm8550.c +++ b/drivers/pinctrl/qcom/pinctrl-sm8550.c @@ -1340,7 +1340,7 @@ static const char *const vsense_trigger_mirnat_groups[] = { }; static const struct pinfunction sm8550_functions[] = { - MSM_PIN_FUNCTION(gpio), + MSM_GPIO_PIN_FUNCTION(gpio), MSM_PIN_FUNCTION(aon_cci), MSM_PIN_FUNCTION(aoss_cti), MSM_PIN_FUNCTION(atest_char), diff --git a/drivers/pinctrl/qcom/pinctrl-sm8650.c b/drivers/pinctrl/qcom/pinctrl-sm8650.c index 449a0077f4b1..e2ae03800206 100644 --- a/drivers/pinctrl/qcom/pinctrl-sm8650.c +++ b/drivers/pinctrl/qcom/pinctrl-sm8650.c @@ -1328,7 +1328,7 @@ static const char *const vsense_trigger_mirnat_groups[] = { }; static const struct pinfunction sm8650_functions[] = { - MSM_PIN_FUNCTION(gpio), + MSM_GPIO_PIN_FUNCTION(gpio), MSM_PIN_FUNCTION(aoss_cti), MSM_PIN_FUNCTION(atest_char), MSM_PIN_FUNCTION(atest_usb), @@ -1359,7 +1359,7 @@ static const struct pinfunction sm8650_functions[] = { MSM_PIN_FUNCTION(ddr_pxi3), MSM_PIN_FUNCTION(do_not), MSM_PIN_FUNCTION(dp_hot), - MSM_PIN_FUNCTION(egpio), + MSM_GPIO_PIN_FUNCTION(egpio), MSM_PIN_FUNCTION(gcc_gp1), MSM_PIN_FUNCTION(gcc_gp2), MSM_PIN_FUNCTION(gcc_gp3), diff --git a/drivers/pinctrl/qcom/pinctrl-sm8750.c b/drivers/pinctrl/qcom/pinctrl-sm8750.c index 8516693d1db5..6f92f176edd4 100644 --- a/drivers/pinctrl/qcom/pinctrl-sm8750.c +++ b/drivers/pinctrl/qcom/pinctrl-sm8750.c @@ -1290,7 +1290,7 @@ static const char *const wcn_sw_ctrl_groups[] = { }; static const struct pinfunction sm8750_functions[] = { - MSM_PIN_FUNCTION(gpio), + MSM_GPIO_PIN_FUNCTION(gpio), MSM_PIN_FUNCTION(aoss_cti), MSM_PIN_FUNCTION(atest_char), MSM_PIN_FUNCTION(atest_usb), @@ -1319,7 +1319,7 @@ static const struct pinfunction sm8750_functions[] = { MSM_PIN_FUNCTION(ddr_pxi2), MSM_PIN_FUNCTION(ddr_pxi3), MSM_PIN_FUNCTION(dp_hot), - MSM_PIN_FUNCTION(egpio), + MSM_GPIO_PIN_FUNCTION(egpio), MSM_PIN_FUNCTION(gcc_gp1), MSM_PIN_FUNCTION(gcc_gp2), MSM_PIN_FUNCTION(gcc_gp3), diff --git a/drivers/pinctrl/qcom/pinctrl-spmi-gpio.c b/drivers/pinctrl/qcom/pinctrl-spmi-gpio.c index bc082bfb52ef..485b68cc93f8 100644 --- a/drivers/pinctrl/qcom/pinctrl-spmi-gpio.c +++ b/drivers/pinctrl/qcom/pinctrl-spmi-gpio.c @@ -438,7 +438,7 @@ static int pmic_gpio_config_get(struct pinctrl_dev *pctldev, case PIN_CONFIG_OUTPUT_ENABLE: arg = pad->output_enabled; break; - case PIN_CONFIG_OUTPUT: + case PIN_CONFIG_LEVEL: arg = pad->out_value; break; case PMIC_GPIO_CONF_PULL_UP: @@ -530,7 +530,7 @@ static int pmic_gpio_config_set(struct pinctrl_dev *pctldev, unsigned int pin, case PIN_CONFIG_OUTPUT_ENABLE: pad->output_enabled = arg ? true : false; break; - case PIN_CONFIG_OUTPUT: + case PIN_CONFIG_LEVEL: pad->output_enabled = true; pad->out_value = arg; break; @@ -737,7 +737,7 @@ static int pmic_gpio_direction_output(struct gpio_chip *chip, struct pmic_gpio_state *state = gpiochip_get_data(chip); unsigned long config; - config = pinconf_to_config_packed(PIN_CONFIG_OUTPUT, val); + config = pinconf_to_config_packed(PIN_CONFIG_LEVEL, val); return pmic_gpio_config_set(state->ctrl, pin, &config, 1); } @@ -769,7 +769,7 @@ static int pmic_gpio_set(struct gpio_chip *chip, unsigned int pin, int value) struct pmic_gpio_state *state = gpiochip_get_data(chip); unsigned long config; - config = pinconf_to_config_packed(PIN_CONFIG_OUTPUT, value); + config = pinconf_to_config_packed(PIN_CONFIG_LEVEL, value); return pmic_gpio_config_set(state->ctrl, pin, &config, 1); } @@ -802,7 +802,7 @@ static const struct gpio_chip pmic_gpio_gpio_template = { .direction_input = pmic_gpio_direction_input, .direction_output = pmic_gpio_direction_output, .get = pmic_gpio_get, - .set_rv = pmic_gpio_set, + .set = pmic_gpio_set, .request = gpiochip_generic_request, .free = gpiochip_generic_free, .of_xlate = pmic_gpio_of_xlate, @@ -1206,6 +1206,7 @@ static const struct of_device_id pmic_gpio_of_match[] = { { .compatible = "qcom,pm6450-gpio", .data = (void *) 9 }, { .compatible = "qcom,pm7250b-gpio", .data = (void *) 12 }, { .compatible = "qcom,pm7325-gpio", .data = (void *) 10 }, + { .compatible = "qcom,pm7550-gpio", .data = (void *) 12 }, { .compatible = "qcom,pm7550ba-gpio", .data = (void *) 8}, { .compatible = "qcom,pm8005-gpio", .data = (void *) 4 }, { .compatible = "qcom,pm8019-gpio", .data = (void *) 6 }, @@ -1244,6 +1245,7 @@ static const struct of_device_id pmic_gpio_of_match[] = { { .compatible = "qcom,pmi8994-gpio", .data = (void *) 10 }, { .compatible = "qcom,pmi8998-gpio", .data = (void *) 14 }, { .compatible = "qcom,pmih0108-gpio", .data = (void *) 18 }, + { .compatible = "qcom,pmiv0104-gpio", .data = (void *) 10 }, { .compatible = "qcom,pmk8350-gpio", .data = (void *) 4 }, { .compatible = "qcom,pmk8550-gpio", .data = (void *) 6 }, { .compatible = "qcom,pmm8155au-gpio", .data = (void *) 10 }, diff --git a/drivers/pinctrl/qcom/pinctrl-spmi-mpp.c b/drivers/pinctrl/qcom/pinctrl-spmi-mpp.c index ba9084978f90..64f8024a865c 100644 --- a/drivers/pinctrl/qcom/pinctrl-spmi-mpp.c +++ b/drivers/pinctrl/qcom/pinctrl-spmi-mpp.c @@ -370,7 +370,7 @@ static int pmic_mpp_config_get(struct pinctrl_dev *pctldev, return -EINVAL; arg = 1; break; - case PIN_CONFIG_OUTPUT: + case PIN_CONFIG_LEVEL: arg = pad->out_value; break; case PMIC_MPP_CONF_DTEST_SELECTOR: @@ -447,7 +447,7 @@ static int pmic_mpp_config_set(struct pinctrl_dev *pctldev, unsigned int pin, case PIN_CONFIG_INPUT_ENABLE: pad->input_enabled = arg ? true : false; break; - case PIN_CONFIG_OUTPUT: + case PIN_CONFIG_LEVEL: pad->output_enabled = true; pad->out_value = arg; break; @@ -576,7 +576,7 @@ static int pmic_mpp_direction_output(struct gpio_chip *chip, struct pmic_mpp_state *state = gpiochip_get_data(chip); unsigned long config; - config = pinconf_to_config_packed(PIN_CONFIG_OUTPUT, val); + config = pinconf_to_config_packed(PIN_CONFIG_LEVEL, val); return pmic_mpp_config_set(state->ctrl, pin, &config, 1); } @@ -605,7 +605,7 @@ static int pmic_mpp_set(struct gpio_chip *chip, unsigned int pin, int value) struct pmic_mpp_state *state = gpiochip_get_data(chip); unsigned long config; - config = pinconf_to_config_packed(PIN_CONFIG_OUTPUT, value); + config = pinconf_to_config_packed(PIN_CONFIG_LEVEL, value); return pmic_mpp_config_set(state->ctrl, pin, &config, 1); } @@ -638,7 +638,7 @@ static const struct gpio_chip pmic_mpp_gpio_template = { .direction_input = pmic_mpp_direction_input, .direction_output = pmic_mpp_direction_output, .get = pmic_mpp_get, - .set_rv = pmic_mpp_set, + .set = pmic_mpp_set, .request = gpiochip_generic_request, .free = gpiochip_generic_free, .of_xlate = pmic_mpp_of_xlate, diff --git a/drivers/pinctrl/qcom/pinctrl-ssbi-gpio.c b/drivers/pinctrl/qcom/pinctrl-ssbi-gpio.c index 3a8014ebf064..5c966d51eda7 100644 --- a/drivers/pinctrl/qcom/pinctrl-ssbi-gpio.c +++ b/drivers/pinctrl/qcom/pinctrl-ssbi-gpio.c @@ -282,7 +282,7 @@ static int pm8xxx_pin_config_get(struct pinctrl_dev *pctldev, return -EINVAL; arg = 1; break; - case PIN_CONFIG_OUTPUT: + case PIN_CONFIG_LEVEL: if (pin->mode & PM8XXX_GPIO_MODE_OUTPUT) arg = pin->output_value; else @@ -364,7 +364,7 @@ static int pm8xxx_pin_config_set(struct pinctrl_dev *pctldev, pin->mode = PM8XXX_GPIO_MODE_INPUT; banks |= BIT(0) | BIT(1); break; - case PIN_CONFIG_OUTPUT: + case PIN_CONFIG_LEVEL: pin->mode = PM8XXX_GPIO_MODE_OUTPUT; pin->output_value = !!arg; banks |= BIT(0) | BIT(1); @@ -597,7 +597,7 @@ static const struct gpio_chip pm8xxx_gpio_template = { .direction_input = pm8xxx_gpio_direction_input, .direction_output = pm8xxx_gpio_direction_output, .get = pm8xxx_gpio_get, - .set_rv = pm8xxx_gpio_set, + .set = pm8xxx_gpio_set, .of_xlate = pm8xxx_gpio_of_xlate, .dbg_show = pm8xxx_gpio_dbg_show, .owner = THIS_MODULE, diff --git a/drivers/pinctrl/qcom/pinctrl-ssbi-mpp.c b/drivers/pinctrl/qcom/pinctrl-ssbi-mpp.c index 087c37d304fc..7970fa6e1557 100644 --- a/drivers/pinctrl/qcom/pinctrl-ssbi-mpp.c +++ b/drivers/pinctrl/qcom/pinctrl-ssbi-mpp.c @@ -337,7 +337,7 @@ static int pm8xxx_pin_config_get(struct pinctrl_dev *pctldev, case PIN_CONFIG_INPUT_ENABLE: arg = pin->input; break; - case PIN_CONFIG_OUTPUT: + case PIN_CONFIG_LEVEL: arg = pin->output_value; break; case PIN_CONFIG_POWER_SOURCE: @@ -392,7 +392,7 @@ static int pm8xxx_pin_config_set(struct pinctrl_dev *pctldev, case PIN_CONFIG_INPUT_ENABLE: pin->input = true; break; - case PIN_CONFIG_OUTPUT: + case PIN_CONFIG_LEVEL: pin->output = true; pin->output_value = !!arg; break; @@ -634,7 +634,7 @@ static const struct gpio_chip pm8xxx_mpp_template = { .direction_input = pm8xxx_mpp_direction_input, .direction_output = pm8xxx_mpp_direction_output, .get = pm8xxx_mpp_get, - .set_rv = pm8xxx_mpp_set, + .set = pm8xxx_mpp_set, .of_xlate = pm8xxx_mpp_of_xlate, .dbg_show = pm8xxx_mpp_dbg_show, .owner = THIS_MODULE, diff --git a/drivers/pinctrl/qcom/pinctrl-x1e80100.c b/drivers/pinctrl/qcom/pinctrl-x1e80100.c index d4b215f34c39..bb36f40b19fa 100644 --- a/drivers/pinctrl/qcom/pinctrl-x1e80100.c +++ b/drivers/pinctrl/qcom/pinctrl-x1e80100.c @@ -1407,7 +1407,7 @@ static const char * const vsense_trigger_groups[] = { }; static const struct pinfunction x1e80100_functions[] = { - MSM_PIN_FUNCTION(gpio), + MSM_GPIO_PIN_FUNCTION(gpio), MSM_PIN_FUNCTION(RESOUT_GPIO), MSM_PIN_FUNCTION(aon_cci), MSM_PIN_FUNCTION(aoss_cti), diff --git a/drivers/pinctrl/qcom/tlmm-test.c b/drivers/pinctrl/qcom/tlmm-test.c index 7b99e89e0f67..7d7fff538755 100644 --- a/drivers/pinctrl/qcom/tlmm-test.c +++ b/drivers/pinctrl/qcom/tlmm-test.c @@ -16,6 +16,7 @@ #include <linux/of_irq.h> #include <linux/pinctrl/consumer.h> #include <linux/platform_device.h> +#include <linux/slab.h> /* * This TLMM test module serves the purpose of validating that the TLMM driver @@ -38,7 +39,10 @@ #define TLMM_REG_SIZE 0x1000 static int tlmm_test_gpio = -1; +static char *tlmm_reg_name = "default_region"; + module_param_named(gpio, tlmm_test_gpio, int, 0600); +module_param_named(name, tlmm_reg_name, charp, 0600); static struct { void __iomem *base; @@ -570,6 +574,47 @@ static const struct of_device_id tlmm_of_match[] = { {} }; +static int tlmm_reg_base(struct device_node *tlmm, struct resource *res) +{ + const char **reg_names; + int count; + int ret; + int i; + + count = of_property_count_strings(tlmm, "reg-names"); + if (count <= 0) { + pr_err("failed to find tlmm reg name\n"); + return count; + } + + reg_names = kcalloc(count, sizeof(char *), GFP_KERNEL); + if (!reg_names) + return -ENOMEM; + + ret = of_property_read_string_array(tlmm, "reg-names", reg_names, count); + if (ret != count) { + kfree(reg_names); + return -EINVAL; + } + + if (!strcmp(tlmm_reg_name, "default_region")) { + ret = of_address_to_resource(tlmm, 0, res); + } else { + for (i = 0; i < count; i++) { + if (!strcmp(reg_names[i], tlmm_reg_name)) { + ret = of_address_to_resource(tlmm, i, res); + break; + } + } + if (i == count) + ret = -EINVAL; + } + + kfree(reg_names); + + return ret; +} + static int tlmm_test_init_suite(struct kunit_suite *suite) { struct of_phandle_args args = {}; @@ -588,7 +633,7 @@ static int tlmm_test_init_suite(struct kunit_suite *suite) return -EINVAL; } - ret = of_address_to_resource(tlmm, 0, &res); + ret = tlmm_reg_base(tlmm, &res); if (ret < 0) return ret; |