diff options
Diffstat (limited to 'drivers/media/platform/cadence/cdns-csi2rx.c')
| -rw-r--r-- | drivers/media/platform/cadence/cdns-csi2rx.c | 206 |
1 files changed, 188 insertions, 18 deletions
diff --git a/drivers/media/platform/cadence/cdns-csi2rx.c b/drivers/media/platform/cadence/cdns-csi2rx.c index cebcae196eec..8c19f125da3e 100644 --- a/drivers/media/platform/cadence/cdns-csi2rx.c +++ b/drivers/media/platform/cadence/cdns-csi2rx.c @@ -5,8 +5,10 @@ * Copyright (C) 2017 Cadence Design Systems Inc. */ +#include <linux/bitfield.h> #include <linux/clk.h> #include <linux/delay.h> +#include <linux/export.h> #include <linux/io.h> #include <linux/iopoll.h> #include <linux/module.h> @@ -17,6 +19,7 @@ #include <linux/reset.h> #include <linux/slab.h> +#include <media/cadence/cdns-csi2rx.h> #include <media/v4l2-ctrls.h> #include <media/v4l2-device.h> #include <media/v4l2-fwnode.h> @@ -52,11 +55,32 @@ #define CSI2RX_STREAM_DATA_CFG_VC_SELECT(n) BIT((n) + 16) #define CSI2RX_STREAM_CFG_REG(n) (CSI2RX_STREAM_BASE(n) + 0x00c) -#define CSI2RX_STREAM_CFG_FIFO_MODE_LARGE_BUF (1 << 8) +#define CSI2RX_STREAM_CFG_FIFO_MODE_LARGE_BUF BIT(8) +#define CSI2RX_STREAM_CFG_NUM_PIXELS_MASK GENMASK(5, 4) +#define CSI2RX_STREAM_CFG_NUM_PIXELS(n) ((n) >> 1U) #define CSI2RX_LANES_MAX 4 #define CSI2RX_STREAMS_MAX 4 +#define CSI2RX_ERROR_IRQS_REG 0x28 +#define CSI2RX_ERROR_IRQS_MASK_REG 0x2C + +#define CSI2RX_STREAM3_FIFO_OVERFLOW_IRQ BIT(19) +#define CSI2RX_STREAM2_FIFO_OVERFLOW_IRQ BIT(18) +#define CSI2RX_STREAM1_FIFO_OVERFLOW_IRQ BIT(17) +#define CSI2RX_STREAM0_FIFO_OVERFLOW_IRQ BIT(16) +#define CSI2RX_FRONT_TRUNC_HDR_IRQ BIT(12) +#define CSI2RX_PROT_TRUNCATED_PACKET_IRQ BIT(11) +#define CSI2RX_FRONT_LP_NO_PAYLOAD_IRQ BIT(10) +#define CSI2RX_SP_INVALID_RCVD_IRQ BIT(9) +#define CSI2RX_DATA_ID_IRQ BIT(7) +#define CSI2RX_HEADER_CORRECTED_ECC_IRQ BIT(6) +#define CSI2RX_HEADER_ECC_IRQ BIT(5) +#define CSI2RX_PAYLOAD_CRC_IRQ BIT(4) + +#define CSI2RX_ECC_ERRORS GENMASK(7, 4) +#define CSI2RX_PACKET_ERRORS GENMASK(12, 9) + enum csi2rx_pads { CSI2RX_PAD_SINK, CSI2RX_PAD_SOURCE_STREAM0, @@ -68,12 +92,38 @@ enum csi2rx_pads { struct csi2rx_fmt { u32 code; + /* width of a single pixel on CSI-2 bus */ u8 bpp; + /* max pixels per clock supported on output bus */ + u8 max_pixels; +}; + +struct csi2rx_event { + u32 mask; + const char *name; +}; + +static const struct csi2rx_event csi2rx_events[] = { + { CSI2RX_STREAM3_FIFO_OVERFLOW_IRQ, "Overflow of the Stream 3 FIFO detected" }, + { CSI2RX_STREAM2_FIFO_OVERFLOW_IRQ, "Overflow of the Stream 2 FIFO detected" }, + { CSI2RX_STREAM1_FIFO_OVERFLOW_IRQ, "Overflow of the Stream 1 FIFO detected" }, + { CSI2RX_STREAM0_FIFO_OVERFLOW_IRQ, "Overflow of the Stream 0 FIFO detected" }, + { CSI2RX_FRONT_TRUNC_HDR_IRQ, "A truncated header [short or long] has been received" }, + { CSI2RX_PROT_TRUNCATED_PACKET_IRQ, "A truncated long packet has been received" }, + { CSI2RX_FRONT_LP_NO_PAYLOAD_IRQ, "A truncated long packet has been received. No payload" }, + { CSI2RX_SP_INVALID_RCVD_IRQ, "A reserved or invalid short packet has been received" }, + { CSI2RX_DATA_ID_IRQ, "Data ID error in the header packet" }, + { CSI2RX_HEADER_CORRECTED_ECC_IRQ, "ECC error detected and corrected" }, + { CSI2RX_HEADER_ECC_IRQ, "Unrecoverable ECC error" }, + { CSI2RX_PAYLOAD_CRC_IRQ, "CRC error" }, }; +#define CSI2RX_NUM_EVENTS ARRAY_SIZE(csi2rx_events) + struct csi2rx_priv { struct device *dev; unsigned int count; + int error_irq; /* * Used to prevent race conditions between multiple, @@ -90,11 +140,13 @@ struct csi2rx_priv { struct reset_control *pixel_rst[CSI2RX_STREAMS_MAX]; struct phy *dphy; + u8 num_pixels[CSI2RX_STREAMS_MAX]; u8 lanes[CSI2RX_LANES_MAX]; u8 num_lanes; u8 max_lanes; u8 max_streams; bool has_internal_dphy; + u32 events[CSI2RX_NUM_EVENTS]; struct v4l2_subdev subdev; struct v4l2_async_notifier notifier; @@ -106,24 +158,72 @@ struct csi2rx_priv { }; static const struct csi2rx_fmt formats[] = { - { .code = MEDIA_BUS_FMT_YUYV8_1X16, .bpp = 16, }, - { .code = MEDIA_BUS_FMT_UYVY8_1X16, .bpp = 16, }, - { .code = MEDIA_BUS_FMT_YVYU8_1X16, .bpp = 16, }, - { .code = MEDIA_BUS_FMT_VYUY8_1X16, .bpp = 16, }, - { .code = MEDIA_BUS_FMT_SBGGR8_1X8, .bpp = 8, }, - { .code = MEDIA_BUS_FMT_SGBRG8_1X8, .bpp = 8, }, - { .code = MEDIA_BUS_FMT_SGRBG8_1X8, .bpp = 8, }, - { .code = MEDIA_BUS_FMT_SRGGB8_1X8, .bpp = 8, }, - { .code = MEDIA_BUS_FMT_Y8_1X8, .bpp = 8, }, - { .code = MEDIA_BUS_FMT_SBGGR10_1X10, .bpp = 10, }, - { .code = MEDIA_BUS_FMT_SGBRG10_1X10, .bpp = 10, }, - { .code = MEDIA_BUS_FMT_SGRBG10_1X10, .bpp = 10, }, - { .code = MEDIA_BUS_FMT_SRGGB10_1X10, .bpp = 10, }, - { .code = MEDIA_BUS_FMT_RGB565_1X16, .bpp = 16, }, - { .code = MEDIA_BUS_FMT_RGB888_1X24, .bpp = 24, }, - { .code = MEDIA_BUS_FMT_BGR888_1X24, .bpp = 24, }, + { .code = MEDIA_BUS_FMT_YUYV8_1X16, .bpp = 16, .max_pixels = 2, }, + { .code = MEDIA_BUS_FMT_UYVY8_1X16, .bpp = 16, .max_pixels = 2, }, + { .code = MEDIA_BUS_FMT_YVYU8_1X16, .bpp = 16, .max_pixels = 2, }, + { .code = MEDIA_BUS_FMT_VYUY8_1X16, .bpp = 16, .max_pixels = 2, }, + { .code = MEDIA_BUS_FMT_SBGGR8_1X8, .bpp = 8, .max_pixels = 4, }, + { .code = MEDIA_BUS_FMT_SGBRG8_1X8, .bpp = 8, .max_pixels = 4, }, + { .code = MEDIA_BUS_FMT_SGRBG8_1X8, .bpp = 8, .max_pixels = 4, }, + { .code = MEDIA_BUS_FMT_SRGGB8_1X8, .bpp = 8, .max_pixels = 4, }, + { .code = MEDIA_BUS_FMT_Y8_1X8, .bpp = 8, .max_pixels = 4, }, + { .code = MEDIA_BUS_FMT_SBGGR10_1X10, .bpp = 10, .max_pixels = 2, }, + { .code = MEDIA_BUS_FMT_SGBRG10_1X10, .bpp = 10, .max_pixels = 2, }, + { .code = MEDIA_BUS_FMT_SGRBG10_1X10, .bpp = 10, .max_pixels = 2, }, + { .code = MEDIA_BUS_FMT_SRGGB10_1X10, .bpp = 10, .max_pixels = 2, }, + { .code = MEDIA_BUS_FMT_RGB565_1X16, .bpp = 16, .max_pixels = 1, }, + { .code = MEDIA_BUS_FMT_RGB888_1X24, .bpp = 24, .max_pixels = 1, }, + { .code = MEDIA_BUS_FMT_BGR888_1X24, .bpp = 24, .max_pixels = 1, }, }; +static void csi2rx_configure_error_irq_mask(void __iomem *base, + struct csi2rx_priv *csi2rx) +{ + u32 error_irq_mask = 0; + + error_irq_mask |= CSI2RX_ECC_ERRORS; + error_irq_mask |= CSI2RX_PACKET_ERRORS; + + /* + * Iterate through all source pads and check if they are linked + * to an active remote pad. If an active remote pad is found, + * calculate the corresponding bit position and set it in + * mask, enabling the stream overflow error in the mask. + */ + for (int i = CSI2RX_PAD_SOURCE_STREAM0; i < CSI2RX_PAD_MAX; i++) { + struct media_pad *remote_pad; + + remote_pad = media_pad_remote_pad_first(&csi2rx->pads[i]); + if (remote_pad) { + int pad = i - CSI2RX_PAD_SOURCE_STREAM0; + u32 bit_mask = CSI2RX_STREAM0_FIFO_OVERFLOW_IRQ << pad; + + error_irq_mask |= bit_mask; + } + } + + writel(error_irq_mask, base + CSI2RX_ERROR_IRQS_MASK_REG); +} + +static irqreturn_t csi2rx_irq_handler(int irq, void *dev_id) +{ + struct csi2rx_priv *csi2rx = dev_id; + int i; + u32 error_status, error_mask; + + error_status = readl(csi2rx->base + CSI2RX_ERROR_IRQS_REG); + error_mask = readl(csi2rx->base + CSI2RX_ERROR_IRQS_MASK_REG); + + for (i = 0; i < CSI2RX_NUM_EVENTS; i++) + if ((error_status & csi2rx_events[i].mask) && + (error_mask & csi2rx_events[i].mask)) + csi2rx->events[i]++; + + writel(error_status, csi2rx->base + CSI2RX_ERROR_IRQS_REG); + + return IRQ_HANDLED; +} + static const struct csi2rx_fmt *csi2rx_get_fmt_by_code(u32 code) { unsigned int i; @@ -220,6 +320,9 @@ static int csi2rx_start(struct csi2rx_priv *csi2rx) reset_control_deassert(csi2rx->p_rst); csi2rx_reset(csi2rx); + if (csi2rx->error_irq >= 0) + csi2rx_configure_error_irq_mask(csi2rx->base, csi2rx); + reg = csi2rx->num_lanes << 8; for (i = 0; i < csi2rx->num_lanes; i++) { reg |= CSI2RX_STATIC_CFG_DLANE_MAP(i, csi2rx->lanes[i]); @@ -276,7 +379,9 @@ static int csi2rx_start(struct csi2rx_priv *csi2rx) reset_control_deassert(csi2rx->pixel_rst[i]); - writel(CSI2RX_STREAM_CFG_FIFO_MODE_LARGE_BUF, + writel(CSI2RX_STREAM_CFG_FIFO_MODE_LARGE_BUF | + FIELD_PREP(CSI2RX_STREAM_CFG_NUM_PIXELS_MASK, + csi2rx->num_pixels[i]), csi2rx->base + CSI2RX_STREAM_CFG_REG(i)); /* @@ -332,6 +437,8 @@ static void csi2rx_stop(struct csi2rx_priv *csi2rx) reset_control_assert(csi2rx->sys_rst); clk_disable_unprepare(csi2rx->sys_clk); + writel(0, csi2rx->base + CSI2RX_ERROR_IRQS_MASK_REG); + for (i = 0; i < csi2rx->max_streams; i++) { writel(CSI2RX_STREAM_CTRL_STOP, csi2rx->base + CSI2RX_STREAM_CTRL_REG(i)); @@ -363,6 +470,21 @@ static void csi2rx_stop(struct csi2rx_priv *csi2rx) } } +static int csi2rx_log_status(struct v4l2_subdev *sd) +{ + struct csi2rx_priv *csi2rx = v4l2_subdev_to_csi2rx(sd); + unsigned int i; + + for (i = 0; i < CSI2RX_NUM_EVENTS; i++) { + if (csi2rx->events[i]) + dev_info(csi2rx->dev, "%s events: %d\n", + csi2rx_events[i].name, + csi2rx->events[i]); + } + + return 0; +} + static int csi2rx_s_stream(struct v4l2_subdev *subdev, int enable) { struct csi2rx_priv *csi2rx = v4l2_subdev_to_csi2rx(subdev); @@ -458,6 +580,33 @@ static int csi2rx_init_state(struct v4l2_subdev *subdev, return csi2rx_set_fmt(subdev, state, &format); } +int cdns_csi2rx_negotiate_ppc(struct v4l2_subdev *subdev, unsigned int pad, + u8 *ppc) +{ + struct csi2rx_priv *csi2rx = v4l2_subdev_to_csi2rx(subdev); + const struct csi2rx_fmt *csi_fmt; + struct v4l2_subdev_state *state; + struct v4l2_mbus_framefmt *fmt; + + if (!ppc || pad < CSI2RX_PAD_SOURCE_STREAM0 || pad >= CSI2RX_PAD_MAX) + return -EINVAL; + + state = v4l2_subdev_lock_and_get_active_state(subdev); + fmt = v4l2_subdev_state_get_format(state, pad); + csi_fmt = csi2rx_get_fmt_by_code(fmt->code); + + /* Reduce requested PPC if it is too high */ + *ppc = min(*ppc, csi_fmt->max_pixels); + + v4l2_subdev_unlock_state(state); + + csi2rx->num_pixels[pad - CSI2RX_PAD_SOURCE_STREAM0] = + CSI2RX_STREAM_CFG_NUM_PIXELS(*ppc); + + return 0; +} +EXPORT_SYMBOL_FOR_MODULES(cdns_csi2rx_negotiate_ppc, "j721e-csi2rx"); + static const struct v4l2_subdev_pad_ops csi2rx_pad_ops = { .enum_mbus_code = csi2rx_enum_mbus_code, .get_fmt = v4l2_subdev_get_fmt, @@ -468,7 +617,12 @@ static const struct v4l2_subdev_video_ops csi2rx_video_ops = { .s_stream = csi2rx_s_stream, }; +static const struct v4l2_subdev_core_ops csi2rx_core_ops = { + .log_status = csi2rx_log_status, +}; + static const struct v4l2_subdev_ops csi2rx_subdev_ops = { + .core = &csi2rx_core_ops, .video = &csi2rx_video_ops, .pad = &csi2rx_pad_ops, }; @@ -479,6 +633,7 @@ static const struct v4l2_subdev_internal_ops csi2rx_internal_ops = { static const struct media_entity_operations csi2rx_media_ops = { .link_validate = v4l2_subdev_link_validate, + .get_fwnode_pad = v4l2_subdev_get_fwnode_pad_1_to_1, }; static int csi2rx_async_bound(struct v4l2_async_notifier *notifier, @@ -705,6 +860,21 @@ static int csi2rx_probe(struct platform_device *pdev) if (ret) goto err_cleanup; + csi2rx->error_irq = platform_get_irq_byname_optional(pdev, "error_irq"); + + if (csi2rx->error_irq < 0) { + dev_dbg(csi2rx->dev, "Optional interrupt not defined, proceeding without it\n"); + } else { + ret = devm_request_irq(csi2rx->dev, csi2rx->error_irq, + csi2rx_irq_handler, 0, + dev_name(&pdev->dev), csi2rx); + if (ret) { + dev_err(csi2rx->dev, + "Unable to request interrupt: %d\n", ret); + goto err_cleanup; + } + } + ret = v4l2_subdev_init_finalize(&csi2rx->subdev); if (ret) goto err_cleanup; |