diff options
Diffstat (limited to 'drivers/gpu/drm/panel')
26 files changed, 2527 insertions, 1464 deletions
diff --git a/drivers/gpu/drm/panel/Kconfig b/drivers/gpu/drm/panel/Kconfig index 9f49b0189d3b..d3a9a9fafe4e 100644 --- a/drivers/gpu/drm/panel/Kconfig +++ b/drivers/gpu/drm/panel/Kconfig @@ -87,6 +87,15 @@ config DRM_PANEL_BOE_TV101WUM_NL6 Say Y here if you want to support for BOE TV101WUM and AUO KD101N80 45NA WUXGA PANEL DSI Video Mode panel +config DRM_PANEL_BOE_TV101WUM_LL2 + tristate "BOE TV101WUM LL2 1200x1920 panel" + depends on OF + depends on DRM_MIPI_DSI + depends on BACKLIGHT_CLASS_DEVICE + help + Say Y here if you want to support for BOE TV101WUM-LL2 + WUXGA PANEL DSI Video Mode panel + config DRM_PANEL_EBBG_FT8719 tristate "EBBG FT8719 panel driver" depends on OF @@ -784,7 +793,8 @@ config DRM_PANEL_SHARP_LS060T1SX01 config DRM_PANEL_SITRONIX_ST7701 tristate "Sitronix ST7701 panel driver" depends on OF - depends on DRM_MIPI_DSI + depends on SPI || DRM_MIPI_DSI + select DRM_MIPI_DBI if SPI depends on BACKLIGHT_CLASS_DEVICE help Say Y here if you want to enable support for the Sitronix diff --git a/drivers/gpu/drm/panel/Makefile b/drivers/gpu/drm/panel/Makefile index 5581387707c6..987a08702410 100644 --- a/drivers/gpu/drm/panel/Makefile +++ b/drivers/gpu/drm/panel/Makefile @@ -6,6 +6,7 @@ obj-$(CONFIG_DRM_PANEL_AUO_A030JTN01) += panel-auo-a030jtn01.o obj-$(CONFIG_DRM_PANEL_BOE_BF060Y8M_AJ0) += panel-boe-bf060y8m-aj0.o obj-$(CONFIG_DRM_PANEL_BOE_HIMAX8279D) += panel-boe-himax8279d.o obj-$(CONFIG_DRM_PANEL_BOE_TH101MB31UIG002_28A) += panel-boe-th101mb31ig002-28a.o +obj-$(CONFIG_DRM_PANEL_BOE_TV101WUM_LL2) += panel-boe-tv101wum-ll2.o obj-$(CONFIG_DRM_PANEL_BOE_TV101WUM_NL6) += panel-boe-tv101wum-nl6.o obj-$(CONFIG_DRM_PANEL_DSI_CM) += panel-dsi-cm.o obj-$(CONFIG_DRM_PANEL_LVDS) += panel-lvds.o diff --git a/drivers/gpu/drm/panel/panel-boe-bf060y8m-aj0.c b/drivers/gpu/drm/panel/panel-boe-bf060y8m-aj0.c index e77db8597eb7..7e66db4a88bb 100644 --- a/drivers/gpu/drm/panel/panel-boe-bf060y8m-aj0.c +++ b/drivers/gpu/drm/panel/panel-boe-bf060y8m-aj0.c @@ -377,6 +377,8 @@ static int boe_bf060y8m_aj0_probe(struct mipi_dsi_device *dsi) drm_panel_init(&boe->panel, dev, &boe_bf060y8m_aj0_panel_funcs, DRM_MODE_CONNECTOR_DSI); + boe->panel.prepare_prev_first = true; + boe->panel.backlight = boe_bf060y8m_aj0_create_backlight(dsi); if (IS_ERR(boe->panel.backlight)) return dev_err_probe(dev, PTR_ERR(boe->panel.backlight), diff --git a/drivers/gpu/drm/panel/panel-boe-th101mb31ig002-28a.c b/drivers/gpu/drm/panel/panel-boe-th101mb31ig002-28a.c index 763e9f8342d3..0b87f1e6ecae 100644 --- a/drivers/gpu/drm/panel/panel-boe-th101mb31ig002-28a.c +++ b/drivers/gpu/drm/panel/panel-boe-th101mb31ig002-28a.c @@ -16,12 +16,31 @@ #include <drm/drm_mipi_dsi.h> #include <drm/drm_modes.h> #include <drm/drm_panel.h> +#include <drm/drm_probe_helper.h> + +struct boe_th101mb31ig002; + +struct panel_desc { + const struct drm_display_mode *modes; + unsigned long mode_flags; + enum mipi_dsi_pixel_format format; + int (*init)(struct boe_th101mb31ig002 *ctx); + unsigned int lanes; + bool lp11_before_reset; + unsigned int vcioo_to_lp11_delay_ms; + unsigned int lp11_to_reset_delay_ms; + unsigned int backlight_off_to_display_off_delay_ms; + unsigned int enter_sleep_to_reset_down_delay_ms; + unsigned int power_off_delay_ms; +}; struct boe_th101mb31ig002 { struct drm_panel panel; struct mipi_dsi_device *dsi; + const struct panel_desc *desc; + struct regulator *power; struct gpio_desc *enable; struct gpio_desc *reset; @@ -39,74 +58,123 @@ static void boe_th101mb31ig002_reset(struct boe_th101mb31ig002 *ctx) usleep_range(5000, 6000); } -static int boe_th101mb31ig002_enable(struct drm_panel *panel) +static int boe_th101mb31ig002_enable(struct boe_th101mb31ig002 *ctx) { - struct boe_th101mb31ig002 *ctx = container_of(panel, - struct boe_th101mb31ig002, - panel); - struct mipi_dsi_device *dsi = ctx->dsi; - struct device *dev = &dsi->dev; - int ret; - - mipi_dsi_dcs_write_seq(dsi, 0xE0, 0xAB, 0xBA); - mipi_dsi_dcs_write_seq(dsi, 0xE1, 0xBA, 0xAB); - mipi_dsi_dcs_write_seq(dsi, 0xB1, 0x10, 0x01, 0x47, 0xFF); - mipi_dsi_dcs_write_seq(dsi, 0xB2, 0x0C, 0x14, 0x04, 0x50, 0x50, 0x14); - mipi_dsi_dcs_write_seq(dsi, 0xB3, 0x56, 0x53, 0x00); - mipi_dsi_dcs_write_seq(dsi, 0xB4, 0x33, 0x30, 0x04); - mipi_dsi_dcs_write_seq(dsi, 0xB6, 0xB0, 0x00, 0x00, 0x10, 0x00, 0x10, - 0x00); - mipi_dsi_dcs_write_seq(dsi, 0xB8, 0x05, 0x12, 0x29, 0x49, 0x48, 0x00, - 0x00); - mipi_dsi_dcs_write_seq(dsi, 0xB9, 0x7C, 0x65, 0x55, 0x49, 0x46, 0x36, - 0x3B, 0x24, 0x3D, 0x3C, 0x3D, 0x5C, 0x4C, - 0x55, 0x47, 0x46, 0x39, 0x26, 0x06, 0x7C, - 0x65, 0x55, 0x49, 0x46, 0x36, 0x3B, 0x24, - 0x3D, 0x3C, 0x3D, 0x5C, 0x4C, 0x55, 0x47, - 0x46, 0x39, 0x26, 0x06); - mipi_dsi_dcs_write_seq(dsi, 0x00, 0xFF, 0x87, 0x12, 0x34, 0x44, 0x44, - 0x44, 0x44, 0x98, 0x04, 0x98, 0x04, 0x0F, - 0x00, 0x00, 0xC1); - mipi_dsi_dcs_write_seq(dsi, 0xC1, 0x54, 0x94, 0x02, 0x85, 0x9F, 0x00, - 0x7F, 0x00, 0x54, 0x00); - mipi_dsi_dcs_write_seq(dsi, 0xC2, 0x17, 0x09, 0x08, 0x89, 0x08, 0x11, - 0x22, 0x20, 0x44, 0xFF, 0x18, 0x00); - mipi_dsi_dcs_write_seq(dsi, 0xC3, 0x86, 0x46, 0x05, 0x05, 0x1C, 0x1C, - 0x1D, 0x1D, 0x02, 0x1F, 0x1F, 0x1E, 0x1E, - 0x0F, 0x0F, 0x0D, 0x0D, 0x13, 0x13, 0x11, - 0x11, 0x00); - mipi_dsi_dcs_write_seq(dsi, 0xC4, 0x07, 0x07, 0x04, 0x04, 0x1C, 0x1C, - 0x1D, 0x1D, 0x02, 0x1F, 0x1F, 0x1E, 0x1E, - 0x0E, 0x0E, 0x0C, 0x0C, 0x12, 0x12, 0x10, - 0x10, 0x00); - mipi_dsi_dcs_write_seq(dsi, 0xC6, 0x2A, 0x2A); - mipi_dsi_dcs_write_seq(dsi, 0xC8, 0x21, 0x00, 0x31, 0x42, 0x34, 0x16); - mipi_dsi_dcs_write_seq(dsi, 0xCA, 0xCB, 0x43); - mipi_dsi_dcs_write_seq(dsi, 0xCD, 0x0E, 0x4B, 0x4B, 0x20, 0x19, 0x6B, - 0x06, 0xB3); - mipi_dsi_dcs_write_seq(dsi, 0xD2, 0xE3, 0x2B, 0x38, 0x00); - mipi_dsi_dcs_write_seq(dsi, 0xD4, 0x00, 0x01, 0x00, 0x0E, 0x04, 0x44, - 0x08, 0x10, 0x00, 0x00, 0x00); - mipi_dsi_dcs_write_seq(dsi, 0xE6, 0x80, 0x01, 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF); - mipi_dsi_dcs_write_seq(dsi, 0xF0, 0x12, 0x03, 0x20, 0x00, 0xFF); - mipi_dsi_dcs_write_seq(dsi, 0xF3, 0x00); - - ret = mipi_dsi_dcs_exit_sleep_mode(dsi); - if (ret < 0) { - dev_err(dev, "Failed to exit sleep mode: %d\n", ret); - return ret; - } - - msleep(120); - - ret = mipi_dsi_dcs_set_display_on(dsi); - if (ret < 0) { - dev_err(dev, "Failed to set panel on: %d\n", ret); - return ret; - } + struct mipi_dsi_multi_context dsi_ctx = { .dsi = ctx->dsi }; + + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xe0, 0xab, 0xba); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xe1, 0xba, 0xab); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xb1, 0x10, 0x01, 0x47, 0xff); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xb2, 0x0c, 0x14, 0x04, 0x50, 0x50, 0x14); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xb3, 0x56, 0x53, 0x00); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xb4, 0x33, 0x30, 0x04); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xb6, 0xb0, 0x00, 0x00, 0x10, 0x00, 0x10, + 0x00); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xb8, 0x05, 0x12, 0x29, 0x49, 0x48, 0x00, + 0x00); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xb9, 0x7c, 0x65, 0x55, 0x49, 0x46, 0x36, + 0x3b, 0x24, 0x3d, 0x3c, 0x3d, 0x5c, 0x4c, + 0x55, 0x47, 0x46, 0x39, 0x26, 0x06, 0x7c, + 0x65, 0x55, 0x49, 0x46, 0x36, 0x3b, 0x24, + 0x3d, 0x3c, 0x3d, 0x5c, 0x4c, 0x55, 0x47, + 0x46, 0x39, 0x26, 0x06); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x00, 0xff, 0x87, 0x12, 0x34, 0x44, 0x44, + 0x44, 0x44, 0x98, 0x04, 0x98, 0x04, 0x0f, + 0x00, 0x00, 0xc1); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xc1, 0x54, 0x94, 0x02, 0x85, 0x9f, 0x00, + 0x7f, 0x00, 0x54, 0x00); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xc2, 0x17, 0x09, 0x08, 0x89, 0x08, 0x11, + 0x22, 0x20, 0x44, 0xff, 0x18, 0x00); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xc3, 0x86, 0x46, 0x05, 0x05, 0x1c, 0x1c, + 0x1d, 0x1d, 0x02, 0x1f, 0x1f, 0x1e, 0x1e, + 0x0f, 0x0f, 0x0d, 0x0d, 0x13, 0x13, 0x11, + 0x11, 0x00); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xc4, 0x07, 0x07, 0x04, 0x04, 0x1c, 0x1c, + 0x1d, 0x1d, 0x02, 0x1f, 0x1f, 0x1e, 0x1e, + 0x0e, 0x0e, 0x0c, 0x0c, 0x12, 0x12, 0x10, + 0x10, 0x00); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xc6, 0x2a, 0x2a); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xc8, 0x21, 0x00, 0x31, 0x42, 0x34, 0x16); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xca, 0xcb, 0x43); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xcd, 0x0e, 0x4b, 0x4b, 0x20, 0x19, 0x6b, + 0x06, 0xb3); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xd2, 0xe3, 0x2b, 0x38, 0x00); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xd4, 0x00, 0x01, 0x00, 0x0e, 0x04, 0x44, + 0x08, 0x10, 0x00, 0x00, 0x00); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xe6, 0x80, 0x01, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xf0, 0x12, 0x03, 0x20, 0x00, 0xff); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xf3, 0x00); + + mipi_dsi_dcs_exit_sleep_mode_multi(&dsi_ctx); + + mipi_dsi_msleep(&dsi_ctx, 120); + + mipi_dsi_dcs_set_display_on_multi(&dsi_ctx); + + return dsi_ctx.accum_err; +} - return 0; +static int starry_er88577_init_cmd(struct boe_th101mb31ig002 *ctx) +{ + struct mipi_dsi_multi_context dsi_ctx = { .dsi = ctx->dsi }; + + msleep(70); + + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xe0, 0xab, 0xba); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xe1, 0xba, 0xab); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xb1, 0x10, 0x01, 0x47, 0xff); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xb2, 0x0c, 0x14, 0x04, 0x50, 0x50, 0x14); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xb3, 0x56, 0x53, 0x00); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xb4, 0x33, 0x30, 0x04); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xb6, 0xb0, 0x00, 0x00, 0x10, 0x00, 0x10, + 0x00); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xb8, 0x05, 0x12, 0x29, 0x49, 0x40); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xb9, 0x7c, 0x61, 0x4f, 0x42, 0x3e, 0x2d, + 0x31, 0x1a, 0x33, 0x33, 0x33, 0x52, 0x40, + 0x47, 0x38, 0x34, 0x26, 0x0e, 0x06, 0x7c, + 0x61, 0x4f, 0x42, 0x3e, 0x2d, 0x31, 0x1a, + 0x33, 0x33, 0x33, 0x52, 0x40, 0x47, 0x38, + 0x34, 0x26, 0x0e, 0x06); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xc0, 0xcc, 0x76, 0x12, 0x34, 0x44, 0x44, + 0x44, 0x44, 0x98, 0x04, 0x98, 0x04, 0x0f, + 0x00, 0x00, 0xc1); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xc1, 0x54, 0x94, 0x02, 0x85, 0x9f, 0x00, + 0x6f, 0x00, 0x54, 0x00); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xc2, 0x17, 0x09, 0x08, 0x89, 0x08, 0x11, + 0x22, 0x20, 0x44, 0xff, 0x18, 0x00); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xc3, 0x87, 0x47, 0x05, 0x05, 0x1c, 0x1c, + 0x1d, 0x1d, 0x02, 0x1e, 0x1e, 0x1f, 0x1f, + 0x0f, 0x0f, 0x0d, 0x0d, 0x13, 0x13, 0x11, + 0x11, 0x24); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xc4, 0x06, 0x06, 0x04, 0x04, 0x1c, 0x1c, + 0x1d, 0x1d, 0x02, 0x1e, 0x1e, 0x1f, 0x1f, + 0x0e, 0x0e, 0x0c, 0x0c, 0x12, 0x12, 0x10, + 0x10, 0x24); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xc8, 0x21, 0x00, 0x31, 0x42, 0x34, 0x16); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xca, 0xcb, 0x43); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xcd, 0x0e, 0x4b, 0x4b, 0x20, 0x19, 0x6b, + 0x06, 0xb3); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xd1, 0x40, 0x0d, 0xff, 0x0f); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xd2, 0xe3, 0x2b, 0x38, 0x08); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xd3, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x33, 0x20, 0x3a, 0xd5, 0x86, 0xf3); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xd4, 0x00, 0x01, 0x00, 0x0e, 0x04, 0x44, + 0x08, 0x10, 0x00, 0x00, 0x00); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xe6, 0x80, 0x09, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xf0, 0x12, 0x03, 0x20, 0x00, 0xff); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xf3, 0x00); + + mipi_dsi_dcs_exit_sleep_mode_multi(&dsi_ctx); + + mipi_dsi_msleep(&dsi_ctx, 120); + + mipi_dsi_dcs_set_display_on_multi(&dsi_ctx); + + mipi_dsi_msleep(&dsi_ctx, 20); + + return dsi_ctx.accum_err; } static int boe_th101mb31ig002_disable(struct drm_panel *panel) @@ -114,21 +182,21 @@ static int boe_th101mb31ig002_disable(struct drm_panel *panel) struct boe_th101mb31ig002 *ctx = container_of(panel, struct boe_th101mb31ig002, panel); - struct mipi_dsi_device *dsi = ctx->dsi; - struct device *dev = &dsi->dev; - int ret; + struct mipi_dsi_multi_context dsi_ctx = { .dsi = ctx->dsi }; - ret = mipi_dsi_dcs_set_display_off(dsi); - if (ret < 0) - dev_err(dev, "Failed to set panel off: %d\n", ret); + if (ctx->desc->backlight_off_to_display_off_delay_ms) + mipi_dsi_msleep(&dsi_ctx, ctx->desc->backlight_off_to_display_off_delay_ms); - msleep(120); + mipi_dsi_dcs_set_display_off_multi(&dsi_ctx); - ret = mipi_dsi_dcs_enter_sleep_mode(dsi); - if (ret < 0) - dev_err(dev, "Failed to enter sleep mode: %d\n", ret); + mipi_dsi_msleep(&dsi_ctx, 120); - return 0; + mipi_dsi_dcs_enter_sleep_mode_multi(&dsi_ctx); + + if (ctx->desc->enter_sleep_to_reset_down_delay_ms) + mipi_dsi_msleep(&dsi_ctx, ctx->desc->enter_sleep_to_reset_down_delay_ms); + + return dsi_ctx.accum_err; } static int boe_th101mb31ig002_unprepare(struct drm_panel *panel) @@ -141,6 +209,9 @@ static int boe_th101mb31ig002_unprepare(struct drm_panel *panel) gpiod_set_value_cansleep(ctx->enable, 0); regulator_disable(ctx->power); + if (ctx->desc->power_off_delay_ms) + msleep(ctx->desc->power_off_delay_ms); + return 0; } @@ -158,10 +229,25 @@ static int boe_th101mb31ig002_prepare(struct drm_panel *panel) return ret; } + if (ctx->desc->vcioo_to_lp11_delay_ms) + msleep(ctx->desc->vcioo_to_lp11_delay_ms); + + if (ctx->desc->lp11_before_reset) { + ret = mipi_dsi_dcs_nop(ctx->dsi); + if (ret) + return ret; + } + + if (ctx->desc->lp11_to_reset_delay_ms) + msleep(ctx->desc->lp11_to_reset_delay_ms); + gpiod_set_value_cansleep(ctx->enable, 1); msleep(50); boe_th101mb31ig002_reset(ctx); - boe_th101mb31ig002_enable(panel); + + ret = ctx->desc->init(ctx); + if (ret) + return ret; return 0; } @@ -181,39 +267,62 @@ static const struct drm_display_mode boe_th101mb31ig002_default_mode = { .type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED, }; +static const struct panel_desc boe_th101mb31ig002_desc = { + .modes = &boe_th101mb31ig002_default_mode, + .lanes = 4, + .format = MIPI_DSI_FMT_RGB888, + .mode_flags = MIPI_DSI_MODE_VIDEO_BURST | + MIPI_DSI_MODE_NO_EOT_PACKET | + MIPI_DSI_MODE_LPM, + .init = boe_th101mb31ig002_enable, +}; + +static const struct drm_display_mode starry_er88577_default_mode = { + .clock = (800 + 25 + 25 + 25) * (1280 + 20 + 4 + 12) * 60 / 1000, + .hdisplay = 800, + .hsync_start = 800 + 25, + .hsync_end = 800 + 25 + 25, + .htotal = 800 + 25 + 25 + 25, + .vdisplay = 1280, + .vsync_start = 1280 + 20, + .vsync_end = 1280 + 20 + 4, + .vtotal = 1280 + 20 + 4 + 12, + .width_mm = 135, + .height_mm = 216, + .type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED, +}; + +static const struct panel_desc starry_er88577_desc = { + .modes = &starry_er88577_default_mode, + .lanes = 4, + .format = MIPI_DSI_FMT_RGB888, + .mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_SYNC_PULSE | + MIPI_DSI_MODE_LPM, + .init = starry_er88577_init_cmd, + .lp11_before_reset = true, + .vcioo_to_lp11_delay_ms = 5, + .lp11_to_reset_delay_ms = 50, + .backlight_off_to_display_off_delay_ms = 100, + .enter_sleep_to_reset_down_delay_ms = 100, + .power_off_delay_ms = 1000, +}; + static int boe_th101mb31ig002_get_modes(struct drm_panel *panel, struct drm_connector *connector) { struct boe_th101mb31ig002 *ctx = container_of(panel, struct boe_th101mb31ig002, panel); - struct drm_display_mode *mode; - - mode = drm_mode_duplicate(connector->dev, - &boe_th101mb31ig002_default_mode); - if (!mode) { - dev_err(panel->dev, "Failed to add mode %ux%u@%u\n", - boe_th101mb31ig002_default_mode.hdisplay, - boe_th101mb31ig002_default_mode.vdisplay, - drm_mode_vrefresh(&boe_th101mb31ig002_default_mode)); - return -ENOMEM; - } - - drm_mode_set_name(mode); + const struct drm_display_mode *desc_mode = ctx->desc->modes; connector->display_info.bpc = 8; - connector->display_info.width_mm = mode->width_mm; - connector->display_info.height_mm = mode->height_mm; - /* * TODO: Remove once all drm drivers call * drm_connector_set_orientation_from_panel() */ drm_connector_set_panel_orientation(connector, ctx->orientation); - drm_mode_probed_add(connector, mode); - - return 1; + return drm_connector_helper_get_modes_fixed(connector, desc_mode); } static enum drm_panel_orientation @@ -237,6 +346,7 @@ static const struct drm_panel_funcs boe_th101mb31ig002_funcs = { static int boe_th101mb31ig002_dsi_probe(struct mipi_dsi_device *dsi) { struct boe_th101mb31ig002 *ctx; + const struct panel_desc *desc; int ret; ctx = devm_kzalloc(&dsi->dev, sizeof(*ctx), GFP_KERNEL); @@ -246,11 +356,11 @@ static int boe_th101mb31ig002_dsi_probe(struct mipi_dsi_device *dsi) mipi_dsi_set_drvdata(dsi, ctx); ctx->dsi = dsi; - dsi->lanes = 4; - dsi->format = MIPI_DSI_FMT_RGB888; - dsi->mode_flags = MIPI_DSI_MODE_VIDEO_BURST | - MIPI_DSI_MODE_NO_EOT_PACKET | - MIPI_DSI_MODE_LPM; + desc = of_device_get_match_data(&dsi->dev); + dsi->lanes = desc->lanes; + dsi->format = desc->format; + dsi->mode_flags = desc->mode_flags; + ctx->desc = desc; ctx->power = devm_regulator_get(&dsi->dev, "power"); if (IS_ERR(ctx->power)) @@ -262,7 +372,7 @@ static int boe_th101mb31ig002_dsi_probe(struct mipi_dsi_device *dsi) return dev_err_probe(&dsi->dev, PTR_ERR(ctx->enable), "Failed to get enable GPIO\n"); - ctx->reset = devm_gpiod_get(&dsi->dev, "reset", GPIOD_OUT_HIGH); + ctx->reset = devm_gpiod_get_optional(&dsi->dev, "reset", GPIOD_OUT_HIGH); if (IS_ERR(ctx->reset)) return dev_err_probe(&dsi->dev, PTR_ERR(ctx->reset), "Failed to get reset GPIO\n"); @@ -302,7 +412,14 @@ static void boe_th101mb31ig002_dsi_remove(struct mipi_dsi_device *dsi) } static const struct of_device_id boe_th101mb31ig002_of_match[] = { - { .compatible = "boe,th101mb31ig002-28a", }, + { + .compatible = "boe,th101mb31ig002-28a", + .data = &boe_th101mb31ig002_desc + }, + { + .compatible = "starry,er88577", + .data = &starry_er88577_desc + }, { /* sentinel */ } }; MODULE_DEVICE_TABLE(of, boe_th101mb31ig002_of_match); diff --git a/drivers/gpu/drm/panel/panel-boe-tv101wum-ll2.c b/drivers/gpu/drm/panel/panel-boe-tv101wum-ll2.c new file mode 100644 index 000000000000..50e4a5341bc6 --- /dev/null +++ b/drivers/gpu/drm/panel/panel-boe-tv101wum-ll2.c @@ -0,0 +1,241 @@ +// SPDX-License-Identifier: GPL-2.0-only +// Generated with linux-mdss-dsi-panel-driver-generator from vendor device tree: +// Copyright (c) 2013, The Linux Foundation. All rights reserved. +// Copyright (c) 2024, Neil Armstrong <neil.armstrong@linaro.org> + +#include <linux/delay.h> +#include <linux/gpio/consumer.h> +#include <linux/module.h> +#include <linux/of.h> +#include <linux/regulator/consumer.h> + +#include <drm/drm_mipi_dsi.h> +#include <drm/drm_modes.h> +#include <drm/drm_panel.h> +#include <drm/drm_probe_helper.h> + +struct boe_tv101wum_ll2 { + struct drm_panel panel; + struct mipi_dsi_device *dsi; + struct gpio_desc *reset_gpio; + struct regulator_bulk_data *supplies; +}; + +static const struct regulator_bulk_data boe_tv101wum_ll2_supplies[] = { + { .supply = "vsp" }, + { .supply = "vsn" }, +}; + +static inline struct boe_tv101wum_ll2 *to_boe_tv101wum_ll2(struct drm_panel *panel) +{ + return container_of(panel, struct boe_tv101wum_ll2, panel); +} + +static void boe_tv101wum_ll2_reset(struct boe_tv101wum_ll2 *ctx) +{ + gpiod_set_value_cansleep(ctx->reset_gpio, 0); + usleep_range(5000, 6000); + gpiod_set_value_cansleep(ctx->reset_gpio, 1); + usleep_range(5000, 6000); + gpiod_set_value_cansleep(ctx->reset_gpio, 0); + + msleep(120); +} + +static int boe_tv101wum_ll2_on(struct boe_tv101wum_ll2 *ctx) +{ + struct mipi_dsi_device *dsi = ctx->dsi; + struct mipi_dsi_multi_context dsi_ctx = { .dsi = dsi }; + + dsi->mode_flags |= MIPI_DSI_MODE_LPM; + + mipi_dsi_dcs_exit_sleep_mode_multi(&dsi_ctx); + + mipi_dsi_msleep(&dsi_ctx, 120); + + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x50, 0x5a, 0x0e); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x80, 0xff, 0x81, 0x68, 0x6c, 0x22, + 0x6d, 0x12, 0x00, 0x00, 0x00, 0x00, 0x00); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x50, 0x5a, 0x23); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x90, 0x00, 0x00); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x94, 0x2c, 0x00); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x50, 0x5a, 0x19); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xa2, 0x38); + + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x50, 0x5a, 0x0c); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x80, 0xfd); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x50, 0x00); + + mipi_dsi_dcs_set_display_on_multi(&dsi_ctx); + + mipi_dsi_msleep(&dsi_ctx, 20); + + return dsi_ctx.accum_err; +} + +static void boe_tv101wum_ll2_off(struct boe_tv101wum_ll2 *ctx) +{ + struct mipi_dsi_device *dsi = ctx->dsi; + struct mipi_dsi_multi_context dsi_ctx = { .dsi = dsi }; + + dsi->mode_flags &= ~MIPI_DSI_MODE_LPM; + + mipi_dsi_dcs_set_display_off_multi(&dsi_ctx); + + mipi_dsi_msleep(&dsi_ctx, 70); + + mipi_dsi_dcs_enter_sleep_mode_multi(&dsi_ctx); + + mipi_dsi_msleep(&dsi_ctx, 20); + + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x04, 0x5a); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x05, 0x5a); + + mipi_dsi_msleep(&dsi_ctx, 150); +} + +static int boe_tv101wum_ll2_prepare(struct drm_panel *panel) +{ + struct boe_tv101wum_ll2 *ctx = to_boe_tv101wum_ll2(panel); + int ret; + + ret = regulator_bulk_enable(ARRAY_SIZE(boe_tv101wum_ll2_supplies), + ctx->supplies); + if (ret < 0) + return ret; + + boe_tv101wum_ll2_reset(ctx); + + ret = boe_tv101wum_ll2_on(ctx); + if (ret < 0) { + gpiod_set_value_cansleep(ctx->reset_gpio, 1); + regulator_bulk_disable(ARRAY_SIZE(boe_tv101wum_ll2_supplies), + ctx->supplies); + return ret; + } + + return 0; +} + +static int boe_tv101wum_ll2_unprepare(struct drm_panel *panel) +{ + struct boe_tv101wum_ll2 *ctx = to_boe_tv101wum_ll2(panel); + + /* Ignore errors on failure, in any case set gpio and disable regulators */ + boe_tv101wum_ll2_off(ctx); + + gpiod_set_value_cansleep(ctx->reset_gpio, 1); + + regulator_bulk_disable(ARRAY_SIZE(boe_tv101wum_ll2_supplies), + ctx->supplies); + + return 0; +} + +static const struct drm_display_mode boe_tv101wum_ll2_mode = { + .clock = (1200 + 27 + 8 + 12) * (1920 + 155 + 8 + 32) * 60 / 1000, + .hdisplay = 1200, + .hsync_start = 1200 + 27, + .hsync_end = 1200 + 27 + 8, + .htotal = 1200 + 27 + 8 + 12, + .vdisplay = 1920, + .vsync_start = 1920 + 155, + .vsync_end = 1920 + 155 + 8, + .vtotal = 1920 + 155 + 8 + 32, + .width_mm = 136, + .height_mm = 217, + .type = DRM_MODE_TYPE_DRIVER, +}; + +static int boe_tv101wum_ll2_get_modes(struct drm_panel *panel, + struct drm_connector *connector) +{ + /* We do not set display_info.bpc since unset value is bpc=8 by default */ + return drm_connector_helper_get_modes_fixed(connector, &boe_tv101wum_ll2_mode); +} + +static const struct drm_panel_funcs boe_tv101wum_ll2_panel_funcs = { + .prepare = boe_tv101wum_ll2_prepare, + .unprepare = boe_tv101wum_ll2_unprepare, + .get_modes = boe_tv101wum_ll2_get_modes, +}; + +static int boe_tv101wum_ll2_probe(struct mipi_dsi_device *dsi) +{ + struct device *dev = &dsi->dev; + struct boe_tv101wum_ll2 *ctx; + int ret; + + ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL); + if (!ctx) + return -ENOMEM; + + ret = devm_regulator_bulk_get_const(&dsi->dev, + ARRAY_SIZE(boe_tv101wum_ll2_supplies), + boe_tv101wum_ll2_supplies, + &ctx->supplies); + if (ret < 0) + return ret; + + ctx->reset_gpio = devm_gpiod_get(dev, "reset", GPIOD_OUT_LOW); + if (IS_ERR(ctx->reset_gpio)) + return dev_err_probe(dev, PTR_ERR(ctx->reset_gpio), + "Failed to get reset-gpios\n"); + + ctx->dsi = dsi; + mipi_dsi_set_drvdata(dsi, ctx); + + dsi->lanes = 4; + dsi->format = MIPI_DSI_FMT_RGB888; + dsi->mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | + MIPI_DSI_MODE_VIDEO_HSE; + + drm_panel_init(&ctx->panel, dev, &boe_tv101wum_ll2_panel_funcs, + DRM_MODE_CONNECTOR_DSI); + ctx->panel.prepare_prev_first = true; + + ret = drm_panel_of_backlight(&ctx->panel); + if (ret) + return dev_err_probe(dev, ret, "Failed to get backlight\n"); + + drm_panel_add(&ctx->panel); + + ret = mipi_dsi_attach(dsi); + if (ret < 0) { + drm_panel_remove(&ctx->panel); + return dev_err_probe(dev, ret, "Failed to attach to DSI host\n"); + } + + return 0; +} + +static void boe_tv101wum_ll2_remove(struct mipi_dsi_device *dsi) +{ + struct boe_tv101wum_ll2 *ctx = mipi_dsi_get_drvdata(dsi); + int ret; + + ret = mipi_dsi_detach(dsi); + if (ret < 0) + dev_err(&dsi->dev, "Failed to detach from DSI host: %d\n", ret); + + drm_panel_remove(&ctx->panel); +} + +static const struct of_device_id boe_tv101wum_ll2_of_match[] = { + { .compatible = "boe,tv101wum-ll2" }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, boe_tv101wum_ll2_of_match); + +static struct mipi_dsi_driver boe_tv101wum_ll2_driver = { + .probe = boe_tv101wum_ll2_probe, + .remove = boe_tv101wum_ll2_remove, + .driver = { + .name = "panel-boe-tv101wum_ll2", + .of_match_table = boe_tv101wum_ll2_of_match, + }, +}; +module_mipi_dsi_driver(boe_tv101wum_ll2_driver); + +MODULE_DESCRIPTION("DRM driver for BOE TV101WUM-LL2 Panel"); +MODULE_LICENSE("GPL"); diff --git a/drivers/gpu/drm/panel/panel-boe-tv101wum-nl6.c b/drivers/gpu/drm/panel/panel-boe-tv101wum-nl6.c index ce919a980875..3e5b0d8636d0 100644 --- a/drivers/gpu/drm/panel/panel-boe-tv101wum-nl6.c +++ b/drivers/gpu/drm/panel/panel-boe-tv101wum-nl6.c @@ -54,12 +54,22 @@ struct boe_panel { struct gpio_desc *enable_gpio; }; +#define NT36523_DCS_SWITCH_PAGE 0xff + +#define nt36523_switch_page(ctx, page) \ + mipi_dsi_dcs_write_seq_multi(ctx, NT36523_DCS_SWITCH_PAGE, (page)) + +static void nt36523_enable_reload_cmds(struct mipi_dsi_multi_context *ctx) +{ + mipi_dsi_dcs_write_seq_multi(ctx, 0xfb, 0x01); +} + static int boe_tv110c9m_init(struct boe_panel *boe) { struct mipi_dsi_multi_context ctx = { .dsi = boe->dsi }; - mipi_dsi_dcs_write_seq_multi(&ctx, 0xff, 0x20); - mipi_dsi_dcs_write_seq_multi(&ctx, 0xfb, 0x01); + nt36523_switch_page(&ctx, 0x20); + nt36523_enable_reload_cmds(&ctx); mipi_dsi_dcs_write_seq_multi(&ctx, 0x05, 0xd9); mipi_dsi_dcs_write_seq_multi(&ctx, 0x07, 0x78); mipi_dsi_dcs_write_seq_multi(&ctx, 0x08, 0x5a); @@ -99,16 +109,14 @@ static int boe_tv110c9m_init(struct boe_panel *boe) mipi_dsi_dcs_write_seq_multi(&ctx, 0xbb, 0x03, 0x8e, 0x03, 0xa2, 0x03, 0xb7, 0x03, 0xe7, 0x03, 0xfd, 0x03, 0xff); - mipi_dsi_dcs_write_seq_multi(&ctx, 0xff, 0x21); - mipi_dsi_dcs_write_seq_multi(&ctx, 0xfb, 0x01); - + nt36523_switch_page(&ctx, 0x21); + nt36523_enable_reload_cmds(&ctx); mipi_dsi_dcs_write_seq_multi(&ctx, 0xb0, 0x00, 0x00, 0x00, 0x1b, 0x00, 0x45, 0x00, 0x65, 0x00, 0x81, 0x00, 0x99, 0x00, 0xae, 0x00, 0xc1); mipi_dsi_dcs_write_seq_multi(&ctx, 0xb1, 0x00, 0xd2, 0x01, 0x0b, 0x01, 0x34, 0x01, 0x76, 0x01, 0xa3, 0x01, 0xef, 0x02, 0x27, 0x02, 0x29); mipi_dsi_dcs_write_seq_multi(&ctx, 0xb2, 0x02, 0x5f, 0x02, 0x9e, 0x02, 0xc9, 0x03, 0x00, 0x03, 0x26, 0x03, 0x53, 0x03, 0x63, 0x03, 0x73); - mipi_dsi_dcs_write_seq_multi(&ctx, 0xb3, 0x03, 0x86, 0x03, 0x9a, 0x03, 0xaf, 0x03, 0xdf, 0x03, 0xf5, 0x03, 0xe0); mipi_dsi_dcs_write_seq_multi(&ctx, 0xb4, 0x00, 0x00, 0x00, 0x1b, 0x00, 0x45, 0x00, 0x65, @@ -119,89 +127,66 @@ static int boe_tv110c9m_init(struct boe_panel *boe) 0x03, 0x26, 0x03, 0x53, 0x03, 0x63, 0x03, 0x73); mipi_dsi_dcs_write_seq_multi(&ctx, 0xb7, 0x03, 0x86, 0x03, 0x9a, 0x03, 0xaf, 0x03, 0xdf, 0x03, 0xf5, 0x03, 0xe0); - mipi_dsi_dcs_write_seq_multi(&ctx, 0xb8, 0x00, 0x00, 0x00, 0x1b, 0x00, 0x45, 0x00, 0x65, 0x00, 0x81, 0x00, 0x99, 0x00, 0xae, 0x00, 0xc1); mipi_dsi_dcs_write_seq_multi(&ctx, 0xb9, 0x00, 0xd2, 0x01, 0x0b, 0x01, 0x34, 0x01, 0x76, 0x01, 0xa3, 0x01, 0xef, 0x02, 0x27, 0x02, 0x29); mipi_dsi_dcs_write_seq_multi(&ctx, 0xba, 0x02, 0x5f, 0x02, 0x9e, 0x02, 0xc9, 0x03, 0x00, 0x03, 0x26, 0x03, 0x53, 0x03, 0x63, 0x03, 0x73); - mipi_dsi_dcs_write_seq_multi(&ctx, 0xbb, 0x03, 0x86, 0x03, 0x9a, 0x03, 0xaf, 0x03, 0xdf, 0x03, 0xf5, 0x03, 0xe0); - mipi_dsi_dcs_write_seq_multi(&ctx, 0xff, 0x24); - mipi_dsi_dcs_write_seq_multi(&ctx, 0xfb, 0x01); + nt36523_switch_page(&ctx, 0x24); + nt36523_enable_reload_cmds(&ctx); mipi_dsi_dcs_write_seq_multi(&ctx, 0x00, 0x00); mipi_dsi_dcs_write_seq_multi(&ctx, 0x01, 0x00); - mipi_dsi_dcs_write_seq_multi(&ctx, 0x02, 0x1c); mipi_dsi_dcs_write_seq_multi(&ctx, 0x03, 0x1c); - mipi_dsi_dcs_write_seq_multi(&ctx, 0x04, 0x1d); mipi_dsi_dcs_write_seq_multi(&ctx, 0x05, 0x1d); - mipi_dsi_dcs_write_seq_multi(&ctx, 0x06, 0x04); mipi_dsi_dcs_write_seq_multi(&ctx, 0x07, 0x04); - mipi_dsi_dcs_write_seq_multi(&ctx, 0x08, 0x0f); mipi_dsi_dcs_write_seq_multi(&ctx, 0x09, 0x0f); - mipi_dsi_dcs_write_seq_multi(&ctx, 0x0a, 0x0e); mipi_dsi_dcs_write_seq_multi(&ctx, 0x0b, 0x0e); - mipi_dsi_dcs_write_seq_multi(&ctx, 0x0c, 0x0d); mipi_dsi_dcs_write_seq_multi(&ctx, 0x0d, 0x0d); - mipi_dsi_dcs_write_seq_multi(&ctx, 0x0e, 0x0c); mipi_dsi_dcs_write_seq_multi(&ctx, 0x0f, 0x0c); - mipi_dsi_dcs_write_seq_multi(&ctx, 0x10, 0x08); mipi_dsi_dcs_write_seq_multi(&ctx, 0x11, 0x08); - mipi_dsi_dcs_write_seq_multi(&ctx, 0x12, 0x00); mipi_dsi_dcs_write_seq_multi(&ctx, 0x13, 0x00); mipi_dsi_dcs_write_seq_multi(&ctx, 0x14, 0x00); mipi_dsi_dcs_write_seq_multi(&ctx, 0x15, 0x00); - mipi_dsi_dcs_write_seq_multi(&ctx, 0x16, 0x00); mipi_dsi_dcs_write_seq_multi(&ctx, 0x17, 0x00); - mipi_dsi_dcs_write_seq_multi(&ctx, 0x18, 0x1c); mipi_dsi_dcs_write_seq_multi(&ctx, 0x19, 0x1c); - mipi_dsi_dcs_write_seq_multi(&ctx, 0x1a, 0x1d); mipi_dsi_dcs_write_seq_multi(&ctx, 0x1b, 0x1d); - mipi_dsi_dcs_write_seq_multi(&ctx, 0x1c, 0x04); mipi_dsi_dcs_write_seq_multi(&ctx, 0x1d, 0x04); - mipi_dsi_dcs_write_seq_multi(&ctx, 0x1e, 0x0f); mipi_dsi_dcs_write_seq_multi(&ctx, 0x1f, 0x0f); - mipi_dsi_dcs_write_seq_multi(&ctx, 0x20, 0x0e); mipi_dsi_dcs_write_seq_multi(&ctx, 0x21, 0x0e); - mipi_dsi_dcs_write_seq_multi(&ctx, 0x22, 0x0d); mipi_dsi_dcs_write_seq_multi(&ctx, 0x23, 0x0d); - mipi_dsi_dcs_write_seq_multi(&ctx, 0x24, 0x0c); mipi_dsi_dcs_write_seq_multi(&ctx, 0x25, 0x0c); - mipi_dsi_dcs_write_seq_multi(&ctx, 0x26, 0x08); mipi_dsi_dcs_write_seq_multi(&ctx, 0x27, 0x08); - mipi_dsi_dcs_write_seq_multi(&ctx, 0x28, 0x00); mipi_dsi_dcs_write_seq_multi(&ctx, 0x29, 0x00); mipi_dsi_dcs_write_seq_multi(&ctx, 0x2a, 0x00); mipi_dsi_dcs_write_seq_multi(&ctx, 0x2b, 0x00); - mipi_dsi_dcs_write_seq_multi(&ctx, 0x2d, 0x20); mipi_dsi_dcs_write_seq_multi(&ctx, 0x2f, 0x0a); mipi_dsi_dcs_write_seq_multi(&ctx, 0x30, 0x44); mipi_dsi_dcs_write_seq_multi(&ctx, 0x33, 0x0c); mipi_dsi_dcs_write_seq_multi(&ctx, 0x34, 0x32); - mipi_dsi_dcs_write_seq_multi(&ctx, 0x37, 0x44); mipi_dsi_dcs_write_seq_multi(&ctx, 0x38, 0x40); mipi_dsi_dcs_write_seq_multi(&ctx, 0x39, 0x00); @@ -244,7 +229,6 @@ static int boe_tv110c9m_init(struct boe_panel *boe) mipi_dsi_dcs_write_seq_multi(&ctx, 0xdb, 0x05); mipi_dsi_dcs_write_seq_multi(&ctx, 0xdc, 0xa9); mipi_dsi_dcs_write_seq_multi(&ctx, 0xdd, 0x22); - mipi_dsi_dcs_write_seq_multi(&ctx, 0xdf, 0x05); mipi_dsi_dcs_write_seq_multi(&ctx, 0xe0, 0xa9); mipi_dsi_dcs_write_seq_multi(&ctx, 0xe1, 0x05); @@ -258,8 +242,9 @@ static int boe_tv110c9m_init(struct boe_panel *boe) mipi_dsi_dcs_write_seq_multi(&ctx, 0x8d, 0x00); mipi_dsi_dcs_write_seq_multi(&ctx, 0x8e, 0x00); mipi_dsi_dcs_write_seq_multi(&ctx, 0xb5, 0x90); - mipi_dsi_dcs_write_seq_multi(&ctx, 0xff, 0x25); - mipi_dsi_dcs_write_seq_multi(&ctx, 0xfb, 0x01); + + nt36523_switch_page(&ctx, 0x25); + nt36523_enable_reload_cmds(&ctx); mipi_dsi_dcs_write_seq_multi(&ctx, 0x05, 0x00); mipi_dsi_dcs_write_seq_multi(&ctx, 0x19, 0x07); mipi_dsi_dcs_write_seq_multi(&ctx, 0x1f, 0x60); @@ -281,26 +266,22 @@ static int boe_tv110c9m_init(struct boe_panel *boe) mipi_dsi_dcs_write_seq_multi(&ctx, 0x61, 0x60); mipi_dsi_dcs_write_seq_multi(&ctx, 0x62, 0x50); mipi_dsi_dcs_write_seq_multi(&ctx, 0xf1, 0x10); - mipi_dsi_dcs_write_seq_multi(&ctx, 0xff, 0x2a); - mipi_dsi_dcs_write_seq_multi(&ctx, 0xfb, 0x01); + nt36523_switch_page(&ctx, 0x2a); + nt36523_enable_reload_cmds(&ctx); mipi_dsi_dcs_write_seq_multi(&ctx, 0x64, 0x16); mipi_dsi_dcs_write_seq_multi(&ctx, 0x67, 0x16); mipi_dsi_dcs_write_seq_multi(&ctx, 0x6a, 0x16); - mipi_dsi_dcs_write_seq_multi(&ctx, 0x70, 0x30); - mipi_dsi_dcs_write_seq_multi(&ctx, 0xa2, 0xf3); mipi_dsi_dcs_write_seq_multi(&ctx, 0xa3, 0xff); mipi_dsi_dcs_write_seq_multi(&ctx, 0xa4, 0xff); mipi_dsi_dcs_write_seq_multi(&ctx, 0xa5, 0xff); - mipi_dsi_dcs_write_seq_multi(&ctx, 0xd6, 0x08); - mipi_dsi_dcs_write_seq_multi(&ctx, 0xff, 0x26); - mipi_dsi_dcs_write_seq_multi(&ctx, 0xfb, 0x01); + nt36523_switch_page(&ctx, 0x26); + nt36523_enable_reload_cmds(&ctx); mipi_dsi_dcs_write_seq_multi(&ctx, 0x00, 0xa1); - mipi_dsi_dcs_write_seq_multi(&ctx, 0x02, 0x31); mipi_dsi_dcs_write_seq_multi(&ctx, 0x04, 0x28); mipi_dsi_dcs_write_seq_multi(&ctx, 0x06, 0x30); @@ -323,7 +304,6 @@ static int boe_tv110c9m_init(struct boe_panel *boe) mipi_dsi_dcs_write_seq_multi(&ctx, 0x23, 0x00); mipi_dsi_dcs_write_seq_multi(&ctx, 0x2a, 0x0d); mipi_dsi_dcs_write_seq_multi(&ctx, 0x2b, 0x7f); - mipi_dsi_dcs_write_seq_multi(&ctx, 0x1d, 0x00); mipi_dsi_dcs_write_seq_multi(&ctx, 0x1e, 0x65); mipi_dsi_dcs_write_seq_multi(&ctx, 0x1f, 0x65); @@ -343,7 +323,6 @@ static int boe_tv110c9m_init(struct boe_panel *boe) mipi_dsi_dcs_write_seq_multi(&ctx, 0xc9, 0x9e); mipi_dsi_dcs_write_seq_multi(&ctx, 0xca, 0x4e); mipi_dsi_dcs_write_seq_multi(&ctx, 0xcb, 0x00); - mipi_dsi_dcs_write_seq_multi(&ctx, 0xa9, 0x49); mipi_dsi_dcs_write_seq_multi(&ctx, 0xaa, 0x4b); mipi_dsi_dcs_write_seq_multi(&ctx, 0xab, 0x48); @@ -373,9 +352,9 @@ static int boe_tv110c9m_init(struct boe_panel *boe) mipi_dsi_dcs_write_seq_multi(&ctx, 0xc3, 0x4f); mipi_dsi_dcs_write_seq_multi(&ctx, 0xc4, 0x3a); mipi_dsi_dcs_write_seq_multi(&ctx, 0xc5, 0x42); - mipi_dsi_dcs_write_seq_multi(&ctx, 0xff, 0x27); - mipi_dsi_dcs_write_seq_multi(&ctx, 0xfb, 0x01); + nt36523_switch_page(&ctx, 0x27); + nt36523_enable_reload_cmds(&ctx); mipi_dsi_dcs_write_seq_multi(&ctx, 0x56, 0x06); mipi_dsi_dcs_write_seq_multi(&ctx, 0x58, 0x80); mipi_dsi_dcs_write_seq_multi(&ctx, 0x59, 0x75); @@ -394,17 +373,14 @@ static int boe_tv110c9m_init(struct boe_panel *boe) mipi_dsi_dcs_write_seq_multi(&ctx, 0x66, 0x00); mipi_dsi_dcs_write_seq_multi(&ctx, 0x67, 0x01); mipi_dsi_dcs_write_seq_multi(&ctx, 0x68, 0x44); - mipi_dsi_dcs_write_seq_multi(&ctx, 0x00, 0x00); mipi_dsi_dcs_write_seq_multi(&ctx, 0x78, 0x00); mipi_dsi_dcs_write_seq_multi(&ctx, 0xc3, 0x00); - mipi_dsi_dcs_write_seq_multi(&ctx, 0xff, 0x2a); - mipi_dsi_dcs_write_seq_multi(&ctx, 0xfb, 0x01); - + nt36523_switch_page(&ctx, 0x2a); + nt36523_enable_reload_cmds(&ctx); mipi_dsi_dcs_write_seq_multi(&ctx, 0x22, 0x2f); mipi_dsi_dcs_write_seq_multi(&ctx, 0x23, 0x08); - mipi_dsi_dcs_write_seq_multi(&ctx, 0x24, 0x00); mipi_dsi_dcs_write_seq_multi(&ctx, 0x25, 0x65); mipi_dsi_dcs_write_seq_multi(&ctx, 0x26, 0xf8); @@ -415,30 +391,30 @@ static int boe_tv110c9m_init(struct boe_panel *boe) mipi_dsi_dcs_write_seq_multi(&ctx, 0x2b, 0x00); mipi_dsi_dcs_write_seq_multi(&ctx, 0x2d, 0x1a); - mipi_dsi_dcs_write_seq_multi(&ctx, 0xff, 0x23); - mipi_dsi_dcs_write_seq_multi(&ctx, 0xfb, 0x01); - + nt36523_switch_page(&ctx, 0x23); + nt36523_enable_reload_cmds(&ctx); mipi_dsi_dcs_write_seq_multi(&ctx, 0x00, 0x80); mipi_dsi_dcs_write_seq_multi(&ctx, 0x07, 0x00); - mipi_dsi_dcs_write_seq_multi(&ctx, 0xff, 0xe0); - mipi_dsi_dcs_write_seq_multi(&ctx, 0xfb, 0x01); + nt36523_switch_page(&ctx, 0xe0); + nt36523_enable_reload_cmds(&ctx); mipi_dsi_dcs_write_seq_multi(&ctx, 0x14, 0x60); mipi_dsi_dcs_write_seq_multi(&ctx, 0x16, 0xc0); - mipi_dsi_dcs_write_seq_multi(&ctx, 0xff, 0xf0); - mipi_dsi_dcs_write_seq_multi(&ctx, 0xfb, 0x01); + nt36523_switch_page(&ctx, 0xf0); + nt36523_enable_reload_cmds(&ctx); mipi_dsi_dcs_write_seq_multi(&ctx, 0x3a, 0x08); - mipi_dsi_dcs_write_seq_multi(&ctx, 0xff, 0x10); - mipi_dsi_dcs_write_seq_multi(&ctx, 0xfb, 0x01); + nt36523_switch_page(&ctx, 0x10); + nt36523_enable_reload_cmds(&ctx); mipi_dsi_dcs_write_seq_multi(&ctx, 0xb9, 0x01); - mipi_dsi_dcs_write_seq_multi(&ctx, 0xff, 0x20); - mipi_dsi_dcs_write_seq_multi(&ctx, 0xfb, 0x01); + + nt36523_switch_page(&ctx, 0x20); + nt36523_enable_reload_cmds(&ctx); mipi_dsi_dcs_write_seq_multi(&ctx, 0x18, 0x40); - mipi_dsi_dcs_write_seq_multi(&ctx, 0xff, 0x10); - mipi_dsi_dcs_write_seq_multi(&ctx, 0xfb, 0x01); + nt36523_switch_page(&ctx, 0x10); + nt36523_enable_reload_cmds(&ctx); mipi_dsi_dcs_write_seq_multi(&ctx, 0xb9, 0x02); mipi_dsi_dcs_write_seq_multi(&ctx, 0x35, 0x00); mipi_dsi_dcs_write_seq_multi(&ctx, 0x51, 0x00, 0xff); @@ -464,13 +440,12 @@ static int inx_hj110iz_init(struct boe_panel *boe) { struct mipi_dsi_multi_context ctx = { .dsi = boe->dsi }; - mipi_dsi_dcs_write_seq_multi(&ctx, 0xff, 0x20); - mipi_dsi_dcs_write_seq_multi(&ctx, 0xfb, 0x01); + nt36523_switch_page(&ctx, 0x20); + nt36523_enable_reload_cmds(&ctx); mipi_dsi_dcs_write_seq_multi(&ctx, 0x05, 0xd1); mipi_dsi_dcs_write_seq_multi(&ctx, 0x06, 0xc0); mipi_dsi_dcs_write_seq_multi(&ctx, 0x07, 0x87); mipi_dsi_dcs_write_seq_multi(&ctx, 0x08, 0x4b); - mipi_dsi_dcs_write_seq_multi(&ctx, 0x0d, 0x63); mipi_dsi_dcs_write_seq_multi(&ctx, 0x0e, 0x91); mipi_dsi_dcs_write_seq_multi(&ctx, 0x0f, 0x69); @@ -482,10 +457,10 @@ static int inx_hj110iz_init(struct boe_panel *boe) mipi_dsi_dcs_write_seq_multi(&ctx, 0x69, 0x98); mipi_dsi_dcs_write_seq_multi(&ctx, 0x75, 0xa2); mipi_dsi_dcs_write_seq_multi(&ctx, 0x77, 0xb3); - mipi_dsi_dcs_write_seq_multi(&ctx, 0x58, 0x43); - mipi_dsi_dcs_write_seq_multi(&ctx, 0xff, 0x24); - mipi_dsi_dcs_write_seq_multi(&ctx, 0xfb, 0x01); + + nt36523_switch_page(&ctx, 0x24); + nt36523_enable_reload_cmds(&ctx); mipi_dsi_dcs_write_seq_multi(&ctx, 0x91, 0x44); mipi_dsi_dcs_write_seq_multi(&ctx, 0x92, 0x4c); mipi_dsi_dcs_write_seq_multi(&ctx, 0x94, 0x86); @@ -493,7 +468,6 @@ static int inx_hj110iz_init(struct boe_panel *boe) mipi_dsi_dcs_write_seq_multi(&ctx, 0x61, 0xd0); mipi_dsi_dcs_write_seq_multi(&ctx, 0x63, 0x70); mipi_dsi_dcs_write_seq_multi(&ctx, 0xc2, 0xca); - mipi_dsi_dcs_write_seq_multi(&ctx, 0x00, 0x03); mipi_dsi_dcs_write_seq_multi(&ctx, 0x01, 0x03); mipi_dsi_dcs_write_seq_multi(&ctx, 0x02, 0x03); @@ -538,7 +512,6 @@ static int inx_hj110iz_init(struct boe_panel *boe) mipi_dsi_dcs_write_seq_multi(&ctx, 0x29, 0x04); mipi_dsi_dcs_write_seq_multi(&ctx, 0x2a, 0x00); mipi_dsi_dcs_write_seq_multi(&ctx, 0x2b, 0x03); - mipi_dsi_dcs_write_seq_multi(&ctx, 0x2f, 0x0a); mipi_dsi_dcs_write_seq_multi(&ctx, 0x30, 0x35); mipi_dsi_dcs_write_seq_multi(&ctx, 0x37, 0xa7); @@ -546,7 +519,6 @@ static int inx_hj110iz_init(struct boe_panel *boe) mipi_dsi_dcs_write_seq_multi(&ctx, 0x3a, 0x46); mipi_dsi_dcs_write_seq_multi(&ctx, 0x3b, 0x32); mipi_dsi_dcs_write_seq_multi(&ctx, 0x3d, 0x12); - mipi_dsi_dcs_write_seq_multi(&ctx, 0x3f, 0x33); mipi_dsi_dcs_write_seq_multi(&ctx, 0x40, 0x31); mipi_dsi_dcs_write_seq_multi(&ctx, 0x41, 0x40); @@ -556,7 +528,6 @@ static int inx_hj110iz_init(struct boe_panel *boe) mipi_dsi_dcs_write_seq_multi(&ctx, 0x4a, 0x45); mipi_dsi_dcs_write_seq_multi(&ctx, 0x4b, 0x45); mipi_dsi_dcs_write_seq_multi(&ctx, 0x4c, 0x14); - mipi_dsi_dcs_write_seq_multi(&ctx, 0x4d, 0x21); mipi_dsi_dcs_write_seq_multi(&ctx, 0x4e, 0x43); mipi_dsi_dcs_write_seq_multi(&ctx, 0x4f, 0x65); @@ -569,7 +540,6 @@ static int inx_hj110iz_init(struct boe_panel *boe) mipi_dsi_dcs_write_seq_multi(&ctx, 0x5c, 0x88); mipi_dsi_dcs_write_seq_multi(&ctx, 0x5e, 0x00, 0x00); mipi_dsi_dcs_write_seq_multi(&ctx, 0x5f, 0x00); - mipi_dsi_dcs_write_seq_multi(&ctx, 0x7a, 0xff); mipi_dsi_dcs_write_seq_multi(&ctx, 0x7b, 0xff); mipi_dsi_dcs_write_seq_multi(&ctx, 0x7c, 0x00); @@ -581,7 +551,6 @@ static int inx_hj110iz_init(struct boe_panel *boe) mipi_dsi_dcs_write_seq_multi(&ctx, 0x82, 0x08); mipi_dsi_dcs_write_seq_multi(&ctx, 0x97, 0x02); mipi_dsi_dcs_write_seq_multi(&ctx, 0xc5, 0x10); - mipi_dsi_dcs_write_seq_multi(&ctx, 0xd7, 0x55); mipi_dsi_dcs_write_seq_multi(&ctx, 0xd8, 0x55); mipi_dsi_dcs_write_seq_multi(&ctx, 0xd9, 0x23); @@ -609,43 +578,32 @@ static int inx_hj110iz_init(struct boe_panel *boe) mipi_dsi_dcs_write_seq_multi(&ctx, 0xb6, 0x05, 0x00, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x05, 0x05, 0x00, 0x00); - mipi_dsi_dcs_write_seq_multi(&ctx, 0xff, 0x25); - - mipi_dsi_dcs_write_seq_multi(&ctx, 0xfb, 0x01); + nt36523_switch_page(&ctx, 0x25); + nt36523_enable_reload_cmds(&ctx); mipi_dsi_dcs_write_seq_multi(&ctx, 0x05, 0x00); mipi_dsi_dcs_write_seq_multi(&ctx, 0xf1, 0x10); - mipi_dsi_dcs_write_seq_multi(&ctx, 0x1e, 0x00); mipi_dsi_dcs_write_seq_multi(&ctx, 0x1f, 0x46); mipi_dsi_dcs_write_seq_multi(&ctx, 0x20, 0x32); - mipi_dsi_dcs_write_seq_multi(&ctx, 0x25, 0x00); mipi_dsi_dcs_write_seq_multi(&ctx, 0x26, 0x46); mipi_dsi_dcs_write_seq_multi(&ctx, 0x27, 0x32); - mipi_dsi_dcs_write_seq_multi(&ctx, 0x3f, 0x80); mipi_dsi_dcs_write_seq_multi(&ctx, 0x40, 0x00); mipi_dsi_dcs_write_seq_multi(&ctx, 0x43, 0x00); - mipi_dsi_dcs_write_seq_multi(&ctx, 0x44, 0x46); mipi_dsi_dcs_write_seq_multi(&ctx, 0x45, 0x46); - mipi_dsi_dcs_write_seq_multi(&ctx, 0x48, 0x46); mipi_dsi_dcs_write_seq_multi(&ctx, 0x49, 0x32); - mipi_dsi_dcs_write_seq_multi(&ctx, 0x5b, 0x80); - mipi_dsi_dcs_write_seq_multi(&ctx, 0x5c, 0x00); mipi_dsi_dcs_write_seq_multi(&ctx, 0x5d, 0x46); mipi_dsi_dcs_write_seq_multi(&ctx, 0x5e, 0x32); - mipi_dsi_dcs_write_seq_multi(&ctx, 0x5f, 0x46); mipi_dsi_dcs_write_seq_multi(&ctx, 0x60, 0x32); - mipi_dsi_dcs_write_seq_multi(&ctx, 0x61, 0x46); mipi_dsi_dcs_write_seq_multi(&ctx, 0x62, 0x32); mipi_dsi_dcs_write_seq_multi(&ctx, 0x68, 0x0c); - mipi_dsi_dcs_write_seq_multi(&ctx, 0x6c, 0x0d); mipi_dsi_dcs_write_seq_multi(&ctx, 0x6e, 0x0d); mipi_dsi_dcs_write_seq_multi(&ctx, 0x78, 0x00); @@ -653,9 +611,8 @@ static int inx_hj110iz_init(struct boe_panel *boe) mipi_dsi_dcs_write_seq_multi(&ctx, 0x7a, 0x0c); mipi_dsi_dcs_write_seq_multi(&ctx, 0x7b, 0xb0); - mipi_dsi_dcs_write_seq_multi(&ctx, 0xff, 0x26); - mipi_dsi_dcs_write_seq_multi(&ctx, 0xfb, 0x01); - + nt36523_switch_page(&ctx, 0x26); + nt36523_enable_reload_cmds(&ctx); mipi_dsi_dcs_write_seq_multi(&ctx, 0x00, 0xa1); mipi_dsi_dcs_write_seq_multi(&ctx, 0x02, 0x31); mipi_dsi_dcs_write_seq_multi(&ctx, 0x0a, 0xf4); @@ -674,18 +631,15 @@ static int inx_hj110iz_init(struct boe_panel *boe) mipi_dsi_dcs_write_seq_multi(&ctx, 0x18, 0x86); mipi_dsi_dcs_write_seq_multi(&ctx, 0x22, 0x00); mipi_dsi_dcs_write_seq_multi(&ctx, 0x23, 0x00); - mipi_dsi_dcs_write_seq_multi(&ctx, 0x19, 0x0e); mipi_dsi_dcs_write_seq_multi(&ctx, 0x1a, 0x31); mipi_dsi_dcs_write_seq_multi(&ctx, 0x1b, 0x0d); mipi_dsi_dcs_write_seq_multi(&ctx, 0x1c, 0x29); mipi_dsi_dcs_write_seq_multi(&ctx, 0x2a, 0x0e); mipi_dsi_dcs_write_seq_multi(&ctx, 0x2b, 0x31); - mipi_dsi_dcs_write_seq_multi(&ctx, 0x1d, 0x00); mipi_dsi_dcs_write_seq_multi(&ctx, 0x1e, 0x62); mipi_dsi_dcs_write_seq_multi(&ctx, 0x1f, 0x62); - mipi_dsi_dcs_write_seq_multi(&ctx, 0x2f, 0x06); mipi_dsi_dcs_write_seq_multi(&ctx, 0x30, 0x62); mipi_dsi_dcs_write_seq_multi(&ctx, 0x31, 0x06); @@ -693,11 +647,9 @@ static int inx_hj110iz_init(struct boe_panel *boe) mipi_dsi_dcs_write_seq_multi(&ctx, 0x33, 0x11); mipi_dsi_dcs_write_seq_multi(&ctx, 0x34, 0x89); mipi_dsi_dcs_write_seq_multi(&ctx, 0x35, 0x67); - mipi_dsi_dcs_write_seq_multi(&ctx, 0x39, 0x0b); mipi_dsi_dcs_write_seq_multi(&ctx, 0x3a, 0x62); mipi_dsi_dcs_write_seq_multi(&ctx, 0x3b, 0x06); - mipi_dsi_dcs_write_seq_multi(&ctx, 0xc8, 0x04); mipi_dsi_dcs_write_seq_multi(&ctx, 0xc9, 0x89); mipi_dsi_dcs_write_seq_multi(&ctx, 0xca, 0x4e); @@ -711,21 +663,18 @@ static int inx_hj110iz_init(struct boe_panel *boe) mipi_dsi_dcs_write_seq_multi(&ctx, 0xaf, 0x39); mipi_dsi_dcs_write_seq_multi(&ctx, 0xb0, 0x38); - mipi_dsi_dcs_write_seq_multi(&ctx, 0xff, 0x27); - mipi_dsi_dcs_write_seq_multi(&ctx, 0xfb, 0x01); - + nt36523_switch_page(&ctx, 0x27); + nt36523_enable_reload_cmds(&ctx); mipi_dsi_dcs_write_seq_multi(&ctx, 0xd0, 0x11); mipi_dsi_dcs_write_seq_multi(&ctx, 0xd1, 0x54); mipi_dsi_dcs_write_seq_multi(&ctx, 0xde, 0x43); mipi_dsi_dcs_write_seq_multi(&ctx, 0xdf, 0x02); - mipi_dsi_dcs_write_seq_multi(&ctx, 0xc0, 0x18); mipi_dsi_dcs_write_seq_multi(&ctx, 0xc1, 0x00); mipi_dsi_dcs_write_seq_multi(&ctx, 0xc2, 0x00); mipi_dsi_dcs_write_seq_multi(&ctx, 0x00, 0x00); mipi_dsi_dcs_write_seq_multi(&ctx, 0xc3, 0x00); mipi_dsi_dcs_write_seq_multi(&ctx, 0x56, 0x06); - mipi_dsi_dcs_write_seq_multi(&ctx, 0x58, 0x80); mipi_dsi_dcs_write_seq_multi(&ctx, 0x59, 0x78); mipi_dsi_dcs_write_seq_multi(&ctx, 0x5a, 0x00); @@ -743,20 +692,17 @@ static int inx_hj110iz_init(struct boe_panel *boe) mipi_dsi_dcs_write_seq_multi(&ctx, 0x66, 0x00); mipi_dsi_dcs_write_seq_multi(&ctx, 0x67, 0x01); mipi_dsi_dcs_write_seq_multi(&ctx, 0x68, 0x44); - mipi_dsi_dcs_write_seq_multi(&ctx, 0x98, 0x01); mipi_dsi_dcs_write_seq_multi(&ctx, 0xb4, 0x03); mipi_dsi_dcs_write_seq_multi(&ctx, 0x9b, 0xbe); - mipi_dsi_dcs_write_seq_multi(&ctx, 0xab, 0x14); mipi_dsi_dcs_write_seq_multi(&ctx, 0xbc, 0x08); mipi_dsi_dcs_write_seq_multi(&ctx, 0xbd, 0x28); - mipi_dsi_dcs_write_seq_multi(&ctx, 0xff, 0x2a); - mipi_dsi_dcs_write_seq_multi(&ctx, 0xfb, 0x01); + nt36523_switch_page(&ctx, 0x2a); + nt36523_enable_reload_cmds(&ctx); mipi_dsi_dcs_write_seq_multi(&ctx, 0x22, 0x2f); mipi_dsi_dcs_write_seq_multi(&ctx, 0x23, 0x08); - mipi_dsi_dcs_write_seq_multi(&ctx, 0x24, 0x00); mipi_dsi_dcs_write_seq_multi(&ctx, 0x25, 0x62); mipi_dsi_dcs_write_seq_multi(&ctx, 0x26, 0xf8); @@ -766,7 +712,6 @@ static int inx_hj110iz_init(struct boe_panel *boe) mipi_dsi_dcs_write_seq_multi(&ctx, 0x2a, 0x1a); mipi_dsi_dcs_write_seq_multi(&ctx, 0x2b, 0x00); mipi_dsi_dcs_write_seq_multi(&ctx, 0x2d, 0x1a); - mipi_dsi_dcs_write_seq_multi(&ctx, 0x64, 0x96); mipi_dsi_dcs_write_seq_multi(&ctx, 0x65, 0x10); mipi_dsi_dcs_write_seq_multi(&ctx, 0x66, 0x00); @@ -783,14 +728,11 @@ static int inx_hj110iz_init(struct boe_panel *boe) mipi_dsi_dcs_write_seq_multi(&ctx, 0x7a, 0x10); mipi_dsi_dcs_write_seq_multi(&ctx, 0x88, 0x96); mipi_dsi_dcs_write_seq_multi(&ctx, 0x89, 0x10); - mipi_dsi_dcs_write_seq_multi(&ctx, 0xa2, 0x3f); mipi_dsi_dcs_write_seq_multi(&ctx, 0xa3, 0x30); mipi_dsi_dcs_write_seq_multi(&ctx, 0xa4, 0xc0); mipi_dsi_dcs_write_seq_multi(&ctx, 0xa5, 0x03); - mipi_dsi_dcs_write_seq_multi(&ctx, 0xe8, 0x00); - mipi_dsi_dcs_write_seq_multi(&ctx, 0x97, 0x3c); mipi_dsi_dcs_write_seq_multi(&ctx, 0x98, 0x02); mipi_dsi_dcs_write_seq_multi(&ctx, 0x99, 0x95); @@ -800,7 +742,7 @@ static int inx_hj110iz_init(struct boe_panel *boe) mipi_dsi_dcs_write_seq_multi(&ctx, 0x9d, 0x0a); mipi_dsi_dcs_write_seq_multi(&ctx, 0x9e, 0x90); - mipi_dsi_dcs_write_seq_multi(&ctx, 0xff, 0x25); + nt36523_switch_page(&ctx, 0x25); mipi_dsi_dcs_write_seq_multi(&ctx, 0x13, 0x02); mipi_dsi_dcs_write_seq_multi(&ctx, 0x14, 0xd7); mipi_dsi_dcs_write_seq_multi(&ctx, 0xdb, 0x02); @@ -809,8 +751,7 @@ static int inx_hj110iz_init(struct boe_panel *boe) mipi_dsi_dcs_write_seq_multi(&ctx, 0x19, 0x0f); mipi_dsi_dcs_write_seq_multi(&ctx, 0x1b, 0x5b); - mipi_dsi_dcs_write_seq_multi(&ctx, 0xff, 0x20); - + nt36523_switch_page(&ctx, 0x20); mipi_dsi_dcs_write_seq_multi(&ctx, 0xb0, 0x00, 0x00, 0x00, 0x0c, 0x00, 0x24, 0x00, 0x38, 0x00, 0x4c, 0x00, 0x5e, 0x00, 0x6f, 0x00, 0x7e); mipi_dsi_dcs_write_seq_multi(&ctx, 0xb1, 0x00, 0x8c, 0x00, 0xbe, 0x00, 0xe5, 0x01, 0x27, @@ -819,7 +760,6 @@ static int inx_hj110iz_init(struct boe_panel *boe) 0x03, 0x00, 0x03, 0x31, 0x03, 0x40, 0x03, 0x51); mipi_dsi_dcs_write_seq_multi(&ctx, 0xb3, 0x03, 0x62, 0x03, 0x75, 0x03, 0x89, 0x03, 0x9c, 0x03, 0xaa, 0x03, 0xb2); - mipi_dsi_dcs_write_seq_multi(&ctx, 0xb4, 0x00, 0x00, 0x00, 0x0d, 0x00, 0x27, 0x00, 0x3d, 0x00, 0x52, 0x00, 0x64, 0x00, 0x75, 0x00, 0x84); mipi_dsi_dcs_write_seq_multi(&ctx, 0xb5, 0x00, 0x93, 0x00, 0xc5, 0x00, 0xec, 0x01, 0x2c, @@ -828,7 +768,6 @@ static int inx_hj110iz_init(struct boe_panel *boe) 0x03, 0x01, 0x03, 0x31, 0x03, 0x41, 0x03, 0x51); mipi_dsi_dcs_write_seq_multi(&ctx, 0xb7, 0x03, 0x63, 0x03, 0x75, 0x03, 0x89, 0x03, 0x9c, 0x03, 0xaa, 0x03, 0xb2); - mipi_dsi_dcs_write_seq_multi(&ctx, 0xb8, 0x00, 0x00, 0x00, 0x0e, 0x00, 0x2a, 0x00, 0x40, 0x00, 0x56, 0x00, 0x68, 0x00, 0x7a, 0x00, 0x89); mipi_dsi_dcs_write_seq_multi(&ctx, 0xb9, 0x00, 0x98, 0x00, 0xc9, 0x00, 0xf1, 0x01, 0x30, @@ -838,7 +777,7 @@ static int inx_hj110iz_init(struct boe_panel *boe) mipi_dsi_dcs_write_seq_multi(&ctx, 0xbb, 0x03, 0x66, 0x03, 0x75, 0x03, 0x89, 0x03, 0x9c, 0x03, 0xaa, 0x03, 0xb2); - mipi_dsi_dcs_write_seq_multi(&ctx, 0xff, 0x21); + nt36523_switch_page(&ctx, 0x21); mipi_dsi_dcs_write_seq_multi(&ctx, 0xb0, 0x00, 0x00, 0x00, 0x0c, 0x00, 0x24, 0x00, 0x38, 0x00, 0x4c, 0x00, 0x5e, 0x00, 0x6f, 0x00, 0x7e); mipi_dsi_dcs_write_seq_multi(&ctx, 0xb1, 0x00, 0x8c, 0x00, 0xbe, 0x00, 0xe5, 0x01, 0x27, @@ -847,7 +786,6 @@ static int inx_hj110iz_init(struct boe_panel *boe) 0x03, 0x00, 0x03, 0x31, 0x03, 0x40, 0x03, 0x51); mipi_dsi_dcs_write_seq_multi(&ctx, 0xb3, 0x03, 0x62, 0x03, 0x77, 0x03, 0x90, 0x03, 0xac, 0x03, 0xca, 0x03, 0xda); - mipi_dsi_dcs_write_seq_multi(&ctx, 0xb4, 0x00, 0x00, 0x00, 0x0d, 0x00, 0x27, 0x00, 0x3d, 0x00, 0x52, 0x00, 0x64, 0x00, 0x75, 0x00, 0x84); mipi_dsi_dcs_write_seq_multi(&ctx, 0xb5, 0x00, 0x93, 0x00, 0xc5, 0x00, 0xec, 0x01, 0x2c, @@ -856,7 +794,6 @@ static int inx_hj110iz_init(struct boe_panel *boe) 0x03, 0x01, 0x03, 0x31, 0x03, 0x41, 0x03, 0x51); mipi_dsi_dcs_write_seq_multi(&ctx, 0xb7, 0x03, 0x63, 0x03, 0x77, 0x03, 0x90, 0x03, 0xac, 0x03, 0xca, 0x03, 0xda); - mipi_dsi_dcs_write_seq_multi(&ctx, 0xb8, 0x00, 0x00, 0x00, 0x0e, 0x00, 0x2a, 0x00, 0x40, 0x00, 0x56, 0x00, 0x68, 0x00, 0x7a, 0x00, 0x89); mipi_dsi_dcs_write_seq_multi(&ctx, 0xb9, 0x00, 0x98, 0x00, 0xc9, 0x00, 0xf1, 0x01, 0x30, @@ -866,22 +803,21 @@ static int inx_hj110iz_init(struct boe_panel *boe) mipi_dsi_dcs_write_seq_multi(&ctx, 0xbb, 0x03, 0x66, 0x03, 0x77, 0x03, 0x90, 0x03, 0xac, 0x03, 0xca, 0x03, 0xda); - mipi_dsi_dcs_write_seq_multi(&ctx, 0xff, 0xf0); - mipi_dsi_dcs_write_seq_multi(&ctx, 0xfb, 0x01); + nt36523_switch_page(&ctx, 0xf0); + nt36523_enable_reload_cmds(&ctx); mipi_dsi_dcs_write_seq_multi(&ctx, 0x3a, 0x08); - mipi_dsi_dcs_write_seq_multi(&ctx, 0xff, 0x10); + nt36523_switch_page(&ctx, 0x10); mipi_dsi_dcs_write_seq_multi(&ctx, 0xb9, 0x01); - mipi_dsi_dcs_write_seq_multi(&ctx, 0xff, 0x20); - + nt36523_switch_page(&ctx, 0x20); mipi_dsi_dcs_write_seq_multi(&ctx, 0x18, 0x40); - mipi_dsi_dcs_write_seq_multi(&ctx, 0xff, 0x10); + nt36523_switch_page(&ctx, 0x10); mipi_dsi_dcs_write_seq_multi(&ctx, 0xb9, 0x02); - mipi_dsi_dcs_write_seq_multi(&ctx, 0xff, 0x10); - mipi_dsi_dcs_write_seq_multi(&ctx, 0xfb, 0x01); + nt36523_switch_page(&ctx, 0x10); + nt36523_enable_reload_cmds(&ctx); mipi_dsi_dcs_write_seq_multi(&ctx, 0xb0, 0x01); mipi_dsi_dcs_write_seq_multi(&ctx, 0x35, 0x00); mipi_dsi_dcs_write_seq_multi(&ctx, 0x3b, 0x03, 0xae, 0x1a, 0x04, 0x04); diff --git a/drivers/gpu/drm/panel/panel-edp.c b/drivers/gpu/drm/panel/panel-edp.c index 3a574a9b46e7..767e47a2b0c1 100644 --- a/drivers/gpu/drm/panel/panel-edp.c +++ b/drivers/gpu/drm/panel/panel-edp.c @@ -954,16 +954,24 @@ static void panel_edp_shutdown(struct device *dev) * drm_atomic_helper_shutdown() at shutdown time and that should * cause the panel to be disabled / unprepared if needed. For now, * however, we'll keep these calls due to the sheer number of - * different DRM modeset drivers used with panel-edp. The fact that - * we're calling these and _also_ the drm_atomic_helper_shutdown() - * will try to disable/unprepare means that we can get a warning about - * trying to disable/unprepare an already disabled/unprepared panel, - * but that's something we'll have to live with until we've confirmed - * that all DRM modeset drivers are properly calling - * drm_atomic_helper_shutdown(). + * different DRM modeset drivers used with panel-edp. Once we've + * confirmed that all DRM modeset drivers using this panel properly + * call drm_atomic_helper_shutdown() we can simply delete the two + * calls below. + * + * TO BE EXPLICIT: THE CALLS BELOW SHOULDN'T BE COPIED TO ANY NEW + * PANEL DRIVERS. + * + * FIXME: If we're still haven't figured out if all DRM modeset + * drivers properly call drm_atomic_helper_shutdown() but we _have_ + * managed to make sure that DRM modeset drivers get their shutdown() + * callback before the panel's shutdown() callback (perhaps using + * device link), we could add a WARN_ON here to help move forward. */ - drm_panel_disable(&panel->base); - drm_panel_unprepare(&panel->base); + if (panel->base.enabled) + drm_panel_disable(&panel->base); + if (panel->base.prepared) + drm_panel_unprepare(&panel->base); } static void panel_edp_remove(struct device *dev) @@ -1845,7 +1853,10 @@ static const struct edp_panel_entry edp_panels[] = { EDP_PANEL_ENTRY('A', 'U', 'O', 0x635c, &delay_200_500_e50, "B116XAN06.3"), EDP_PANEL_ENTRY('A', 'U', 'O', 0x639c, &delay_200_500_e50, "B140HAK02.7"), EDP_PANEL_ENTRY('A', 'U', 'O', 0x723c, &delay_200_500_e50, "B140XTN07.2"), + EDP_PANEL_ENTRY('A', 'U', 'O', 0x73aa, &delay_200_500_e50, "B116XTN02.3"), EDP_PANEL_ENTRY('A', 'U', 'O', 0x8594, &delay_200_500_e50, "B133UAN01.0"), + EDP_PANEL_ENTRY('A', 'U', 'O', 0xa199, &delay_200_500_e50, "B116XAN06.1"), + EDP_PANEL_ENTRY('A', 'U', 'O', 0xc4b4, &delay_200_500_e50, "B116XAT04.1"), EDP_PANEL_ENTRY('A', 'U', 'O', 0xd497, &delay_200_500_e50, "B120XAN01.0"), EDP_PANEL_ENTRY('A', 'U', 'O', 0xf390, &delay_200_500_e50, "B140XTN07.7"), @@ -1891,15 +1902,19 @@ static const struct edp_panel_entry edp_panels[] = { EDP_PANEL_ENTRY('B', 'O', 'E', 0x09ad, &delay_200_500_e80, "NV116WHM-N47"), EDP_PANEL_ENTRY('B', 'O', 'E', 0x09ae, &delay_200_500_e200, "NT140FHM-N45"), EDP_PANEL_ENTRY('B', 'O', 'E', 0x09dd, &delay_200_500_e50, "NT116WHM-N21"), + EDP_PANEL_ENTRY('B', 'O', 'E', 0x0a1b, &delay_200_500_e50, "NV133WUM-N63"), EDP_PANEL_ENTRY('B', 'O', 'E', 0x0a36, &delay_200_500_e200, "Unknown"), EDP_PANEL_ENTRY('B', 'O', 'E', 0x0a3e, &delay_200_500_e80, "NV116WHM-N49"), EDP_PANEL_ENTRY('B', 'O', 'E', 0x0a5d, &delay_200_500_e50, "NV116WHM-N45"), EDP_PANEL_ENTRY('B', 'O', 'E', 0x0ac5, &delay_200_500_e50, "NV116WHM-N4C"), + EDP_PANEL_ENTRY('B', 'O', 'E', 0x0ae8, &delay_200_500_e50_p2e80, "NV140WUM-N41"), EDP_PANEL_ENTRY('B', 'O', 'E', 0x0b34, &delay_200_500_e80, "NV122WUM-N41"), EDP_PANEL_ENTRY('B', 'O', 'E', 0x0b43, &delay_200_500_e200, "NV140FHM-T09"), EDP_PANEL_ENTRY('B', 'O', 'E', 0x0b56, &delay_200_500_e80, "NT140FHM-N47"), + EDP_PANEL_ENTRY('B', 'O', 'E', 0x0b66, &delay_200_500_e80, "NE140WUM-N6G"), EDP_PANEL_ENTRY('B', 'O', 'E', 0x0c20, &delay_200_500_e80, "NT140FHM-N47"), EDP_PANEL_ENTRY('B', 'O', 'E', 0x0cb6, &delay_200_500_e200, "NT116WHM-N44"), + EDP_PANEL_ENTRY('B', 'O', 'E', 0x0cfa, &delay_200_500_e50, "NV116WHM-A4D"), EDP_PANEL_ENTRY('C', 'M', 'N', 0x1130, &delay_200_500_e50, "N116BGE-EB2"), EDP_PANEL_ENTRY('C', 'M', 'N', 0x1132, &delay_200_500_e80_d50, "N116BGE-EA2"), @@ -1915,8 +1930,10 @@ static const struct edp_panel_entry edp_panels[] = { EDP_PANEL_ENTRY('C', 'M', 'N', 0x1156, &delay_200_500_e80_d50, "Unknown"), EDP_PANEL_ENTRY('C', 'M', 'N', 0x1157, &delay_200_500_e80_d50, "N116BGE-EA2"), EDP_PANEL_ENTRY('C', 'M', 'N', 0x115b, &delay_200_500_e80_d50, "N116BCN-EB1"), + EDP_PANEL_ENTRY('C', 'M', 'N', 0x115d, &delay_200_500_e80_d50, "N116BCA-EA2"), EDP_PANEL_ENTRY('C', 'M', 'N', 0x115e, &delay_200_500_e80_d50, "N116BCA-EA1"), EDP_PANEL_ENTRY('C', 'M', 'N', 0x1160, &delay_200_500_e80_d50, "N116BCJ-EAK"), + EDP_PANEL_ENTRY('C', 'M', 'N', 0x1161, &delay_200_500_e80, "N116BCP-EA2"), EDP_PANEL_ENTRY('C', 'M', 'N', 0x1247, &delay_200_500_e80_d50, "N120ACA-EA1"), EDP_PANEL_ENTRY('C', 'M', 'N', 0x142b, &delay_200_500_e80_d50, "N140HCA-EAC"), EDP_PANEL_ENTRY('C', 'M', 'N', 0x142e, &delay_200_500_e80_d50, "N140BGA-EA4"), @@ -1929,9 +1946,10 @@ static const struct edp_panel_entry edp_panels[] = { EDP_PANEL_ENTRY('C', 'S', 'O', 0x1200, &delay_200_500_e50_p2e200, "MNC207QS1-1"), EDP_PANEL_ENTRY('C', 'S', 'W', 0x1100, &delay_200_500_e80_d50, "MNB601LS1-1"), + EDP_PANEL_ENTRY('C', 'S', 'W', 0x1104, &delay_200_500_e50, "MNB601LS1-4"), EDP_PANEL_ENTRY('H', 'K', 'C', 0x2d51, &delay_200_500_e200, "Unknown"), - EDP_PANEL_ENTRY('H', 'K', 'C', 0x2d5b, &delay_200_500_e200, "Unknown"), + EDP_PANEL_ENTRY('H', 'K', 'C', 0x2d5b, &delay_200_500_e200, "MB116AN01"), EDP_PANEL_ENTRY('H', 'K', 'C', 0x2d5c, &delay_200_500_e200, "MB116AN01-2"), EDP_PANEL_ENTRY('I', 'V', 'O', 0x048e, &delay_200_500_e200_d10, "M116NWR6 R5"), @@ -1960,8 +1978,6 @@ static const struct edp_panel_entry edp_panels[] = { EDP_PANEL_ENTRY('L', 'G', 'D', 0x05af, &delay_200_500_e200_d200, "Unknown"), EDP_PANEL_ENTRY('L', 'G', 'D', 0x05f1, &delay_200_500_e200_d200, "Unknown"), - EDP_PANEL_ENTRY('S', 'D', 'C', 0x416d, &delay_100_500_e200, "ATNA45AF01"), - EDP_PANEL_ENTRY('S', 'H', 'P', 0x1511, &delay_200_500_e50, "LQ140M1JW48"), EDP_PANEL_ENTRY('S', 'H', 'P', 0x1523, &delay_80_500_e50, "LQ140M1JW46"), EDP_PANEL_ENTRY('S', 'H', 'P', 0x153a, &delay_200_500_e50, "LQ140T1JH01"), diff --git a/drivers/gpu/drm/panel/panel-himax-hx8394.c b/drivers/gpu/drm/panel/panel-himax-hx8394.c index cb9f46e853de..92b03a2f65a3 100644 --- a/drivers/gpu/drm/panel/panel-himax-hx8394.c +++ b/drivers/gpu/drm/panel/panel-himax-hx8394.c @@ -339,6 +339,156 @@ static const struct hx8394_panel_desc powkiddy_x55_desc = { .init_sequence = powkiddy_x55_init_sequence, }; +static int mchp_ac40t08a_init_sequence(struct hx8394 *ctx) +{ + struct mipi_dsi_device *dsi = to_mipi_dsi_device(ctx->dev); + + /* DCS commands do not seem to be sent correclty without this delay */ + msleep(20); + + /* 5.19.8 SETEXTC: Set extension command (B9h) */ + mipi_dsi_dcs_write_seq(dsi, HX8394_CMD_SETEXTC, + 0xff, 0x83, 0x94); + + /* 5.19.9 SETMIPI: Set MIPI control (BAh) */ + mipi_dsi_dcs_write_seq(dsi, HX8394_CMD_SETMIPI, + 0x63, 0x03, 0x68, 0x6b, 0xb2, 0xc0); + + /* 5.19.2 SETPOWER: Set power (B1h) */ + mipi_dsi_dcs_write_seq(dsi, HX8394_CMD_SETPOWER, + 0x48, 0x12, 0x72, 0x09, 0x32, 0x54, + 0x71, 0x71, 0x57, 0x47); + + /* 5.19.3 SETDISP: Set display related register (B2h) */ + mipi_dsi_dcs_write_seq(dsi, HX8394_CMD_SETDISP, + 0x00, 0x80, 0x64, 0x0c, 0x0d, 0x2f); + + /* 5.19.4 SETCYC: Set display waveform cycles (B4h) */ + mipi_dsi_dcs_write_seq(dsi, HX8394_CMD_SETCYC, + 0x73, 0x74, 0x73, 0x74, 0x73, 0x74, + 0x01, 0x0c, 0x86, 0x75, 0x00, 0x3f, + 0x73, 0x74, 0x73, 0x74, 0x73, 0x74, + 0x01, 0x0c, 0x86); + + /* 5.19.5 SETVCOM: Set VCOM voltage (B6h) */ + mipi_dsi_dcs_write_seq(dsi, HX8394_CMD_SETVCOM, + 0x6e, 0x6e); + + /* 5.19.19 SETGIP0: Set GIP Option0 (D3h) */ + mipi_dsi_dcs_write_seq(dsi, HX8394_CMD_SETGIP0, + 0x00, 0x00, 0x07, 0x07, 0x40, 0x07, + 0x0c, 0x00, 0x08, 0x10, 0x08, 0x00, + 0x08, 0x54, 0x15, 0x0a, 0x05, 0x0a, + 0x02, 0x15, 0x06, 0x05, 0x06, 0x47, + 0x44, 0x0a, 0x0a, 0x4b, 0x10, 0x07, + 0x07, 0x0c, 0x40); + + /* 5.19.20 Set GIP Option1 (D5h) */ + mipi_dsi_dcs_write_seq(dsi, HX8394_CMD_SETGIP1, + 0x1c, 0x1c, 0x1d, 0x1d, 0x00, 0x01, + 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, + 0x08, 0x09, 0x0a, 0x0b, 0x24, 0x25, + 0x18, 0x18, 0x26, 0x27, 0x18, 0x18, + 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, + 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, + 0x18, 0x18, 0x20, 0x21, 0x18, 0x18, + 0x18, 0x18); + + /* 5.19.21 Set GIP Option2 (D6h) */ + mipi_dsi_dcs_write_seq(dsi, HX8394_CMD_SETGIP2, + 0x1c, 0x1c, 0x1d, 0x1d, 0x07, 0x06, + 0x05, 0x04, 0x03, 0x02, 0x01, 0x00, + 0x0b, 0x0a, 0x09, 0x08, 0x21, 0x20, + 0x18, 0x18, 0x27, 0x26, 0x18, 0x18, + 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, + 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, + 0x18, 0x18, 0x25, 0x24, 0x18, 0x18, + 0x18, 0x18); + + /* 5.19.25 SETGAMMA: Set gamma curve related setting (E0h) */ + mipi_dsi_dcs_write_seq(dsi, HX8394_CMD_SETGAMMA, + 0x00, 0x0a, 0x15, 0x1b, 0x1e, 0x21, + 0x24, 0x22, 0x47, 0x56, 0x65, 0x66, + 0x6e, 0x82, 0x88, 0x8b, 0x9a, 0x9d, + 0x98, 0xa8, 0xb9, 0x5d, 0x5c, 0x61, + 0x66, 0x6a, 0x6f, 0x7f, 0x7f, 0x00, + 0x0a, 0x15, 0x1b, 0x1e, 0x21, 0x24, + 0x22, 0x47, 0x56, 0x65, 0x65, 0x6e, + 0x81, 0x87, 0x8b, 0x98, 0x9d, 0x99, + 0xa8, 0xba, 0x5d, 0x5d, 0x62, 0x67, + 0x6b, 0x72, 0x7f, 0x7f); + + /* Unknown command, not listed in the HX8394-F datasheet (C0H) */ + mipi_dsi_dcs_write_seq(dsi, HX8394_CMD_UNKNOWN1, + 0x1f, 0x73); + + /* Set CABC control (C9h)*/ + mipi_dsi_dcs_write_seq(dsi, HX8394_CMD_SETCABC, + 0x76, 0x00, 0x30); + + /* 5.19.17 SETPANEL (CCh) */ + mipi_dsi_dcs_write_seq(dsi, HX8394_CMD_SETPANEL, + 0x0b); + + /* Unknown command, not listed in the HX8394-F datasheet (D4h) */ + mipi_dsi_dcs_write_seq(dsi, HX8394_CMD_UNKNOWN3, + 0x02); + + /* 5.19.11 Set register bank (BDh) */ + mipi_dsi_dcs_write_seq(dsi, HX8394_CMD_SETREGBANK, + 0x02); + + /* 5.19.11 Set register bank (D8h) */ + mipi_dsi_dcs_write_seq(dsi, HX8394_CMD_UNKNOWN4, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff); + + /* 5.19.11 Set register bank (BDh) */ + mipi_dsi_dcs_write_seq(dsi, HX8394_CMD_SETREGBANK, + 0x00); + + /* 5.19.11 Set register bank (BDh) */ + mipi_dsi_dcs_write_seq(dsi, HX8394_CMD_SETREGBANK, + 0x01); + + /* 5.19.2 SETPOWER: Set power (B1h) */ + mipi_dsi_dcs_write_seq(dsi, HX8394_CMD_SETPOWER, + 0x00); + + /* 5.19.11 Set register bank (BDh) */ + mipi_dsi_dcs_write_seq(dsi, HX8394_CMD_SETREGBANK, + 0x00); + + /* Unknown command, not listed in the HX8394-F datasheet (C6h) */ + mipi_dsi_dcs_write_seq(dsi, HX8394_CMD_UNKNOWN2, + 0xed); + + return 0; +} + +static const struct drm_display_mode mchp_ac40t08a_mode = { + .hdisplay = 720, + .hsync_start = 720 + 12, + .hsync_end = 720 + 12 + 24, + .htotal = 720 + 12 + 12 + 24, + .vdisplay = 1280, + .vsync_start = 1280 + 13, + .vsync_end = 1280 + 14, + .vtotal = 1280 + 14 + 13, + .clock = 60226, + .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, + .width_mm = 76, + .height_mm = 132, +}; + +static const struct hx8394_panel_desc mchp_ac40t08a_desc = { + .mode = &mchp_ac40t08a_mode, + .lanes = 4, + .mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST, + .format = MIPI_DSI_FMT_RGB888, + .init_sequence = mchp_ac40t08a_init_sequence, +}; + static int hx8394_enable(struct drm_panel *panel) { struct hx8394 *ctx = panel_to_hx8394(panel); @@ -486,7 +636,7 @@ static int hx8394_probe(struct mipi_dsi_device *dsi) if (!ctx) return -ENOMEM; - ctx->reset_gpio = devm_gpiod_get(dev, "reset", GPIOD_OUT_HIGH); + ctx->reset_gpio = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_HIGH); if (IS_ERR(ctx->reset_gpio)) return dev_err_probe(dev, PTR_ERR(ctx->reset_gpio), "Failed to get reset gpio\n"); @@ -555,6 +705,7 @@ static void hx8394_remove(struct mipi_dsi_device *dsi) static const struct of_device_id hx8394_of_match[] = { { .compatible = "hannstar,hsd060bhw4", .data = &hsd060bhw4_desc }, { .compatible = "powkiddy,x55-panel", .data = &powkiddy_x55_desc }, + { .compatible = "microchip,ac40t08a-mipi-panel", .data = &mchp_ac40t08a_desc }, { /* sentinel */ } }; MODULE_DEVICE_TABLE(of, hx8394_of_match); diff --git a/drivers/gpu/drm/panel/panel-ilitek-ili9341.c b/drivers/gpu/drm/panel/panel-ilitek-ili9341.c index 775d5d5e828c..1fbc5d433d75 100644 --- a/drivers/gpu/drm/panel/panel-ilitek-ili9341.c +++ b/drivers/gpu/drm/panel/panel-ilitek-ili9341.c @@ -121,19 +121,19 @@ struct ili9341_config { const struct drm_display_mode mode; /* ca: TODO: need comments for this register */ u8 ca[ILI9341_CA_LEN]; - /* power_b: TODO: need comments for this register */ + /* power_b: Power control B (CFh) */ u8 power_b[ILI9341_POWER_B_LEN]; - /* power_seq: TODO: need comments for this register */ + /* power_seq: Power on sequence control (EDh) */ u8 power_seq[ILI9341_POWER_SEQ_LEN]; - /* dtca: TODO: need comments for this register */ + /* dtca: Driver timing control A (E8h) */ u8 dtca[ILI9341_DTCA_LEN]; - /* dtcb: TODO: need comments for this register */ + /* dtcb: Driver timing control B (EAh) */ u8 dtcb[ILI9341_DTCB_LEN]; - /* power_a: TODO: need comments for this register */ + /* power_a: Power control A (CBh) */ u8 power_a[ILI9341_POWER_A_LEN]; /* frc: Frame Rate Control (In Normal Mode/Full Colors) (B1h) */ u8 frc[ILI9341_FRC_LEN]; - /* prc: TODO: need comments for this register */ + /* prc: Pump ratio control (F7h) */ u8 prc; /* dfc_1: B6h DISCTRL (Display Function Control) */ u8 dfc_1[ILI9341_DFC_1_LEN]; @@ -147,7 +147,7 @@ struct ili9341_config { u8 vcom_2; /* address_mode: Memory Access Control (36h) */ u8 address_mode; - /* g3amma_en: TODO: need comments for this register */ + /* g3amma_en: Enable 3G (F2h) */ u8 g3amma_en; /* rgb_interface: RGB Interface Signal Control (B0h) */ u8 rgb_interface; diff --git a/drivers/gpu/drm/panel/panel-ilitek-ili9806e.c b/drivers/gpu/drm/panel/panel-ilitek-ili9806e.c index e4a44cd26c4d..a3c79ad99d0b 100644 --- a/drivers/gpu/drm/panel/panel-ilitek-ili9806e.c +++ b/drivers/gpu/drm/panel/panel-ilitek-ili9806e.c @@ -380,7 +380,172 @@ static const struct panel_desc com35h3p70ulc_desc = { .lanes = 2, }; +static void dmt028vghmcmi_1d_init(struct mipi_dsi_multi_context *ctx) +{ + mipi_dsi_dcs_write_seq_multi(ctx, 0xff, 0xff, 0x98, 0x06, 0x04, 0x01); + mipi_dsi_dcs_write_seq_multi(ctx, 0x08, 0x10); + mipi_dsi_dcs_write_seq_multi(ctx, 0x21, 0x01); + mipi_dsi_dcs_write_seq_multi(ctx, 0x30, 0x03); + mipi_dsi_dcs_write_seq_multi(ctx, 0x31, 0x00); + mipi_dsi_dcs_write_seq_multi(ctx, 0x60, 0x06); + mipi_dsi_dcs_write_seq_multi(ctx, 0x61, 0x00); + mipi_dsi_dcs_write_seq_multi(ctx, 0x62, 0x07); + mipi_dsi_dcs_write_seq_multi(ctx, 0x63, 0x00); + mipi_dsi_dcs_write_seq_multi(ctx, 0x40, 0x16); + mipi_dsi_dcs_write_seq_multi(ctx, 0x41, 0x44); + mipi_dsi_dcs_write_seq_multi(ctx, 0x42, 0x00); + mipi_dsi_dcs_write_seq_multi(ctx, 0x43, 0x83); + mipi_dsi_dcs_write_seq_multi(ctx, 0x44, 0x89); + mipi_dsi_dcs_write_seq_multi(ctx, 0x45, 0x8a); + mipi_dsi_dcs_write_seq_multi(ctx, 0x46, 0x44); + mipi_dsi_dcs_write_seq_multi(ctx, 0x47, 0x44); + mipi_dsi_dcs_write_seq_multi(ctx, 0x50, 0x78); + mipi_dsi_dcs_write_seq_multi(ctx, 0x51, 0x78); + mipi_dsi_dcs_write_seq_multi(ctx, 0x52, 0x00); + mipi_dsi_dcs_write_seq_multi(ctx, 0x53, 0x6c); + mipi_dsi_dcs_write_seq_multi(ctx, 0x54, 0x00); + mipi_dsi_dcs_write_seq_multi(ctx, 0x55, 0x6c); + mipi_dsi_dcs_write_seq_multi(ctx, 0x56, 0x00); + /* Gamma settings */ + mipi_dsi_dcs_write_seq_multi(ctx, 0xa0, 0x00); + mipi_dsi_dcs_write_seq_multi(ctx, 0xa1, 0x09); + mipi_dsi_dcs_write_seq_multi(ctx, 0xa2, 0x14); + mipi_dsi_dcs_write_seq_multi(ctx, 0xa3, 0x09); + mipi_dsi_dcs_write_seq_multi(ctx, 0xa4, 0x05); + mipi_dsi_dcs_write_seq_multi(ctx, 0xa5, 0x0a); + mipi_dsi_dcs_write_seq_multi(ctx, 0xa6, 0x07); + mipi_dsi_dcs_write_seq_multi(ctx, 0xa7, 0x07); + mipi_dsi_dcs_write_seq_multi(ctx, 0xa8, 0x08); + mipi_dsi_dcs_write_seq_multi(ctx, 0xa9, 0x0b); + mipi_dsi_dcs_write_seq_multi(ctx, 0xaa, 0x0c); + mipi_dsi_dcs_write_seq_multi(ctx, 0xab, 0x05); + mipi_dsi_dcs_write_seq_multi(ctx, 0xac, 0x0a); + mipi_dsi_dcs_write_seq_multi(ctx, 0xad, 0x19); + mipi_dsi_dcs_write_seq_multi(ctx, 0xae, 0x0b); + mipi_dsi_dcs_write_seq_multi(ctx, 0xaf, 0x00); + + mipi_dsi_dcs_write_seq_multi(ctx, 0xc0, 0x00); + mipi_dsi_dcs_write_seq_multi(ctx, 0xc1, 0x0c); + mipi_dsi_dcs_write_seq_multi(ctx, 0xc2, 0x14); + mipi_dsi_dcs_write_seq_multi(ctx, 0xc3, 0x11); + mipi_dsi_dcs_write_seq_multi(ctx, 0xc4, 0x05); + mipi_dsi_dcs_write_seq_multi(ctx, 0xc5, 0x0c); + mipi_dsi_dcs_write_seq_multi(ctx, 0xc6, 0x08); + mipi_dsi_dcs_write_seq_multi(ctx, 0xc7, 0x03); + mipi_dsi_dcs_write_seq_multi(ctx, 0xc8, 0x06); + mipi_dsi_dcs_write_seq_multi(ctx, 0xc9, 0x0a); + mipi_dsi_dcs_write_seq_multi(ctx, 0xca, 0x10); + mipi_dsi_dcs_write_seq_multi(ctx, 0xcb, 0x05); + mipi_dsi_dcs_write_seq_multi(ctx, 0xcc, 0x0d); + mipi_dsi_dcs_write_seq_multi(ctx, 0xcd, 0x15); + mipi_dsi_dcs_write_seq_multi(ctx, 0xce, 0x13); + mipi_dsi_dcs_write_seq_multi(ctx, 0xcf, 0x00); + + mipi_dsi_dcs_write_seq_multi(ctx, 0xff, 0xff, 0x98, 0x06, 0x04, 0x07); + mipi_dsi_dcs_write_seq_multi(ctx, 0x17, 0x22); + mipi_dsi_dcs_write_seq_multi(ctx, 0x18, 0x1d); + mipi_dsi_dcs_write_seq_multi(ctx, 0x02, 0x77); + mipi_dsi_dcs_write_seq_multi(ctx, 0xe1, 0x79); + mipi_dsi_dcs_write_seq_multi(ctx, 0x06, 0x13); + + mipi_dsi_dcs_write_seq_multi(ctx, 0xff, 0xff, 0x98, 0x06, 0x04, 0x06); + /* GIP 0 */ + mipi_dsi_dcs_write_seq_multi(ctx, 0x00, 0x21); + mipi_dsi_dcs_write_seq_multi(ctx, 0x01, 0x0a); + mipi_dsi_dcs_write_seq_multi(ctx, 0x02, 0x00); + mipi_dsi_dcs_write_seq_multi(ctx, 0x03, 0x05); + mipi_dsi_dcs_write_seq_multi(ctx, 0x04, 0x01); + mipi_dsi_dcs_write_seq_multi(ctx, 0x05, 0x01); + mipi_dsi_dcs_write_seq_multi(ctx, 0x06, 0x98); + mipi_dsi_dcs_write_seq_multi(ctx, 0x07, 0x06); + mipi_dsi_dcs_write_seq_multi(ctx, 0x08, 0x01); + mipi_dsi_dcs_write_seq_multi(ctx, 0x09, 0x00); + mipi_dsi_dcs_write_seq_multi(ctx, 0x0a, 0x00); + mipi_dsi_dcs_write_seq_multi(ctx, 0x0b, 0x00); + mipi_dsi_dcs_write_seq_multi(ctx, 0x0c, 0x01); + mipi_dsi_dcs_write_seq_multi(ctx, 0x0d, 0x01); + mipi_dsi_dcs_write_seq_multi(ctx, 0x0e, 0x00); + mipi_dsi_dcs_write_seq_multi(ctx, 0x0f, 0x00); + mipi_dsi_dcs_write_seq_multi(ctx, 0x10, 0xf7); + mipi_dsi_dcs_write_seq_multi(ctx, 0x11, 0xf0); + mipi_dsi_dcs_write_seq_multi(ctx, 0x12, 0x00); + mipi_dsi_dcs_write_seq_multi(ctx, 0x13, 0x00); + mipi_dsi_dcs_write_seq_multi(ctx, 0x14, 0x00); + mipi_dsi_dcs_write_seq_multi(ctx, 0x15, 0xc0); + mipi_dsi_dcs_write_seq_multi(ctx, 0x16, 0x08); + mipi_dsi_dcs_write_seq_multi(ctx, 0x17, 0x00); + mipi_dsi_dcs_write_seq_multi(ctx, 0x18, 0x00); + mipi_dsi_dcs_write_seq_multi(ctx, 0x19, 0x00); + mipi_dsi_dcs_write_seq_multi(ctx, 0x1a, 0x00); + mipi_dsi_dcs_write_seq_multi(ctx, 0x1b, 0x00); + mipi_dsi_dcs_write_seq_multi(ctx, 0x1c, 0x00); + mipi_dsi_dcs_write_seq_multi(ctx, 0x1d, 0x00); + /* GIP 1 */ + mipi_dsi_dcs_write_seq_multi(ctx, 0x20, 0x01); + mipi_dsi_dcs_write_seq_multi(ctx, 0x21, 0x23); + mipi_dsi_dcs_write_seq_multi(ctx, 0x22, 0x44); + mipi_dsi_dcs_write_seq_multi(ctx, 0x23, 0x67); + mipi_dsi_dcs_write_seq_multi(ctx, 0x24, 0x01); + mipi_dsi_dcs_write_seq_multi(ctx, 0x25, 0x23); + mipi_dsi_dcs_write_seq_multi(ctx, 0x26, 0x45); + mipi_dsi_dcs_write_seq_multi(ctx, 0x27, 0x67); + /* GIP 2 */ + mipi_dsi_dcs_write_seq_multi(ctx, 0x30, 0x01); + mipi_dsi_dcs_write_seq_multi(ctx, 0x31, 0x22); + mipi_dsi_dcs_write_seq_multi(ctx, 0x32, 0x22); + mipi_dsi_dcs_write_seq_multi(ctx, 0x33, 0xbc); + mipi_dsi_dcs_write_seq_multi(ctx, 0x34, 0xad); + mipi_dsi_dcs_write_seq_multi(ctx, 0x35, 0xda); + mipi_dsi_dcs_write_seq_multi(ctx, 0x36, 0xcb); + mipi_dsi_dcs_write_seq_multi(ctx, 0x37, 0x22); + mipi_dsi_dcs_write_seq_multi(ctx, 0x38, 0x55); + mipi_dsi_dcs_write_seq_multi(ctx, 0x39, 0x76); + mipi_dsi_dcs_write_seq_multi(ctx, 0x3a, 0x67); + mipi_dsi_dcs_write_seq_multi(ctx, 0x3b, 0x88); + mipi_dsi_dcs_write_seq_multi(ctx, 0x3c, 0x22); + mipi_dsi_dcs_write_seq_multi(ctx, 0x3d, 0x11); + mipi_dsi_dcs_write_seq_multi(ctx, 0x3e, 0x00); + mipi_dsi_dcs_write_seq_multi(ctx, 0x3f, 0x22); + mipi_dsi_dcs_write_seq_multi(ctx, 0x40, 0x22); + + mipi_dsi_dcs_write_seq_multi(ctx, 0x52, 0x10); + mipi_dsi_dcs_write_seq_multi(ctx, 0x53, 0x10); + mipi_dsi_dcs_write_seq_multi(ctx, 0x54, 0x13); + + mipi_dsi_dcs_write_seq_multi(ctx, 0xff, 0xff, 0x98, 0x06, 0x04, 0x00); +}; + +static const struct drm_display_mode dmt028vghmcmi_1d_default_mode = { + .clock = 22000, + + .hdisplay = 480, + .hsync_start = 480 + 20, + .hsync_end = 480 + 20 + 4, + .htotal = 480 + 20 + 4 + 10, + + .vdisplay = 640, + .vsync_start = 640 + 40, + .vsync_end = 640 + 40 + 4, + .vtotal = 640 + 40 + 4 + 20, + + .width_mm = 53, + .height_mm = 79, + + .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, + .type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED, +}; + +static const struct panel_desc dmt028vghmcmi_1d_desc = { + .init_sequence = dmt028vghmcmi_1d_init, + .display_mode = &dmt028vghmcmi_1d_default_mode, + .mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | + MIPI_DSI_MODE_LPM | MIPI_DSI_CLOCK_NON_CONTINUOUS, + .format = MIPI_DSI_FMT_RGB888, + .lanes = 2, +}; + static const struct of_device_id ili9806e_of_match[] = { + { .compatible = "densitron,dmt028vghmcmi-1d", .data = &dmt028vghmcmi_1d_desc }, { .compatible = "ortustech,com35h3p70ulc", .data = &com35h3p70ulc_desc }, { } }; diff --git a/drivers/gpu/drm/panel/panel-jadard-jd9365da-h3.c b/drivers/gpu/drm/panel/panel-jadard-jd9365da-h3.c index c6b669866fed..44897e5218a6 100644 --- a/drivers/gpu/drm/panel/panel-jadard-jd9365da-h3.c +++ b/drivers/gpu/drm/panel/panel-jadard-jd9365da-h3.c @@ -31,8 +31,6 @@ struct jadard_panel_desc { bool reset_before_power_off_vcioo; unsigned int vcioo_to_lp11_delay_ms; unsigned int lp11_to_reset_delay_ms; - unsigned int exit_sleep_to_display_on_delay_ms; - unsigned int display_on_delay_ms; unsigned int backlight_off_to_display_off_delay_ms; unsigned int display_off_to_enter_sleep_delay_ms; unsigned int enter_sleep_to_reset_down_delay_ms; @@ -48,29 +46,22 @@ struct jadard { struct gpio_desc *reset; }; -static inline struct jadard *panel_to_jadard(struct drm_panel *panel) +#define JD9365DA_DCS_SWITCH_PAGE 0xe0 + +#define jd9365da_switch_page(dsi_ctx, page) \ + mipi_dsi_dcs_write_seq_multi(dsi_ctx, JD9365DA_DCS_SWITCH_PAGE, (page)) + +static void jadard_enable_standard_cmds(struct mipi_dsi_multi_context *dsi_ctx) { - return container_of(panel, struct jadard, panel); + mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0xe1, 0x93); + mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0xe2, 0x65); + mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0xe3, 0xf8); + mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0x80, 0x03); } -static int jadard_enable(struct drm_panel *panel) +static inline struct jadard *panel_to_jadard(struct drm_panel *panel) { - struct jadard *jadard = panel_to_jadard(panel); - struct mipi_dsi_multi_context dsi_ctx = { .dsi = jadard->dsi }; - - msleep(120); - - mipi_dsi_dcs_exit_sleep_mode_multi(&dsi_ctx); - - if (jadard->desc->exit_sleep_to_display_on_delay_ms) - mipi_dsi_msleep(&dsi_ctx, jadard->desc->exit_sleep_to_display_on_delay_ms); - - mipi_dsi_dcs_set_display_on_multi(&dsi_ctx); - - if (jadard->desc->display_on_delay_ms) - mipi_dsi_msleep(&dsi_ctx, jadard->desc->display_on_delay_ms); - - return dsi_ctx.accum_err; + return container_of(panel, struct jadard, panel); } static int jadard_disable(struct drm_panel *panel) @@ -189,7 +180,6 @@ static const struct drm_panel_funcs jadard_funcs = { .disable = jadard_disable, .unprepare = jadard_unprepare, .prepare = jadard_prepare, - .enable = jadard_enable, .get_modes = jadard_get_modes, .get_orientation = jadard_panel_get_orientation, }; @@ -198,12 +188,10 @@ static int radxa_display_8hd_ad002_init_cmds(struct jadard *jadard) { struct mipi_dsi_multi_context dsi_ctx = { .dsi = jadard->dsi }; - mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xE0, 0x00); - mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xE1, 0x93); - mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xE2, 0x65); - mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xE3, 0xF8); - mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x80, 0x03); - mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xE0, 0x01); + jd9365da_switch_page(&dsi_ctx, 0x00); + jadard_enable_standard_cmds(&dsi_ctx); + + jd9365da_switch_page(&dsi_ctx, 0x01); mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x00, 0x00); mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x01, 0x7E); mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x03, 0x00); @@ -276,7 +264,8 @@ static int radxa_display_8hd_ad002_init_cmds(struct jadard *jadard) mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x80, 0x37); mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x81, 0x23); mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x82, 0x10); - mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xE0, 0x02); + + jd9365da_switch_page(&dsi_ctx, 0x02); mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x00, 0x47); mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x01, 0x47); mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x02, 0x45); @@ -360,13 +349,21 @@ static int radxa_display_8hd_ad002_init_cmds(struct jadard *jadard) mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7C, 0x00); mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7D, 0x03); mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7E, 0x7B); - mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xE0, 0x04); + + jd9365da_switch_page(&dsi_ctx, 0x04); mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x00, 0x0E); mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x02, 0xB3); mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x09, 0x60); mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0E, 0x2A); mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x36, 0x59); - mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xE0, 0x00); + + jd9365da_switch_page(&dsi_ctx, 0x00); + + mipi_dsi_msleep(&dsi_ctx, 120); + + mipi_dsi_dcs_exit_sleep_mode_multi(&dsi_ctx); + + mipi_dsi_dcs_set_display_on_multi(&dsi_ctx); return dsi_ctx.accum_err; }; @@ -398,12 +395,10 @@ static int cz101b4001_init_cmds(struct jadard *jadard) { struct mipi_dsi_multi_context dsi_ctx = { .dsi = jadard->dsi }; - mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xE0, 0x00); - mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xE1, 0x93); - mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xE2, 0x65); - mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xE3, 0xF8); - mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x80, 0x03); - mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xE0, 0x01); + jd9365da_switch_page(&dsi_ctx, 0x00); + jadard_enable_standard_cmds(&dsi_ctx); + + jd9365da_switch_page(&dsi_ctx, 0x01); mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x00, 0x00); mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x01, 0x3B); mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0C, 0x74); @@ -471,7 +466,8 @@ static int cz101b4001_init_cmds(struct jadard *jadard) mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x80, 0x20); mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x81, 0x0F); mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x82, 0x00); - mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xE0, 0x02); + + jd9365da_switch_page(&dsi_ctx, 0x02); mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x00, 0x02); mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x01, 0x02); mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x02, 0x00); @@ -584,15 +580,23 @@ static int cz101b4001_init_cmds(struct jadard *jadard) mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7A, 0x17); mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7D, 0x14); mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7E, 0x82); - mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xE0, 0x04); + + jd9365da_switch_page(&dsi_ctx, 0x04); mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x00, 0x0E); mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x02, 0xB3); mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x09, 0x61); mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0E, 0x48); - mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xE0, 0x00); + + jd9365da_switch_page(&dsi_ctx, 0x00); mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xE6, 0x02); mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xE7, 0x0C); + mipi_dsi_msleep(&dsi_ctx, 120); + + mipi_dsi_dcs_exit_sleep_mode_multi(&dsi_ctx); + + mipi_dsi_dcs_set_display_on_multi(&dsi_ctx); + return dsi_ctx.accum_err; }; @@ -623,12 +627,10 @@ static int kingdisplay_kd101ne3_init_cmds(struct jadard *jadard) { struct mipi_dsi_multi_context dsi_ctx = { .dsi = jadard->dsi }; - mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xe0, 0x00); - mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xe1, 0x93); - mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xe2, 0x65); - mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xe3, 0xf8); - mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x80, 0x03); - mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xe0, 0x01); + jd9365da_switch_page(&dsi_ctx, 0x00); + jadard_enable_standard_cmds(&dsi_ctx); + + jd9365da_switch_page(&dsi_ctx, 0x01); mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0c, 0x74); mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x17, 0x00); mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x18, 0xc7); @@ -694,7 +696,8 @@ static int kingdisplay_kd101ne3_init_cmds(struct jadard *jadard) mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x80, 0x26); mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x81, 0x14); mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x82, 0x02); - mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xe0, 0x02); + + jd9365da_switch_page(&dsi_ctx, 0x02); mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x00, 0x52); mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x01, 0x5f); mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x02, 0x5f); @@ -808,12 +811,24 @@ static int kingdisplay_kd101ne3_init_cmds(struct jadard *jadard) mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x76, 0x00); mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x77, 0x05); mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x78, 0x2a); - mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xe0, 0x04); + + jd9365da_switch_page(&dsi_ctx, 0x04); mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x00, 0x0e); mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x02, 0xb3); mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x09, 0x61); mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0e, 0x48); - mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xe0, 0x00); + + jd9365da_switch_page(&dsi_ctx, 0x00); + + mipi_dsi_msleep(&dsi_ctx, 120); + + mipi_dsi_dcs_exit_sleep_mode_multi(&dsi_ctx); + + mipi_dsi_msleep(&dsi_ctx, 120); + + mipi_dsi_dcs_set_display_on_multi(&dsi_ctx); + + mipi_dsi_msleep(&dsi_ctx, 20); return dsi_ctx.accum_err; }; @@ -843,8 +858,257 @@ static const struct jadard_panel_desc kingdisplay_kd101ne3_40ti_desc = { .reset_before_power_off_vcioo = true, .vcioo_to_lp11_delay_ms = 5, .lp11_to_reset_delay_ms = 10, - .exit_sleep_to_display_on_delay_ms = 120, - .display_on_delay_ms = 20, + .backlight_off_to_display_off_delay_ms = 100, + .display_off_to_enter_sleep_delay_ms = 50, + .enter_sleep_to_reset_down_delay_ms = 100, +}; + +static int melfas_lmfbx101117480_init_cmds(struct jadard *jadard) +{ + struct mipi_dsi_multi_context dsi_ctx = { .dsi = jadard->dsi }; + + jd9365da_switch_page(&dsi_ctx, 0x00); + jadard_enable_standard_cmds(&dsi_ctx); + + jd9365da_switch_page(&dsi_ctx, 0x01); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0c, 0x74); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x17, 0x00); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x18, 0xd7); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x19, 0x01); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1a, 0x00); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1b, 0xd7); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1c, 0x01); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1f, 0x70); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x20, 0x2d); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x21, 0x2d); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x22, 0x7e); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x24, 0xfd); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x37, 0x19); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x35, 0x28); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x38, 0x05); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x39, 0x08); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3a, 0x12); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3c, 0x7e); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3d, 0xff); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3e, 0xff); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3f, 0x7f); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x40, 0x06); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x41, 0xa0); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x43, 0x1e); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x44, 0x0b); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0c, 0x74); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x55, 0x02); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x56, 0x01); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x57, 0x6a); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x58, 0x09); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x59, 0x0a); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5a, 0x2e); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5b, 0x1a); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5c, 0x15); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5d, 0x73); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5e, 0x56); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5f, 0x43); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x60, 0x38); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x61, 0x36); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x62, 0x28); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x63, 0x2f); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x64, 0x19); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x65, 0x32); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x66, 0x31); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x67, 0x31); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x68, 0x4f); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x69, 0x3e); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6a, 0x47); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6b, 0x36); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6c, 0x31); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6d, 0x24); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6e, 0x12); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6f, 0x02); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x70, 0x73); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x71, 0x56); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x72, 0x43); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x73, 0x38); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x74, 0x36); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x75, 0x28); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x76, 0x2f); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x77, 0x19); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x78, 0x32); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x79, 0x31); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7a, 0x31); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7b, 0x4f); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7c, 0x3e); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7d, 0x47); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7e, 0x36); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7f, 0x31); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x80, 0x24); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x81, 0x12); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x82, 0x02); + + jd9365da_switch_page(&dsi_ctx, 0x02); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x00, 0x52); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x01, 0x55); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x02, 0x55); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x03, 0x50); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x04, 0x77); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x05, 0x57); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x06, 0x55); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x07, 0x4e); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x08, 0x4c); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x09, 0x5f); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0a, 0x4a); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0b, 0x48); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0c, 0x55); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0d, 0x46); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0e, 0x44); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0f, 0x40); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x10, 0x55); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x11, 0x55); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x12, 0x55); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x13, 0x55); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x14, 0x55); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x15, 0x55); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x16, 0x53); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x17, 0x55); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x18, 0x55); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x19, 0x51); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1a, 0x77); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1b, 0x57); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1c, 0x55); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1d, 0x4f); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1e, 0x4d); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1f, 0x5f); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x20, 0x4b); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x21, 0x49); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x22, 0x55); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x23, 0x47); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x24, 0x45); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x25, 0x41); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x26, 0x55); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x27, 0x55); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x28, 0x55); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x29, 0x55); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x2a, 0x55); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x2b, 0x55); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x2c, 0x13); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x2d, 0x15); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x2e, 0x15); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x2f, 0x01); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x30, 0x37); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x31, 0x17); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x32, 0x15); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x33, 0x0d); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x34, 0x0f); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x35, 0x15); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x36, 0x05); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x37, 0x07); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x38, 0x15); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x39, 0x09); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3a, 0x0b); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3b, 0x11); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3c, 0x15); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3d, 0x15); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3e, 0x15); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3f, 0x15); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x40, 0x15); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x41, 0x15); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x42, 0x12); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x43, 0x15); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x44, 0x15); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x45, 0x00); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x46, 0x37); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x47, 0x17); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x48, 0x15); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x49, 0x0c); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x4a, 0x0e); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x4b, 0x15); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x4c, 0x04); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x4d, 0x06); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x4e, 0x15); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x4f, 0x08); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x50, 0x0a); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x51, 0x10); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x52, 0x15); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x53, 0x15); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x54, 0x15); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x55, 0x15); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x56, 0x15); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x57, 0x15); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x58, 0x40); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5b, 0x10); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5c, 0x06); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5d, 0x40); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5e, 0x00); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5f, 0x00); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x60, 0x40); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x61, 0x03); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x62, 0x04); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x63, 0x6c); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x64, 0x6c); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x65, 0x75); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x66, 0x08); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x67, 0xb4); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x68, 0x08); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x69, 0x6c); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6a, 0x6c); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6b, 0x0c); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6d, 0x00); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6e, 0x00); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6f, 0x88); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x75, 0xbb); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x76, 0x00); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x77, 0x05); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x78, 0x2a); + + jd9365da_switch_page(&dsi_ctx, 0x04); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x02, 0x23); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x09, 0x11); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0e, 0x48); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x36, 0x49); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x2b, 0x08); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x2e, 0x03); + + jd9365da_switch_page(&dsi_ctx, 0x00); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xe6, 0x02); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xe7, 0x06); + + mipi_dsi_msleep(&dsi_ctx, 120); + + mipi_dsi_dcs_exit_sleep_mode_multi(&dsi_ctx); + + mipi_dsi_msleep(&dsi_ctx, 120); + + mipi_dsi_dcs_set_display_on_multi(&dsi_ctx); + + mipi_dsi_msleep(&dsi_ctx, 20); + + return dsi_ctx.accum_err; +}; + +static const struct jadard_panel_desc melfas_lmfbx101117480_desc = { + .mode = { + .clock = (800 + 24 + 24 + 24) * (1280 + 30 + 4 + 8) * 60 / 1000, + + .hdisplay = 800, + .hsync_start = 800 + 24, + .hsync_end = 800 + 24 + 24, + .htotal = 800 + 24 + 24 + 24, + + .vdisplay = 1280, + .vsync_start = 1280 + 30, + .vsync_end = 1280 + 30 + 4, + .vtotal = 1280 + 30 + 4 + 8, + + .width_mm = 135, + .height_mm = 216, + .type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED, + }, + .lanes = 4, + .format = MIPI_DSI_FMT_RGB888, + .init = melfas_lmfbx101117480_init_cmds, + .lp11_before_reset = true, + .reset_before_power_off_vcioo = true, + .vcioo_to_lp11_delay_ms = 5, + .lp11_to_reset_delay_ms = 10, .backlight_off_to_display_off_delay_ms = 100, .display_off_to_enter_sleep_delay_ms = 50, .enter_sleep_to_reset_down_delay_ms = 100, @@ -927,6 +1191,10 @@ static const struct of_device_id jadard_of_match[] = { .data = &kingdisplay_kd101ne3_40ti_desc }, { + .compatible = "melfas,lmfbx101117480", + .data = &melfas_lmfbx101117480_desc + }, + { .compatible = "radxa,display-10hd-ad001", .data = &cz101b4001_desc }, diff --git a/drivers/gpu/drm/panel/panel-jdi-fhd-r63452.c b/drivers/gpu/drm/panel/panel-jdi-fhd-r63452.c index 483dc88d16d8..4eb71e85e9e9 100644 --- a/drivers/gpu/drm/panel/panel-jdi-fhd-r63452.c +++ b/drivers/gpu/drm/panel/panel-jdi-fhd-r63452.c @@ -41,142 +41,89 @@ static void jdi_fhd_r63452_reset(struct jdi_fhd_r63452 *ctx) static int jdi_fhd_r63452_on(struct jdi_fhd_r63452 *ctx) { struct mipi_dsi_device *dsi = ctx->dsi; - struct device *dev = &dsi->dev; - int ret; + struct mipi_dsi_multi_context dsi_ctx = { .dsi = dsi }; dsi->mode_flags |= MIPI_DSI_MODE_LPM; - mipi_dsi_generic_write_seq(dsi, 0xb0, 0x00); - mipi_dsi_generic_write_seq(dsi, 0xd6, 0x01); - mipi_dsi_generic_write_seq(dsi, 0xec, - 0x64, 0xdc, 0xec, 0x3b, 0x52, 0x00, 0x0b, 0x0b, - 0x13, 0x15, 0x68, 0x0b, 0xb5); - mipi_dsi_generic_write_seq(dsi, 0xb0, 0x03); - - ret = mipi_dsi_dcs_set_tear_on(dsi, MIPI_DSI_DCS_TEAR_MODE_VBLANK); - if (ret < 0) { - dev_err(dev, "Failed to set tear on: %d\n", ret); - return ret; - } - - mipi_dsi_dcs_write_seq(dsi, MIPI_DCS_SET_ADDRESS_MODE, 0x00); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xb0, 0x00); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xd6, 0x01); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xec, + 0x64, 0xdc, 0xec, 0x3b, 0x52, 0x00, 0x0b, 0x0b, + 0x13, 0x15, 0x68, 0x0b, 0xb5); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xb0, 0x03); - ret = mipi_dsi_dcs_set_pixel_format(dsi, 0x77); - if (ret < 0) { - dev_err(dev, "Failed to set pixel format: %d\n", ret); - return ret; - } - - ret = mipi_dsi_dcs_set_column_address(dsi, 0x0000, 0x0437); - if (ret < 0) { - dev_err(dev, "Failed to set column address: %d\n", ret); - return ret; - } + mipi_dsi_dcs_set_tear_on_multi(&dsi_ctx, MIPI_DSI_DCS_TEAR_MODE_VBLANK); - ret = mipi_dsi_dcs_set_page_address(dsi, 0x0000, 0x077f); - if (ret < 0) { - dev_err(dev, "Failed to set page address: %d\n", ret); - return ret; - } + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, MIPI_DCS_SET_ADDRESS_MODE, 0x00); - ret = mipi_dsi_dcs_set_tear_scanline(dsi, 0x0000); - if (ret < 0) { - dev_err(dev, "Failed to set tear scanline: %d\n", ret); - return ret; - } + mipi_dsi_dcs_set_pixel_format_multi(&dsi_ctx, 0x77); + mipi_dsi_dcs_set_column_address_multi(&dsi_ctx, 0x0000, 0x0437); + mipi_dsi_dcs_set_page_address_multi(&dsi_ctx, 0x0000, 0x077f); + mipi_dsi_dcs_set_tear_scanline_multi(&dsi_ctx, 0x0000); + mipi_dsi_dcs_set_display_brightness_multi(&dsi_ctx, 0x00ff); - ret = mipi_dsi_dcs_set_display_brightness(dsi, 0x00ff); - if (ret < 0) { - dev_err(dev, "Failed to set display brightness: %d\n", ret); - return ret; - } + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, MIPI_DCS_WRITE_CONTROL_DISPLAY, 0x24); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, MIPI_DCS_WRITE_POWER_SAVE, 0x00); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, MIPI_DCS_SET_CABC_MIN_BRIGHTNESS, 0x00); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x84, 0x00); - mipi_dsi_dcs_write_seq(dsi, MIPI_DCS_WRITE_CONTROL_DISPLAY, 0x24); - mipi_dsi_dcs_write_seq(dsi, MIPI_DCS_WRITE_POWER_SAVE, 0x00); - mipi_dsi_dcs_write_seq(dsi, MIPI_DCS_SET_CABC_MIN_BRIGHTNESS, 0x00); - mipi_dsi_dcs_write_seq(dsi, 0x84, 0x00); + mipi_dsi_dcs_set_display_on_multi(&dsi_ctx); + mipi_dsi_msleep(&dsi_ctx, 20); + mipi_dsi_dcs_exit_sleep_mode_multi(&dsi_ctx); + mipi_dsi_msleep(&dsi_ctx, 80); - ret = mipi_dsi_dcs_set_display_on(dsi); - if (ret < 0) { - dev_err(dev, "Failed to set display on: %d\n", ret); - return ret; - } - msleep(20); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xb0, 0x04); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x84, 0x00); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xc8, 0x11); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xb0, 0x03); - ret = mipi_dsi_dcs_exit_sleep_mode(dsi); - if (ret < 0) { - dev_err(dev, "Failed to exit sleep mode: %d\n", ret); - return ret; - } - msleep(80); - - mipi_dsi_generic_write_seq(dsi, 0xb0, 0x04); - mipi_dsi_dcs_write_seq(dsi, 0x84, 0x00); - mipi_dsi_generic_write_seq(dsi, 0xc8, 0x11); - mipi_dsi_generic_write_seq(dsi, 0xb0, 0x03); - - return 0; + return dsi_ctx.accum_err; } -static int jdi_fhd_r63452_off(struct jdi_fhd_r63452 *ctx) +static void jdi_fhd_r63452_off(struct jdi_fhd_r63452 *ctx) { struct mipi_dsi_device *dsi = ctx->dsi; - struct device *dev = &dsi->dev; - int ret; + struct mipi_dsi_multi_context dsi_ctx = { .dsi = dsi }; dsi->mode_flags &= ~MIPI_DSI_MODE_LPM; - mipi_dsi_generic_write_seq(dsi, 0xb0, 0x00); - mipi_dsi_generic_write_seq(dsi, 0xd6, 0x01); - mipi_dsi_generic_write_seq(dsi, 0xec, - 0x64, 0xdc, 0xec, 0x3b, 0x52, 0x00, 0x0b, 0x0b, - 0x13, 0x15, 0x68, 0x0b, 0x95); - mipi_dsi_generic_write_seq(dsi, 0xb0, 0x03); - - ret = mipi_dsi_dcs_set_display_off(dsi); - if (ret < 0) { - dev_err(dev, "Failed to set display off: %d\n", ret); - return ret; - } - usleep_range(2000, 3000); - - ret = mipi_dsi_dcs_enter_sleep_mode(dsi); - if (ret < 0) { - dev_err(dev, "Failed to enter sleep mode: %d\n", ret); - return ret; - } - msleep(120); - - return 0; + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xb0, 0x00); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xd6, 0x01); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xec, + 0x64, 0xdc, 0xec, 0x3b, 0x52, 0x00, 0x0b, 0x0b, + 0x13, 0x15, 0x68, 0x0b, 0x95); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xb0, 0x03); + + mipi_dsi_dcs_set_display_off_multi(&dsi_ctx); + mipi_dsi_usleep_range(&dsi_ctx, 2000, 3000); + mipi_dsi_dcs_enter_sleep_mode_multi(&dsi_ctx); + mipi_dsi_msleep(&dsi_ctx, 120); } static int jdi_fhd_r63452_prepare(struct drm_panel *panel) { struct jdi_fhd_r63452 *ctx = to_jdi_fhd_r63452(panel); - struct device *dev = &ctx->dsi->dev; int ret; jdi_fhd_r63452_reset(ctx); ret = jdi_fhd_r63452_on(ctx); - if (ret < 0) { - dev_err(dev, "Failed to initialize panel: %d\n", ret); + if (ret < 0) gpiod_set_value_cansleep(ctx->reset_gpio, 1); - return ret; - } - return 0; + return ret; } static int jdi_fhd_r63452_unprepare(struct drm_panel *panel) { struct jdi_fhd_r63452 *ctx = to_jdi_fhd_r63452(panel); - struct device *dev = &ctx->dsi->dev; - int ret; - ret = jdi_fhd_r63452_off(ctx); - if (ret < 0) - dev_err(dev, "Failed to un-initialize panel: %d\n", ret); + /* + * NOTE: We don't return an error here as while the panel won't have + * been cleanly turned off at least we've asserted the reset signal + * so it should be safe to power it back on again later + */ + jdi_fhd_r63452_off(ctx); gpiod_set_value_cansleep(ctx->reset_gpio, 1); diff --git a/drivers/gpu/drm/panel/panel-mantix-mlaf057we51.c b/drivers/gpu/drm/panel/panel-mantix-mlaf057we51.c index ea4a6bf6d35b..4db852ffb0f6 100644 --- a/drivers/gpu/drm/panel/panel-mantix-mlaf057we51.c +++ b/drivers/gpu/drm/panel/panel-mantix-mlaf057we51.c @@ -23,7 +23,7 @@ /* Manufacturer specific Commands send via DSI */ #define MANTIX_CMD_OTP_STOP_RELOAD_MIPI 0x41 -#define MANTIX_CMD_INT_CANCEL 0x4C +#define MANTIX_CMD_INT_CANCEL 0x4c #define MANTIX_CMD_SPI_FINISH 0x90 struct mantix { @@ -45,82 +45,57 @@ static inline struct mantix *panel_to_mantix(struct drm_panel *panel) return container_of(panel, struct mantix, panel); } -static int mantix_init_sequence(struct mantix *ctx) +static void mantix_init_sequence(struct mipi_dsi_multi_context *dsi_ctx) { - struct mipi_dsi_device *dsi = to_mipi_dsi_device(ctx->dev); - struct device *dev = ctx->dev; - /* * Init sequence was supplied by the panel vendor. */ - mipi_dsi_generic_write_seq(dsi, MANTIX_CMD_OTP_STOP_RELOAD_MIPI, 0x5A); - - mipi_dsi_generic_write_seq(dsi, MANTIX_CMD_INT_CANCEL, 0x03); - mipi_dsi_generic_write_seq(dsi, MANTIX_CMD_OTP_STOP_RELOAD_MIPI, 0x5A, 0x03); - mipi_dsi_generic_write_seq(dsi, 0x80, 0xA9, 0x00); + mipi_dsi_generic_write_seq_multi(dsi_ctx, MANTIX_CMD_OTP_STOP_RELOAD_MIPI, 0x5a); - mipi_dsi_generic_write_seq(dsi, MANTIX_CMD_OTP_STOP_RELOAD_MIPI, 0x5A, 0x09); - mipi_dsi_generic_write_seq(dsi, 0x80, 0x64, 0x00, 0x64, 0x00, 0x00); - msleep(20); + mipi_dsi_generic_write_seq_multi(dsi_ctx, MANTIX_CMD_INT_CANCEL, 0x03); + mipi_dsi_generic_write_seq_multi(dsi_ctx, MANTIX_CMD_OTP_STOP_RELOAD_MIPI, 0x5a, 0x03); + mipi_dsi_generic_write_seq_multi(dsi_ctx, 0x80, 0xa9, 0x00); - mipi_dsi_generic_write_seq(dsi, MANTIX_CMD_SPI_FINISH, 0xA5); - mipi_dsi_generic_write_seq(dsi, MANTIX_CMD_OTP_STOP_RELOAD_MIPI, 0x00, 0x2F); - msleep(20); + mipi_dsi_generic_write_seq_multi(dsi_ctx, MANTIX_CMD_OTP_STOP_RELOAD_MIPI, 0x5a, 0x09); + mipi_dsi_generic_write_seq_multi(dsi_ctx, 0x80, 0x64, 0x00, 0x64, 0x00, 0x00); + mipi_dsi_msleep(dsi_ctx, 20); - dev_dbg(dev, "Panel init sequence done\n"); - return 0; + mipi_dsi_generic_write_seq_multi(dsi_ctx, MANTIX_CMD_SPI_FINISH, 0xa5); + mipi_dsi_generic_write_seq_multi(dsi_ctx, MANTIX_CMD_OTP_STOP_RELOAD_MIPI, 0x00, 0x2f); + mipi_dsi_msleep(dsi_ctx, 20); } static int mantix_enable(struct drm_panel *panel) { struct mantix *ctx = panel_to_mantix(panel); - struct device *dev = ctx->dev; - struct mipi_dsi_device *dsi = to_mipi_dsi_device(dev); - int ret; + struct mipi_dsi_device *dsi = to_mipi_dsi_device(ctx->dev); + struct mipi_dsi_multi_context dsi_ctx = { .dsi = dsi }; - ret = mantix_init_sequence(ctx); - if (ret < 0) { - dev_err(ctx->dev, "Panel init sequence failed: %d\n", ret); - return ret; - } + mantix_init_sequence(&dsi_ctx); + if (!dsi_ctx.accum_err) + dev_dbg(ctx->dev, "Panel init sequence done\n"); - ret = mipi_dsi_dcs_exit_sleep_mode(dsi); - if (ret < 0) { - dev_err(dev, "Failed to exit sleep mode\n"); - return ret; - } - msleep(20); + mipi_dsi_dcs_exit_sleep_mode_multi(&dsi_ctx); + mipi_dsi_msleep(&dsi_ctx, 20); - ret = mipi_dsi_dcs_set_display_on(dsi); - if (ret) - return ret; - usleep_range(10000, 12000); + mipi_dsi_dcs_set_display_on_multi(&dsi_ctx); + mipi_dsi_usleep_range(&dsi_ctx, 10000, 12000); - ret = mipi_dsi_turn_on_peripheral(dsi); - if (ret < 0) { - dev_err(dev, "Failed to turn on peripheral\n"); - return ret; - } + mipi_dsi_turn_on_peripheral_multi(&dsi_ctx); - return 0; + return dsi_ctx.accum_err; } static int mantix_disable(struct drm_panel *panel) { struct mantix *ctx = panel_to_mantix(panel); struct mipi_dsi_device *dsi = to_mipi_dsi_device(ctx->dev); - int ret; - - ret = mipi_dsi_dcs_set_display_off(dsi); - if (ret < 0) - dev_err(ctx->dev, "Failed to turn off the display: %d\n", ret); + struct mipi_dsi_multi_context dsi_ctx = { .dsi = dsi }; - ret = mipi_dsi_dcs_enter_sleep_mode(dsi); - if (ret < 0) - dev_err(ctx->dev, "Failed to enter sleep mode: %d\n", ret); + mipi_dsi_dcs_set_display_off_multi(&dsi_ctx); + mipi_dsi_dcs_enter_sleep_mode_multi(&dsi_ctx); - - return 0; + return dsi_ctx.accum_err; } static int mantix_unprepare(struct drm_panel *panel) diff --git a/drivers/gpu/drm/panel/panel-newvision-nv3051d.c b/drivers/gpu/drm/panel/panel-newvision-nv3051d.c index 94d89ffd596b..5d115ecd5dd4 100644 --- a/drivers/gpu/drm/panel/panel-newvision-nv3051d.c +++ b/drivers/gpu/drm/panel/panel-newvision-nv3051d.c @@ -47,195 +47,196 @@ static inline struct panel_nv3051d *panel_to_panelnv3051d(struct drm_panel *pane static int panel_nv3051d_init_sequence(struct panel_nv3051d *ctx) { struct mipi_dsi_device *dsi = to_mipi_dsi_device(ctx->dev); + struct mipi_dsi_multi_context dsi_ctx = {.dsi = dsi}; /* * Init sequence was supplied by device vendor with no * documentation. */ - mipi_dsi_dcs_write_seq(dsi, 0xFF, 0x30); - mipi_dsi_dcs_write_seq(dsi, 0xFF, 0x52); - mipi_dsi_dcs_write_seq(dsi, 0xFF, 0x01); - mipi_dsi_dcs_write_seq(dsi, 0xE3, 0x00); - mipi_dsi_dcs_write_seq(dsi, 0x03, 0x40); - mipi_dsi_dcs_write_seq(dsi, 0x04, 0x00); - mipi_dsi_dcs_write_seq(dsi, 0x05, 0x03); - mipi_dsi_dcs_write_seq(dsi, 0x24, 0x12); - mipi_dsi_dcs_write_seq(dsi, 0x25, 0x1E); - mipi_dsi_dcs_write_seq(dsi, 0x26, 0x28); - mipi_dsi_dcs_write_seq(dsi, 0x27, 0x52); - mipi_dsi_dcs_write_seq(dsi, 0x28, 0x57); - mipi_dsi_dcs_write_seq(dsi, 0x29, 0x01); - mipi_dsi_dcs_write_seq(dsi, 0x2A, 0xDF); - mipi_dsi_dcs_write_seq(dsi, 0x38, 0x9C); - mipi_dsi_dcs_write_seq(dsi, 0x39, 0xA7); - mipi_dsi_dcs_write_seq(dsi, 0x3A, 0x53); - mipi_dsi_dcs_write_seq(dsi, 0x44, 0x00); - mipi_dsi_dcs_write_seq(dsi, 0x49, 0x3C); - mipi_dsi_dcs_write_seq(dsi, 0x59, 0xFE); - mipi_dsi_dcs_write_seq(dsi, 0x5C, 0x00); - mipi_dsi_dcs_write_seq(dsi, 0x91, 0x77); - mipi_dsi_dcs_write_seq(dsi, 0x92, 0x77); - mipi_dsi_dcs_write_seq(dsi, 0xA0, 0x55); - mipi_dsi_dcs_write_seq(dsi, 0xA1, 0x50); - mipi_dsi_dcs_write_seq(dsi, 0xA4, 0x9C); - mipi_dsi_dcs_write_seq(dsi, 0xA7, 0x02); - mipi_dsi_dcs_write_seq(dsi, 0xA8, 0x01); - mipi_dsi_dcs_write_seq(dsi, 0xA9, 0x01); - mipi_dsi_dcs_write_seq(dsi, 0xAA, 0xFC); - mipi_dsi_dcs_write_seq(dsi, 0xAB, 0x28); - mipi_dsi_dcs_write_seq(dsi, 0xAC, 0x06); - mipi_dsi_dcs_write_seq(dsi, 0xAD, 0x06); - mipi_dsi_dcs_write_seq(dsi, 0xAE, 0x06); - mipi_dsi_dcs_write_seq(dsi, 0xAF, 0x03); - mipi_dsi_dcs_write_seq(dsi, 0xB0, 0x08); - mipi_dsi_dcs_write_seq(dsi, 0xB1, 0x26); - mipi_dsi_dcs_write_seq(dsi, 0xB2, 0x28); - mipi_dsi_dcs_write_seq(dsi, 0xB3, 0x28); - mipi_dsi_dcs_write_seq(dsi, 0xB4, 0x33); - mipi_dsi_dcs_write_seq(dsi, 0xB5, 0x08); - mipi_dsi_dcs_write_seq(dsi, 0xB6, 0x26); - mipi_dsi_dcs_write_seq(dsi, 0xB7, 0x08); - mipi_dsi_dcs_write_seq(dsi, 0xB8, 0x26); - mipi_dsi_dcs_write_seq(dsi, 0xFF, 0x30); - mipi_dsi_dcs_write_seq(dsi, 0xFF, 0x52); - mipi_dsi_dcs_write_seq(dsi, 0xFF, 0x02); - mipi_dsi_dcs_write_seq(dsi, 0xB1, 0x0E); - mipi_dsi_dcs_write_seq(dsi, 0xD1, 0x0E); - mipi_dsi_dcs_write_seq(dsi, 0xB4, 0x29); - mipi_dsi_dcs_write_seq(dsi, 0xD4, 0x2B); - mipi_dsi_dcs_write_seq(dsi, 0xB2, 0x0C); - mipi_dsi_dcs_write_seq(dsi, 0xD2, 0x0A); - mipi_dsi_dcs_write_seq(dsi, 0xB3, 0x28); - mipi_dsi_dcs_write_seq(dsi, 0xD3, 0x28); - mipi_dsi_dcs_write_seq(dsi, 0xB6, 0x11); - mipi_dsi_dcs_write_seq(dsi, 0xD6, 0x0D); - mipi_dsi_dcs_write_seq(dsi, 0xB7, 0x32); - mipi_dsi_dcs_write_seq(dsi, 0xD7, 0x30); - mipi_dsi_dcs_write_seq(dsi, 0xC1, 0x04); - mipi_dsi_dcs_write_seq(dsi, 0xE1, 0x06); - mipi_dsi_dcs_write_seq(dsi, 0xB8, 0x0A); - mipi_dsi_dcs_write_seq(dsi, 0xD8, 0x0A); - mipi_dsi_dcs_write_seq(dsi, 0xB9, 0x01); - mipi_dsi_dcs_write_seq(dsi, 0xD9, 0x01); - mipi_dsi_dcs_write_seq(dsi, 0xBD, 0x13); - mipi_dsi_dcs_write_seq(dsi, 0xDD, 0x13); - mipi_dsi_dcs_write_seq(dsi, 0xBC, 0x11); - mipi_dsi_dcs_write_seq(dsi, 0xDC, 0x11); - mipi_dsi_dcs_write_seq(dsi, 0xBB, 0x0F); - mipi_dsi_dcs_write_seq(dsi, 0xDB, 0x0F); - mipi_dsi_dcs_write_seq(dsi, 0xBA, 0x0F); - mipi_dsi_dcs_write_seq(dsi, 0xDA, 0x0F); - mipi_dsi_dcs_write_seq(dsi, 0xBE, 0x18); - mipi_dsi_dcs_write_seq(dsi, 0xDE, 0x18); - mipi_dsi_dcs_write_seq(dsi, 0xBF, 0x0F); - mipi_dsi_dcs_write_seq(dsi, 0xDF, 0x0F); - mipi_dsi_dcs_write_seq(dsi, 0xC0, 0x17); - mipi_dsi_dcs_write_seq(dsi, 0xE0, 0x17); - mipi_dsi_dcs_write_seq(dsi, 0xB5, 0x3B); - mipi_dsi_dcs_write_seq(dsi, 0xD5, 0x3C); - mipi_dsi_dcs_write_seq(dsi, 0xB0, 0x0B); - mipi_dsi_dcs_write_seq(dsi, 0xD0, 0x0C); - mipi_dsi_dcs_write_seq(dsi, 0xFF, 0x30); - mipi_dsi_dcs_write_seq(dsi, 0xFF, 0x52); - mipi_dsi_dcs_write_seq(dsi, 0xFF, 0x03); - mipi_dsi_dcs_write_seq(dsi, 0x00, 0x2A); - mipi_dsi_dcs_write_seq(dsi, 0x01, 0x2A); - mipi_dsi_dcs_write_seq(dsi, 0x02, 0x2A); - mipi_dsi_dcs_write_seq(dsi, 0x03, 0x2A); - mipi_dsi_dcs_write_seq(dsi, 0x04, 0x61); - mipi_dsi_dcs_write_seq(dsi, 0x05, 0x80); - mipi_dsi_dcs_write_seq(dsi, 0x06, 0xC7); - mipi_dsi_dcs_write_seq(dsi, 0x07, 0x01); - mipi_dsi_dcs_write_seq(dsi, 0x08, 0x82); - mipi_dsi_dcs_write_seq(dsi, 0x09, 0x83); - mipi_dsi_dcs_write_seq(dsi, 0x30, 0x2A); - mipi_dsi_dcs_write_seq(dsi, 0x31, 0x2A); - mipi_dsi_dcs_write_seq(dsi, 0x32, 0x2A); - mipi_dsi_dcs_write_seq(dsi, 0x33, 0x2A); - mipi_dsi_dcs_write_seq(dsi, 0x34, 0x61); - mipi_dsi_dcs_write_seq(dsi, 0x35, 0xC5); - mipi_dsi_dcs_write_seq(dsi, 0x36, 0x80); - mipi_dsi_dcs_write_seq(dsi, 0x37, 0x23); - mipi_dsi_dcs_write_seq(dsi, 0x40, 0x82); - mipi_dsi_dcs_write_seq(dsi, 0x41, 0x83); - mipi_dsi_dcs_write_seq(dsi, 0x42, 0x80); - mipi_dsi_dcs_write_seq(dsi, 0x43, 0x81); - mipi_dsi_dcs_write_seq(dsi, 0x44, 0x11); - mipi_dsi_dcs_write_seq(dsi, 0x45, 0xF2); - mipi_dsi_dcs_write_seq(dsi, 0x46, 0xF1); - mipi_dsi_dcs_write_seq(dsi, 0x47, 0x11); - mipi_dsi_dcs_write_seq(dsi, 0x48, 0xF4); - mipi_dsi_dcs_write_seq(dsi, 0x49, 0xF3); - mipi_dsi_dcs_write_seq(dsi, 0x50, 0x02); - mipi_dsi_dcs_write_seq(dsi, 0x51, 0x01); - mipi_dsi_dcs_write_seq(dsi, 0x52, 0x04); - mipi_dsi_dcs_write_seq(dsi, 0x53, 0x03); - mipi_dsi_dcs_write_seq(dsi, 0x54, 0x11); - mipi_dsi_dcs_write_seq(dsi, 0x55, 0xF6); - mipi_dsi_dcs_write_seq(dsi, 0x56, 0xF5); - mipi_dsi_dcs_write_seq(dsi, 0x57, 0x11); - mipi_dsi_dcs_write_seq(dsi, 0x58, 0xF8); - mipi_dsi_dcs_write_seq(dsi, 0x59, 0xF7); - mipi_dsi_dcs_write_seq(dsi, 0x7E, 0x02); - mipi_dsi_dcs_write_seq(dsi, 0x7F, 0x80); - mipi_dsi_dcs_write_seq(dsi, 0xE0, 0x5A); - mipi_dsi_dcs_write_seq(dsi, 0xB1, 0x00); - mipi_dsi_dcs_write_seq(dsi, 0xB4, 0x0E); - mipi_dsi_dcs_write_seq(dsi, 0xB5, 0x0F); - mipi_dsi_dcs_write_seq(dsi, 0xB6, 0x04); - mipi_dsi_dcs_write_seq(dsi, 0xB7, 0x07); - mipi_dsi_dcs_write_seq(dsi, 0xB8, 0x06); - mipi_dsi_dcs_write_seq(dsi, 0xB9, 0x05); - mipi_dsi_dcs_write_seq(dsi, 0xBA, 0x0F); - mipi_dsi_dcs_write_seq(dsi, 0xC7, 0x00); - mipi_dsi_dcs_write_seq(dsi, 0xCA, 0x0E); - mipi_dsi_dcs_write_seq(dsi, 0xCB, 0x0F); - mipi_dsi_dcs_write_seq(dsi, 0xCC, 0x04); - mipi_dsi_dcs_write_seq(dsi, 0xCD, 0x07); - mipi_dsi_dcs_write_seq(dsi, 0xCE, 0x06); - mipi_dsi_dcs_write_seq(dsi, 0xCF, 0x05); - mipi_dsi_dcs_write_seq(dsi, 0xD0, 0x0F); - mipi_dsi_dcs_write_seq(dsi, 0x81, 0x0F); - mipi_dsi_dcs_write_seq(dsi, 0x84, 0x0E); - mipi_dsi_dcs_write_seq(dsi, 0x85, 0x0F); - mipi_dsi_dcs_write_seq(dsi, 0x86, 0x07); - mipi_dsi_dcs_write_seq(dsi, 0x87, 0x04); - mipi_dsi_dcs_write_seq(dsi, 0x88, 0x05); - mipi_dsi_dcs_write_seq(dsi, 0x89, 0x06); - mipi_dsi_dcs_write_seq(dsi, 0x8A, 0x00); - mipi_dsi_dcs_write_seq(dsi, 0x97, 0x0F); - mipi_dsi_dcs_write_seq(dsi, 0x9A, 0x0E); - mipi_dsi_dcs_write_seq(dsi, 0x9B, 0x0F); - mipi_dsi_dcs_write_seq(dsi, 0x9C, 0x07); - mipi_dsi_dcs_write_seq(dsi, 0x9D, 0x04); - mipi_dsi_dcs_write_seq(dsi, 0x9E, 0x05); - mipi_dsi_dcs_write_seq(dsi, 0x9F, 0x06); - mipi_dsi_dcs_write_seq(dsi, 0xA0, 0x00); - mipi_dsi_dcs_write_seq(dsi, 0xFF, 0x30); - mipi_dsi_dcs_write_seq(dsi, 0xFF, 0x52); - mipi_dsi_dcs_write_seq(dsi, 0xFF, 0x02); - mipi_dsi_dcs_write_seq(dsi, 0x01, 0x01); - mipi_dsi_dcs_write_seq(dsi, 0x02, 0xDA); - mipi_dsi_dcs_write_seq(dsi, 0x03, 0xBA); - mipi_dsi_dcs_write_seq(dsi, 0x04, 0xA8); - mipi_dsi_dcs_write_seq(dsi, 0x05, 0x9A); - mipi_dsi_dcs_write_seq(dsi, 0x06, 0x70); - mipi_dsi_dcs_write_seq(dsi, 0x07, 0xFF); - mipi_dsi_dcs_write_seq(dsi, 0x08, 0x91); - mipi_dsi_dcs_write_seq(dsi, 0x09, 0x90); - mipi_dsi_dcs_write_seq(dsi, 0x0A, 0xFF); - mipi_dsi_dcs_write_seq(dsi, 0x0B, 0x8F); - mipi_dsi_dcs_write_seq(dsi, 0x0C, 0x60); - mipi_dsi_dcs_write_seq(dsi, 0x0D, 0x58); - mipi_dsi_dcs_write_seq(dsi, 0x0E, 0x48); - mipi_dsi_dcs_write_seq(dsi, 0x0F, 0x38); - mipi_dsi_dcs_write_seq(dsi, 0x10, 0x2B); - mipi_dsi_dcs_write_seq(dsi, 0xFF, 0x30); - mipi_dsi_dcs_write_seq(dsi, 0xFF, 0x52); - mipi_dsi_dcs_write_seq(dsi, 0xFF, 0x00); - mipi_dsi_dcs_write_seq(dsi, 0x36, 0x02); - mipi_dsi_dcs_write_seq(dsi, 0x3A, 0x70); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xFF, 0x30); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xFF, 0x52); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xFF, 0x01); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xE3, 0x00); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x03, 0x40); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x04, 0x00); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x05, 0x03); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x24, 0x12); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x25, 0x1E); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x26, 0x28); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x27, 0x52); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x28, 0x57); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x29, 0x01); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x2A, 0xDF); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x38, 0x9C); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x39, 0xA7); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3A, 0x53); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x44, 0x00); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x49, 0x3C); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x59, 0xFE); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5C, 0x00); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x91, 0x77); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x92, 0x77); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xA0, 0x55); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xA1, 0x50); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xA4, 0x9C); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xA7, 0x02); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xA8, 0x01); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xA9, 0x01); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xAA, 0xFC); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xAB, 0x28); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xAC, 0x06); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xAD, 0x06); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xAE, 0x06); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xAF, 0x03); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xB0, 0x08); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xB1, 0x26); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xB2, 0x28); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xB3, 0x28); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xB4, 0x33); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xB5, 0x08); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xB6, 0x26); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xB7, 0x08); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xB8, 0x26); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xFF, 0x30); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xFF, 0x52); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xFF, 0x02); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xB1, 0x0E); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xD1, 0x0E); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xB4, 0x29); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xD4, 0x2B); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xB2, 0x0C); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xD2, 0x0A); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xB3, 0x28); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xD3, 0x28); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xB6, 0x11); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xD6, 0x0D); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xB7, 0x32); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xD7, 0x30); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xC1, 0x04); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xE1, 0x06); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xB8, 0x0A); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xD8, 0x0A); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xB9, 0x01); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xD9, 0x01); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xBD, 0x13); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xDD, 0x13); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xBC, 0x11); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xDC, 0x11); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xBB, 0x0F); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xDB, 0x0F); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xBA, 0x0F); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xDA, 0x0F); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xBE, 0x18); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xDE, 0x18); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xBF, 0x0F); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xDF, 0x0F); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xC0, 0x17); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xE0, 0x17); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xB5, 0x3B); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xD5, 0x3C); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xB0, 0x0B); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xD0, 0x0C); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xFF, 0x30); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xFF, 0x52); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xFF, 0x03); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x00, 0x2A); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x01, 0x2A); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x02, 0x2A); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x03, 0x2A); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x04, 0x61); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x05, 0x80); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x06, 0xC7); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x07, 0x01); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x08, 0x82); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x09, 0x83); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x30, 0x2A); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x31, 0x2A); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x32, 0x2A); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x33, 0x2A); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x34, 0x61); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x35, 0xC5); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x36, 0x80); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x37, 0x23); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x40, 0x82); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x41, 0x83); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x42, 0x80); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x43, 0x81); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x44, 0x11); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x45, 0xF2); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x46, 0xF1); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x47, 0x11); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x48, 0xF4); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x49, 0xF3); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x50, 0x02); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x51, 0x01); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x52, 0x04); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x53, 0x03); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x54, 0x11); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x55, 0xF6); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x56, 0xF5); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x57, 0x11); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x58, 0xF8); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x59, 0xF7); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7E, 0x02); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7F, 0x80); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xE0, 0x5A); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xB1, 0x00); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xB4, 0x0E); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xB5, 0x0F); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xB6, 0x04); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xB7, 0x07); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xB8, 0x06); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xB9, 0x05); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xBA, 0x0F); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xC7, 0x00); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xCA, 0x0E); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xCB, 0x0F); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xCC, 0x04); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xCD, 0x07); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xCE, 0x06); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xCF, 0x05); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xD0, 0x0F); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x81, 0x0F); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x84, 0x0E); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x85, 0x0F); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x86, 0x07); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x87, 0x04); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x88, 0x05); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x89, 0x06); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x8A, 0x00); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x97, 0x0F); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x9A, 0x0E); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x9B, 0x0F); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x9C, 0x07); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x9D, 0x04); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x9E, 0x05); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x9F, 0x06); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xA0, 0x00); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xFF, 0x30); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xFF, 0x52); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xFF, 0x02); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x01, 0x01); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x02, 0xDA); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x03, 0xBA); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x04, 0xA8); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x05, 0x9A); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x06, 0x70); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x07, 0xFF); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x08, 0x91); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x09, 0x90); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0A, 0xFF); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0B, 0x8F); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0C, 0x60); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0D, 0x58); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0E, 0x48); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0F, 0x38); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x10, 0x2B); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xFF, 0x30); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xFF, 0x52); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xFF, 0x00); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x36, 0x02); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3A, 0x70); dev_dbg(ctx->dev, "Panel init sequence done\n"); diff --git a/drivers/gpu/drm/panel/panel-novatek-nt35510.c b/drivers/gpu/drm/panel/panel-novatek-nt35510.c index d3bfdfc9cff6..57686340de49 100644 --- a/drivers/gpu/drm/panel/panel-novatek-nt35510.c +++ b/drivers/gpu/drm/panel/panel-novatek-nt35510.c @@ -1166,7 +1166,7 @@ static int nt35510_probe(struct mipi_dsi_device *dsi) bl->props.brightness = nt->conf->wrdisbv; else bl->props.brightness = 255; - bl->props.power = FB_BLANK_POWERDOWN; + bl->props.power = BACKLIGHT_POWER_OFF; nt->panel.backlight = bl; } diff --git a/drivers/gpu/drm/panel/panel-novatek-nt35950.c b/drivers/gpu/drm/panel/panel-novatek-nt35950.c index 028fdac293f7..b036208f9356 100644 --- a/drivers/gpu/drm/panel/panel-novatek-nt35950.c +++ b/drivers/gpu/drm/panel/panel-novatek-nt35950.c @@ -100,106 +100,87 @@ static void nt35950_reset(struct nt35950 *nt) /* * nt35950_set_cmd2_page - Select manufacturer control (CMD2) page + * @dsi_ctx: context for mipi_dsi functions * @nt: Main driver structure * @page: Page number (0-7) - * - * Return: Number of transferred bytes or negative number on error */ -static int nt35950_set_cmd2_page(struct nt35950 *nt, u8 page) +static void nt35950_set_cmd2_page(struct mipi_dsi_multi_context *dsi_ctx, + struct nt35950 *nt, u8 page) { const u8 mauc_cmd2_page[] = { MCS_CMD_MAUCCTR, 0x55, 0xaa, 0x52, 0x08, page }; - int ret; - ret = mipi_dsi_dcs_write_buffer(nt->dsi[0], mauc_cmd2_page, + mipi_dsi_dcs_write_buffer_multi(dsi_ctx, mauc_cmd2_page, ARRAY_SIZE(mauc_cmd2_page)); - if (ret < 0) - return ret; - - nt->last_page = page; - return 0; + if (!dsi_ctx->accum_err) + nt->last_page = page; } /* * nt35950_set_data_compression - Set data compression mode + * @dsi_ctx: context for mipi_dsi functions * @nt: Main driver structure * @comp_mode: Compression mode - * - * Return: Number of transferred bytes or negative number on error */ -static int nt35950_set_data_compression(struct nt35950 *nt, u8 comp_mode) +static void nt35950_set_data_compression(struct mipi_dsi_multi_context *dsi_ctx, + struct nt35950 *nt, u8 comp_mode) { u8 cmd_data_compression[] = { MCS_PARAM_DATA_COMPRESSION, comp_mode }; u8 cmd_vesa_dsc_on[] = { MCS_PARAM_VESA_DSC_ON, !!comp_mode }; u8 cmd_vesa_dsc_setting[] = { MCS_PARAM_VESA_DSC_SETTING, 0x03 }; u8 last_page = nt->last_page; - int ret; /* Set CMD2 Page 0 if we're not there yet */ - if (last_page != 0) { - ret = nt35950_set_cmd2_page(nt, 0); - if (ret < 0) - return ret; - } + if (last_page != 0) + nt35950_set_cmd2_page(dsi_ctx, nt, 0); - ret = mipi_dsi_dcs_write_buffer(nt->dsi[0], cmd_data_compression, + mipi_dsi_dcs_write_buffer_multi(dsi_ctx, cmd_data_compression, ARRAY_SIZE(cmd_data_compression)); - if (ret < 0) - return ret; - - ret = mipi_dsi_dcs_write_buffer(nt->dsi[0], cmd_vesa_dsc_on, + mipi_dsi_dcs_write_buffer_multi(dsi_ctx, cmd_vesa_dsc_on, ARRAY_SIZE(cmd_vesa_dsc_on)); - if (ret < 0) - return ret; /* Set the vesa dsc setting on Page 4 */ - ret = nt35950_set_cmd2_page(nt, 4); - if (ret < 0) - return ret; + nt35950_set_cmd2_page(dsi_ctx, nt, 4); /* Display Stream Compression setting, always 0x03 */ - ret = mipi_dsi_dcs_write_buffer(nt->dsi[0], cmd_vesa_dsc_setting, + mipi_dsi_dcs_write_buffer_multi(dsi_ctx, cmd_vesa_dsc_setting, ARRAY_SIZE(cmd_vesa_dsc_setting)); - if (ret < 0) - return ret; /* Get back to the previously set page */ - return nt35950_set_cmd2_page(nt, last_page); + nt35950_set_cmd2_page(dsi_ctx, nt, last_page); } /* * nt35950_set_scaler - Enable/disable resolution upscaling - * @nt: Main driver structure + * @dsi_ctx: context for mipi_dsi functions * @scale_up: Scale up function control - * - * Return: Number of transferred bytes or negative number on error */ -static int nt35950_set_scaler(struct nt35950 *nt, u8 scale_up) +static void nt35950_set_scaler(struct mipi_dsi_multi_context *dsi_ctx, + u8 scale_up) { u8 cmd_scaler[] = { MCS_PARAM_SCALER_FUNCTION, scale_up }; - return mipi_dsi_dcs_write_buffer(nt->dsi[0], cmd_scaler, - ARRAY_SIZE(cmd_scaler)); + mipi_dsi_dcs_write_buffer_multi(dsi_ctx, cmd_scaler, + ARRAY_SIZE(cmd_scaler)); } /* * nt35950_set_scale_mode - Resolution upscaling mode - * @nt: Main driver structure + * @dsi_ctx: context for mipi_dsi functions * @mode: Scaler mode (MCS_DATA_COMPRESSION_*) - * - * Return: Number of transferred bytes or negative number on error */ -static int nt35950_set_scale_mode(struct nt35950 *nt, u8 mode) +static void nt35950_set_scale_mode(struct mipi_dsi_multi_context *dsi_ctx, + u8 mode) { u8 cmd_scaler[] = { MCS_PARAM_SCALEUP_MODE, mode }; - return mipi_dsi_dcs_write_buffer(nt->dsi[0], cmd_scaler, - ARRAY_SIZE(cmd_scaler)); + mipi_dsi_dcs_write_buffer_multi(dsi_ctx, cmd_scaler, + ARRAY_SIZE(cmd_scaler)); } /* * nt35950_inject_black_image - Display a completely black image - * @nt: Main driver structure + * @dsi_ctx: context for mipi_dsi functions * * After IC setup, the attached panel may show random data * due to driveric behavior changes (resolution, compression, @@ -208,43 +189,34 @@ static int nt35950_set_scale_mode(struct nt35950 *nt, u8 mode) * the display. * It makes sense to push a black image before sending the sleep-out * and display-on commands. - * - * Return: Number of transferred bytes or negative number on error */ -static int nt35950_inject_black_image(struct nt35950 *nt) +static void nt35950_inject_black_image(struct mipi_dsi_multi_context *dsi_ctx) { const u8 cmd0_black_img[] = { 0x6f, 0x01 }; const u8 cmd1_black_img[] = { 0xf3, 0x10 }; u8 cmd_test[] = { 0xff, 0xaa, 0x55, 0xa5, 0x80 }; - int ret; /* Enable test command */ - ret = mipi_dsi_dcs_write_buffer(nt->dsi[0], cmd_test, ARRAY_SIZE(cmd_test)); - if (ret < 0) - return ret; + mipi_dsi_dcs_write_buffer_multi(dsi_ctx, cmd_test, ARRAY_SIZE(cmd_test)); /* Send a black image */ - ret = mipi_dsi_dcs_write_buffer(nt->dsi[0], cmd0_black_img, + mipi_dsi_dcs_write_buffer_multi(dsi_ctx, cmd0_black_img, ARRAY_SIZE(cmd0_black_img)); - if (ret < 0) - return ret; - ret = mipi_dsi_dcs_write_buffer(nt->dsi[0], cmd1_black_img, + mipi_dsi_dcs_write_buffer_multi(dsi_ctx, cmd1_black_img, ARRAY_SIZE(cmd1_black_img)); - if (ret < 0) - return ret; /* Disable test command */ cmd_test[ARRAY_SIZE(cmd_test) - 1] = 0x00; - return mipi_dsi_dcs_write_buffer(nt->dsi[0], cmd_test, ARRAY_SIZE(cmd_test)); + mipi_dsi_dcs_write_buffer_multi(dsi_ctx, cmd_test, ARRAY_SIZE(cmd_test)); } /* * nt35950_set_dispout - Set Display Output register parameters * @nt: Main driver structure - * - * Return: Number of transferred bytes or negative number on error + * @dsi_ctx: context for mipi_dsi functions */ -static int nt35950_set_dispout(struct nt35950 *nt) +static void nt35950_set_dispout(struct mipi_dsi_multi_context *dsi_ctx, + struct nt35950 *nt) { u8 cmd_dispout[] = { MCS_PARAM_DISP_OUTPUT_CTRL, 0x00 }; const struct nt35950_panel_mode *mode_data = nt->desc->mode_data; @@ -254,8 +226,8 @@ static int nt35950_set_dispout(struct nt35950 *nt) if (mode_data[nt->cur_mode].enable_sram) cmd_dispout[1] |= MCS_DISP_OUT_SRAM_EN; - return mipi_dsi_dcs_write_buffer(nt->dsi[0], cmd_dispout, - ARRAY_SIZE(cmd_dispout)); + mipi_dsi_dcs_write_buffer_multi(dsi_ctx, cmd_dispout, + ARRAY_SIZE(cmd_dispout)); } static int nt35950_get_current_mode(struct nt35950 *nt) @@ -284,78 +256,47 @@ static int nt35950_on(struct nt35950 *nt) { const struct nt35950_panel_mode *mode_data = nt->desc->mode_data; struct mipi_dsi_device *dsi = nt->dsi[0]; - struct device *dev = &dsi->dev; - int ret; + struct mipi_dsi_multi_context dsi_ctx = { .dsi = dsi }; nt->cur_mode = nt35950_get_current_mode(nt); nt->dsi[0]->mode_flags |= MIPI_DSI_MODE_LPM; nt->dsi[1]->mode_flags |= MIPI_DSI_MODE_LPM; - ret = nt35950_set_cmd2_page(nt, 0); - if (ret < 0) - return ret; + nt35950_set_cmd2_page(&dsi_ctx, nt, 0); + nt35950_set_data_compression(&dsi_ctx, nt, mode_data[nt->cur_mode].compression); + nt35950_set_scale_mode(&dsi_ctx, mode_data[nt->cur_mode].scaler_mode); + nt35950_set_scaler(&dsi_ctx, mode_data[nt->cur_mode].scaler_on); + nt35950_set_dispout(&dsi_ctx, nt); - ret = nt35950_set_data_compression(nt, mode_data[nt->cur_mode].compression); - if (ret < 0) - return ret; - - ret = nt35950_set_scale_mode(nt, mode_data[nt->cur_mode].scaler_mode); - if (ret < 0) - return ret; - - ret = nt35950_set_scaler(nt, mode_data[nt->cur_mode].scaler_on); - if (ret < 0) - return ret; - - ret = nt35950_set_dispout(nt); - if (ret < 0) - return ret; - - ret = mipi_dsi_dcs_set_tear_on(dsi, MIPI_DSI_DCS_TEAR_MODE_VBLANK); - if (ret < 0) { - dev_err(dev, "Failed to set tear on: %d\n", ret); - return ret; - } - - ret = mipi_dsi_dcs_set_tear_scanline(dsi, 0); - if (ret < 0) { - dev_err(dev, "Failed to set tear scanline: %d\n", ret); - return ret; - } + mipi_dsi_dcs_set_tear_on_multi(&dsi_ctx, MIPI_DSI_DCS_TEAR_MODE_VBLANK); + mipi_dsi_dcs_set_tear_scanline_multi(&dsi_ctx, 0); /* CMD2 Page 1 */ - ret = nt35950_set_cmd2_page(nt, 1); - if (ret < 0) - return ret; + nt35950_set_cmd2_page(&dsi_ctx, nt, 1); /* Unknown command */ - mipi_dsi_dcs_write_seq(dsi, 0xd4, 0x88, 0x88); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xd4, 0x88, 0x88); /* CMD2 Page 7 */ - ret = nt35950_set_cmd2_page(nt, 7); - if (ret < 0) - return ret; + nt35950_set_cmd2_page(&dsi_ctx, nt, 7); /* Enable SubPixel Rendering */ - mipi_dsi_dcs_write_seq(dsi, MCS_PARAM_SPR_EN, 0x01); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, MCS_PARAM_SPR_EN, 0x01); /* SPR Mode: YYG Rainbow-RGB */ - mipi_dsi_dcs_write_seq(dsi, MCS_PARAM_SPR_MODE, MCS_SPR_MODE_YYG_RAINBOW_RGB); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, MCS_PARAM_SPR_MODE, + MCS_SPR_MODE_YYG_RAINBOW_RGB); /* CMD3 */ - ret = nt35950_inject_black_image(nt); - if (ret < 0) - return ret; + nt35950_inject_black_image(&dsi_ctx); + mipi_dsi_dcs_exit_sleep_mode_multi(&dsi_ctx); + mipi_dsi_msleep(&dsi_ctx, 120); - ret = mipi_dsi_dcs_exit_sleep_mode(dsi); - if (ret < 0) - return ret; - msleep(120); + mipi_dsi_dcs_set_display_on_multi(&dsi_ctx); + mipi_dsi_msleep(&dsi_ctx, 120); - ret = mipi_dsi_dcs_set_display_on(dsi); - if (ret < 0) - return ret; - msleep(120); + if (dsi_ctx.accum_err) + return dsi_ctx.accum_err; nt->dsi[0]->mode_flags &= ~MIPI_DSI_MODE_LPM; nt->dsi[1]->mode_flags &= ~MIPI_DSI_MODE_LPM; @@ -363,30 +304,19 @@ static int nt35950_on(struct nt35950 *nt) return 0; } -static int nt35950_off(struct nt35950 *nt) +static void nt35950_off(struct nt35950 *nt) { - struct device *dev = &nt->dsi[0]->dev; - int ret; + struct mipi_dsi_device *dsi = nt->dsi[0]; + struct mipi_dsi_multi_context dsi_ctx = { .dsi = dsi }; - ret = mipi_dsi_dcs_set_display_off(nt->dsi[0]); - if (ret < 0) { - dev_err(dev, "Failed to set display off: %d\n", ret); - goto set_lpm; - } - usleep_range(10000, 11000); + mipi_dsi_dcs_set_display_off_multi(&dsi_ctx); + mipi_dsi_usleep_range(&dsi_ctx, 10000, 11000); - ret = mipi_dsi_dcs_enter_sleep_mode(nt->dsi[0]); - if (ret < 0) { - dev_err(dev, "Failed to enter sleep mode: %d\n", ret); - goto set_lpm; - } - msleep(150); + mipi_dsi_dcs_enter_sleep_mode_multi(&dsi_ctx); + mipi_dsi_msleep(&dsi_ctx, 150); -set_lpm: nt->dsi[0]->mode_flags |= MIPI_DSI_MODE_LPM; nt->dsi[1]->mode_flags |= MIPI_DSI_MODE_LPM; - - return 0; } static int nt35950_sharp_init_vregs(struct nt35950 *nt, struct device *dev) @@ -427,7 +357,6 @@ static int nt35950_sharp_init_vregs(struct nt35950 *nt, struct device *dev) static int nt35950_prepare(struct drm_panel *panel) { struct nt35950 *nt = to_nt35950(panel); - struct device *dev = &nt->dsi[0]->dev; int ret; ret = regulator_enable(nt->vregs[0].consumer); @@ -452,10 +381,6 @@ static int nt35950_prepare(struct drm_panel *panel) nt35950_reset(nt); ret = nt35950_on(nt); - if (ret < 0) { - dev_err(dev, "Failed to initialize panel: %d\n", ret); - goto end; - } end: if (ret < 0) { @@ -469,12 +394,8 @@ end: static int nt35950_unprepare(struct drm_panel *panel) { struct nt35950 *nt = to_nt35950(panel); - struct device *dev = &nt->dsi[0]->dev; - int ret; - ret = nt35950_off(nt); - if (ret < 0) - dev_err(dev, "Failed to deinitialize panel: %d\n", ret); + nt35950_off(nt); gpiod_set_value_cansleep(nt->reset_gpio, 0); regulator_bulk_disable(ARRAY_SIZE(nt->vregs), nt->vregs); diff --git a/drivers/gpu/drm/panel/panel-novatek-nt36672e.c b/drivers/gpu/drm/panel/panel-novatek-nt36672e.c index e81a70147259..8c9e04207ba9 100644 --- a/drivers/gpu/drm/panel/panel-novatek-nt36672e.c +++ b/drivers/gpu/drm/panel/panel-novatek-nt36672e.c @@ -44,6 +44,16 @@ struct nt36672e_panel { const struct panel_desc *desc; }; +#define NT36672E_DCS_SWITCH_PAGE 0xff + +#define nt36672e_switch_page(ctx, page) \ + mipi_dsi_dcs_write_seq_multi(ctx, NT36672E_DCS_SWITCH_PAGE, (page)) + +static void nt36672e_enable_reload_cmds(struct mipi_dsi_multi_context *ctx) +{ + mipi_dsi_dcs_write_seq_multi(ctx, 0xfb, 0x01); +} + static inline struct nt36672e_panel *to_nt36672e_panel(struct drm_panel *panel) { return container_of(panel, struct nt36672e_panel, panel); @@ -51,16 +61,16 @@ static inline struct nt36672e_panel *to_nt36672e_panel(struct drm_panel *panel) static void nt36672e_1080x2408_60hz_init(struct mipi_dsi_multi_context *ctx) { - mipi_dsi_dcs_write_seq_multi(ctx, 0xff, 0x10); - mipi_dsi_dcs_write_seq_multi(ctx, 0xfb, 0x01); + nt36672e_switch_page(ctx, 0x10); + nt36672e_enable_reload_cmds(ctx); mipi_dsi_dcs_write_seq_multi(ctx, 0xb0, 0x00); mipi_dsi_dcs_write_seq_multi(ctx, 0xc0, 0x00); mipi_dsi_dcs_write_seq_multi(ctx, 0xc1, 0x89, 0x28, 0x00, 0x08, 0x00, 0xaa, 0x02, 0x0e, 0x00, 0x2b, 0x00, 0x07, 0x0d, 0xb7, 0x0c, 0xb7); - mipi_dsi_dcs_write_seq_multi(ctx, 0xc2, 0x1b, 0xa0); - mipi_dsi_dcs_write_seq_multi(ctx, 0xff, 0x20); - mipi_dsi_dcs_write_seq_multi(ctx, 0xfb, 0x01); + + nt36672e_switch_page(ctx, 0x20); + nt36672e_enable_reload_cmds(ctx); mipi_dsi_dcs_write_seq_multi(ctx, 0x01, 0x66); mipi_dsi_dcs_write_seq_multi(ctx, 0x06, 0x40); mipi_dsi_dcs_write_seq_multi(ctx, 0x07, 0x38); @@ -76,8 +86,9 @@ static void nt36672e_1080x2408_60hz_init(struct mipi_dsi_multi_context *ctx) mipi_dsi_dcs_write_seq_multi(ctx, 0xf7, 0x54); mipi_dsi_dcs_write_seq_multi(ctx, 0xf8, 0x64); mipi_dsi_dcs_write_seq_multi(ctx, 0xf9, 0x54); - mipi_dsi_dcs_write_seq_multi(ctx, 0xff, 0x24); - mipi_dsi_dcs_write_seq_multi(ctx, 0xfb, 0x01); + + nt36672e_switch_page(ctx, 0x24); + nt36672e_enable_reload_cmds(ctx); mipi_dsi_dcs_write_seq_multi(ctx, 0x01, 0x0f); mipi_dsi_dcs_write_seq_multi(ctx, 0x03, 0x0c); mipi_dsi_dcs_write_seq_multi(ctx, 0x05, 0x1d); @@ -139,8 +150,9 @@ static void nt36672e_1080x2408_60hz_init(struct mipi_dsi_multi_context *ctx) mipi_dsi_dcs_write_seq_multi(ctx, 0xc9, 0x00); mipi_dsi_dcs_write_seq_multi(ctx, 0xd9, 0x80); mipi_dsi_dcs_write_seq_multi(ctx, 0xe9, 0x02); - mipi_dsi_dcs_write_seq_multi(ctx, 0xff, 0x25); - mipi_dsi_dcs_write_seq_multi(ctx, 0xfb, 0x01); + + nt36672e_switch_page(ctx, 0x25); + nt36672e_enable_reload_cmds(ctx); mipi_dsi_dcs_write_seq_multi(ctx, 0x18, 0x22); mipi_dsi_dcs_write_seq_multi(ctx, 0x19, 0xe4); mipi_dsi_dcs_write_seq_multi(ctx, 0x21, 0x40); @@ -164,8 +176,9 @@ static void nt36672e_1080x2408_60hz_init(struct mipi_dsi_multi_context *ctx) mipi_dsi_dcs_write_seq_multi(ctx, 0xd7, 0x80); mipi_dsi_dcs_write_seq_multi(ctx, 0xef, 0x20); mipi_dsi_dcs_write_seq_multi(ctx, 0xf0, 0x84); - mipi_dsi_dcs_write_seq_multi(ctx, 0xff, 0x26); - mipi_dsi_dcs_write_seq_multi(ctx, 0xfb, 0x01); + + nt36672e_switch_page(ctx, 0x26); + nt36672e_enable_reload_cmds(ctx); mipi_dsi_dcs_write_seq_multi(ctx, 0x81, 0x0f); mipi_dsi_dcs_write_seq_multi(ctx, 0x83, 0x01); mipi_dsi_dcs_write_seq_multi(ctx, 0x84, 0x03); @@ -185,8 +198,9 @@ static void nt36672e_1080x2408_60hz_init(struct mipi_dsi_multi_context *ctx) mipi_dsi_dcs_write_seq_multi(ctx, 0x9c, 0x00); mipi_dsi_dcs_write_seq_multi(ctx, 0x9d, 0x00); mipi_dsi_dcs_write_seq_multi(ctx, 0x9e, 0x00); - mipi_dsi_dcs_write_seq_multi(ctx, 0xff, 0x27); - mipi_dsi_dcs_write_seq_multi(ctx, 0xfb, 0x01); + + nt36672e_switch_page(ctx, 0x27); + nt36672e_enable_reload_cmds(ctx); mipi_dsi_dcs_write_seq_multi(ctx, 0x01, 0x68); mipi_dsi_dcs_write_seq_multi(ctx, 0x20, 0x81); mipi_dsi_dcs_write_seq_multi(ctx, 0x21, 0x6a); @@ -215,8 +229,9 @@ static void nt36672e_1080x2408_60hz_init(struct mipi_dsi_multi_context *ctx) mipi_dsi_dcs_write_seq_multi(ctx, 0xe6, 0xd3); mipi_dsi_dcs_write_seq_multi(ctx, 0xeb, 0x03); mipi_dsi_dcs_write_seq_multi(ctx, 0xec, 0x28); - mipi_dsi_dcs_write_seq_multi(ctx, 0xff, 0x2a); - mipi_dsi_dcs_write_seq_multi(ctx, 0xfb, 0x01); + + nt36672e_switch_page(ctx, 0x2a); + nt36672e_enable_reload_cmds(ctx); mipi_dsi_dcs_write_seq_multi(ctx, 0x00, 0x91); mipi_dsi_dcs_write_seq_multi(ctx, 0x03, 0x20); mipi_dsi_dcs_write_seq_multi(ctx, 0x07, 0x50); @@ -260,8 +275,9 @@ static void nt36672e_1080x2408_60hz_init(struct mipi_dsi_multi_context *ctx) mipi_dsi_dcs_write_seq_multi(ctx, 0x8c, 0x7d); mipi_dsi_dcs_write_seq_multi(ctx, 0x8d, 0x7d); mipi_dsi_dcs_write_seq_multi(ctx, 0x8e, 0x7d); - mipi_dsi_dcs_write_seq_multi(ctx, 0xff, 0x20); - mipi_dsi_dcs_write_seq_multi(ctx, 0xfb, 0x01); + + nt36672e_switch_page(ctx, 0x20); + nt36672e_enable_reload_cmds(ctx); mipi_dsi_dcs_write_seq_multi(ctx, 0xb0, 0x00, 0x00, 0x00, 0x17, 0x00, 0x49, 0x00, 0x6a, 0x00, 0x89, 0x00, 0x9f, 0x00, 0xb6, 0x00, 0xc8); mipi_dsi_dcs_write_seq_multi(ctx, 0xb1, 0x00, 0xd9, 0x01, 0x10, 0x01, 0x3a, 0x01, @@ -286,8 +302,9 @@ static void nt36672e_1080x2408_60hz_init(struct mipi_dsi_multi_context *ctx) 0x01, 0x03, 0x1f, 0x03, 0x4a, 0x03, 0x59, 0x03, 0x6a); mipi_dsi_dcs_write_seq_multi(ctx, 0xbb, 0x03, 0x7d, 0x03, 0x93, 0x03, 0xab, 0x03, 0xc8, 0x03, 0xec, 0x03, 0xfe, 0x00, 0x00); - mipi_dsi_dcs_write_seq_multi(ctx, 0xff, 0x21); - mipi_dsi_dcs_write_seq_multi(ctx, 0xfb, 0x01); + + nt36672e_switch_page(ctx, 0x21); + nt36672e_enable_reload_cmds(ctx); mipi_dsi_dcs_write_seq_multi(ctx, 0xb0, 0x00, 0x00, 0x00, 0x17, 0x00, 0x49, 0x00, 0x6a, 0x00, 0x89, 0x00, 0x9f, 0x00, 0xb6, 0x00, 0xc8); mipi_dsi_dcs_write_seq_multi(ctx, 0xb1, 0x00, 0xd9, 0x01, 0x10, 0x01, 0x3a, 0x01, @@ -312,8 +329,9 @@ static void nt36672e_1080x2408_60hz_init(struct mipi_dsi_multi_context *ctx) 0x01, 0x03, 0x1f, 0x03, 0x4a, 0x03, 0x59, 0x03, 0x6a); mipi_dsi_dcs_write_seq_multi(ctx, 0xbb, 0x03, 0x7d, 0x03, 0x93, 0x03, 0xab, 0x03, 0xc8, 0x03, 0xec, 0x03, 0xfe, 0x00, 0x00); - mipi_dsi_dcs_write_seq_multi(ctx, 0xff, 0x2c); - mipi_dsi_dcs_write_seq_multi(ctx, 0xfb, 0x01); + + nt36672e_switch_page(ctx, 0x2c); + nt36672e_enable_reload_cmds(ctx); mipi_dsi_dcs_write_seq_multi(ctx, 0x61, 0x1f); mipi_dsi_dcs_write_seq_multi(ctx, 0x62, 0x1f); mipi_dsi_dcs_write_seq_multi(ctx, 0x7e, 0x03); @@ -327,12 +345,13 @@ static void nt36672e_1080x2408_60hz_init(struct mipi_dsi_multi_context *ctx) mipi_dsi_dcs_write_seq_multi(ctx, 0x56, 0x0f); mipi_dsi_dcs_write_seq_multi(ctx, 0x58, 0x0f); mipi_dsi_dcs_write_seq_multi(ctx, 0x59, 0x0f); - mipi_dsi_dcs_write_seq_multi(ctx, 0xff, 0xf0); - mipi_dsi_dcs_write_seq_multi(ctx, 0xfb, 0x01); + + nt36672e_switch_page(ctx, 0xf0); + nt36672e_enable_reload_cmds(ctx); mipi_dsi_dcs_write_seq_multi(ctx, 0x5a, 0x00); - mipi_dsi_dcs_write_seq_multi(ctx, 0xff, 0x10); - mipi_dsi_dcs_write_seq_multi(ctx, 0xfb, 0x01); + nt36672e_switch_page(ctx, 0x10); + nt36672e_enable_reload_cmds(ctx); mipi_dsi_dcs_write_seq_multi(ctx, 0x51, 0xff); mipi_dsi_dcs_write_seq_multi(ctx, 0x53, 0x24); mipi_dsi_dcs_write_seq_multi(ctx, 0x55, 0x01); diff --git a/drivers/gpu/drm/panel/panel-orisetech-otm8009a.c b/drivers/gpu/drm/panel/panel-orisetech-otm8009a.c index 93183f30d7d6..a9b5dad70bc1 100644 --- a/drivers/gpu/drm/panel/panel-orisetech-otm8009a.c +++ b/drivers/gpu/drm/panel/panel-orisetech-otm8009a.c @@ -389,7 +389,7 @@ static int otm8009a_backlight_update_status(struct backlight_device *bd) return -ENXIO; } - if (bd->props.power <= FB_BLANK_NORMAL) { + if (bd->props.power <= BACKLIGHT_POWER_REDUCED) { /* Power on the backlight with the requested brightness * Note We can not use mipi_dsi_dcs_set_display_brightness() * as otm8009a driver support only 8-bit brightness (1 param). @@ -465,7 +465,7 @@ static int otm8009a_probe(struct mipi_dsi_device *dsi) ctx->bl_dev->props.max_brightness = OTM8009A_BACKLIGHT_MAX; ctx->bl_dev->props.brightness = OTM8009A_BACKLIGHT_DEFAULT; - ctx->bl_dev->props.power = FB_BLANK_POWERDOWN; + ctx->bl_dev->props.power = BACKLIGHT_POWER_OFF; ctx->bl_dev->props.type = BACKLIGHT_RAW; drm_panel_add(&ctx->panel); diff --git a/drivers/gpu/drm/panel/panel-samsung-s6e3ha2.c b/drivers/gpu/drm/panel/panel-samsung-s6e3ha2.c index 639a4fdf57bb..ab8b58545284 100644 --- a/drivers/gpu/drm/panel/panel-samsung-s6e3ha2.c +++ b/drivers/gpu/drm/panel/panel-samsung-s6e3ha2.c @@ -458,7 +458,7 @@ static int s6e3ha2_set_brightness(struct backlight_device *bl_dev) return -EINVAL; } - if (bl_dev->props.power > FB_BLANK_NORMAL) + if (bl_dev->props.power > BACKLIGHT_POWER_REDUCED) return -EPERM; s6e3ha2_call_write_func(ret, s6e3ha2_test_key_on_f0(ctx)); @@ -508,7 +508,7 @@ static int s6e3ha2_disable(struct drm_panel *panel) s6e3ha2_call_write_func(ret, mipi_dsi_dcs_set_display_off(dsi)); msleep(40); - ctx->bl_dev->props.power = FB_BLANK_NORMAL; + ctx->bl_dev->props.power = BACKLIGHT_POWER_REDUCED; return 0; } @@ -554,7 +554,7 @@ static int s6e3ha2_prepare(struct drm_panel *panel) if (ret < 0) goto err; - ctx->bl_dev->props.power = FB_BLANK_NORMAL; + ctx->bl_dev->props.power = BACKLIGHT_POWER_REDUCED; return 0; @@ -601,7 +601,7 @@ static int s6e3ha2_enable(struct drm_panel *panel) s6e3ha2_call_write_func(ret, s6e3ha2_test_key_off_f0(ctx)); s6e3ha2_call_write_func(ret, mipi_dsi_dcs_set_display_on(dsi)); - ctx->bl_dev->props.power = FB_BLANK_UNBLANK; + ctx->bl_dev->props.power = BACKLIGHT_POWER_ON; return 0; } @@ -729,7 +729,7 @@ static int s6e3ha2_probe(struct mipi_dsi_device *dsi) ctx->bl_dev->props.max_brightness = S6E3HA2_MAX_BRIGHTNESS; ctx->bl_dev->props.brightness = S6E3HA2_DEFAULT_BRIGHTNESS; - ctx->bl_dev->props.power = FB_BLANK_POWERDOWN; + ctx->bl_dev->props.power = BACKLIGHT_POWER_OFF; drm_panel_init(&ctx->panel, dev, &s6e3ha2_drm_funcs, DRM_MODE_CONNECTOR_DSI); diff --git a/drivers/gpu/drm/panel/panel-samsung-s6e63j0x03.c b/drivers/gpu/drm/panel/panel-samsung-s6e63j0x03.c index 46d6f4a87bf7..ed53787d1dea 100644 --- a/drivers/gpu/drm/panel/panel-samsung-s6e63j0x03.c +++ b/drivers/gpu/drm/panel/panel-samsung-s6e63j0x03.c @@ -225,7 +225,7 @@ static int s6e63j0x03_disable(struct drm_panel *panel) if (ret < 0) return ret; - ctx->bl_dev->props.power = FB_BLANK_NORMAL; + ctx->bl_dev->props.power = BACKLIGHT_POWER_REDUCED; ret = mipi_dsi_dcs_enter_sleep_mode(dsi); if (ret < 0) @@ -245,7 +245,7 @@ static int s6e63j0x03_unprepare(struct drm_panel *panel) if (ret < 0) return ret; - ctx->bl_dev->props.power = FB_BLANK_POWERDOWN; + ctx->bl_dev->props.power = BACKLIGHT_POWER_OFF; return 0; } @@ -332,7 +332,7 @@ static int s6e63j0x03_prepare(struct drm_panel *panel) if (ret < 0) goto err; - ctx->bl_dev->props.power = FB_BLANK_NORMAL; + ctx->bl_dev->props.power = BACKLIGHT_POWER_REDUCED; return 0; @@ -393,7 +393,7 @@ static int s6e63j0x03_enable(struct drm_panel *panel) if (ret < 0) return ret; - ctx->bl_dev->props.power = FB_BLANK_UNBLANK; + ctx->bl_dev->props.power = BACKLIGHT_POWER_ON; return 0; } @@ -473,7 +473,7 @@ static int s6e63j0x03_probe(struct mipi_dsi_device *dsi) ctx->bl_dev->props.max_brightness = MAX_BRIGHTNESS; ctx->bl_dev->props.brightness = DEFAULT_BRIGHTNESS; - ctx->bl_dev->props.power = FB_BLANK_POWERDOWN; + ctx->bl_dev->props.power = BACKLIGHT_POWER_OFF; drm_panel_add(&ctx->panel); diff --git a/drivers/gpu/drm/panel/panel-simple.c b/drivers/gpu/drm/panel/panel-simple.c index bf40057c5cf3..86735430462f 100644 --- a/drivers/gpu/drm/panel/panel-simple.c +++ b/drivers/gpu/drm/panel/panel-simple.c @@ -726,16 +726,24 @@ static void panel_simple_shutdown(struct device *dev) * drm_atomic_helper_shutdown() at shutdown time and that should * cause the panel to be disabled / unprepared if needed. For now, * however, we'll keep these calls due to the sheer number of - * different DRM modeset drivers used with panel-simple. The fact that - * we're calling these and _also_ the drm_atomic_helper_shutdown() - * will try to disable/unprepare means that we can get a warning about - * trying to disable/unprepare an already disabled/unprepared panel, - * but that's something we'll have to live with until we've confirmed - * that all DRM modeset drivers are properly calling - * drm_atomic_helper_shutdown(). + * different DRM modeset drivers used with panel-simple. Once we've + * confirmed that all DRM modeset drivers using this panel properly + * call drm_atomic_helper_shutdown() we can simply delete the two + * calls below. + * + * TO BE EXPLICIT: THE CALLS BELOW SHOULDN'T BE COPIED TO ANY NEW + * PANEL DRIVERS. + * + * FIXME: If we're still haven't figured out if all DRM modeset + * drivers properly call drm_atomic_helper_shutdown() but we _have_ + * managed to make sure that DRM modeset drivers get their shutdown() + * callback before the panel's shutdown() callback (perhaps using + * device link), we could add a WARN_ON here to help move forward. */ - drm_panel_disable(&panel->base); - drm_panel_unprepare(&panel->base); + if (panel->base.enabled) + drm_panel_disable(&panel->base); + if (panel->base.prepared) + drm_panel_unprepare(&panel->base); } static void panel_simple_remove(struct device *dev) @@ -2519,6 +2527,38 @@ static const struct panel_desc innolux_g070y2_l01 = { .connector_type = DRM_MODE_CONNECTOR_LVDS, }; +static const struct display_timing innolux_g070ace_lh3_timing = { + .pixelclock = { 25200000, 25400000, 35700000 }, + .hactive = { 800, 800, 800 }, + .hfront_porch = { 30, 32, 87 }, + .hback_porch = { 29, 31, 86 }, + .hsync_len = { 1, 1, 1 }, + .vactive = { 480, 480, 480 }, + .vfront_porch = { 4, 5, 65 }, + .vback_porch = { 3, 4, 65 }, + .vsync_len = { 1, 1, 1 }, + .flags = DISPLAY_FLAGS_DE_HIGH, +}; + +static const struct panel_desc innolux_g070ace_lh3 = { + .timings = &innolux_g070ace_lh3_timing, + .num_timings = 1, + .bpc = 8, + .size = { + .width = 152, + .height = 91, + }, + .delay = { + .prepare = 10, + .enable = 450, + .disable = 200, + .unprepare = 510, + }, + .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, + .bus_flags = DRM_BUS_FLAG_DE_HIGH, + .connector_type = DRM_MODE_CONNECTOR_LVDS, +}; + static const struct drm_display_mode innolux_g070y2_t02_mode = { .clock = 33333, .hdisplay = 800, @@ -3478,6 +3518,39 @@ static const struct panel_desc olimex_lcd_olinuxino_43ts = { .bus_format = MEDIA_BUS_FMT_RGB888_1X24, }; +static const struct display_timing ontat_kd50g21_40nt_a1_timing = { + .pixelclock = { 30000000, 30000000, 50000000 }, + .hactive = { 800, 800, 800 }, + .hfront_porch = { 1, 40, 255 }, + .hback_porch = { 1, 40, 87 }, + .hsync_len = { 1, 48, 87 }, + .vactive = { 480, 480, 480 }, + .vfront_porch = { 1, 13, 255 }, + .vback_porch = { 1, 29, 29 }, + .vsync_len = { 3, 3, 31 }, + .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | + DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE, +}; + +static const struct panel_desc ontat_kd50g21_40nt_a1 = { + .timings = &ontat_kd50g21_40nt_a1_timing, + .num_timings = 1, + .bpc = 8, + .size = { + .width = 108, + .height = 65, + }, + .delay = { + .prepare = 147, /* 5 VSDs */ + .enable = 147, /* 5 VSDs */ + .disable = 88, /* 3 VSDs */ + .unprepare = 117, /* 4 VSDs */ + }, + .bus_format = MEDIA_BUS_FMT_RGB888_1X24, + .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, + .connector_type = DRM_MODE_CONNECTOR_DPI, +}; + /* * 800x480 CVT. The panel appears to be quite accepting, at least as far as * pixel clocks, but this is the timing that was being used in the Adafruit @@ -4727,6 +4800,9 @@ static const struct of_device_id platform_of_match[] = { .compatible = "innolux,g070ace-l01", .data = &innolux_g070ace_l01, }, { + .compatible = "innolux,g070ace-lh3", + .data = &innolux_g070ace_lh3, + }, { .compatible = "innolux,g070y2-l01", .data = &innolux_g070y2_l01, }, { @@ -4838,6 +4914,9 @@ static const struct of_device_id platform_of_match[] = { .compatible = "olimex,lcd-olinuxino-43-ts", .data = &olimex_lcd_olinuxino_43ts, }, { + .compatible = "ontat,kd50g21-40nt-a1", + .data = &ontat_kd50g21_40nt_a1, + }, { .compatible = "ontat,yx700wv03", .data = &ontat_yx700wv03, }, { diff --git a/drivers/gpu/drm/panel/panel-sitronix-st7701.c b/drivers/gpu/drm/panel/panel-sitronix-st7701.c index 421eb4592b61..eef03d04e0cd 100644 --- a/drivers/gpu/drm/panel/panel-sitronix-st7701.c +++ b/drivers/gpu/drm/panel/panel-sitronix-st7701.c @@ -4,6 +4,7 @@ * Author: Jagan Teki <jagan@amarulasolutions.com> */ +#include <drm/drm_mipi_dbi.h> #include <drm/drm_mipi_dsi.h> #include <drm/drm_modes.h> #include <drm/drm_panel.h> @@ -14,79 +15,80 @@ #include <linux/module.h> #include <linux/of.h> #include <linux/regulator/consumer.h> +#include <linux/spi/spi.h> #include <video/mipi_display.h> /* Command2 BKx selection command */ -#define DSI_CMD2BKX_SEL 0xFF -#define DSI_CMD1 0 -#define DSI_CMD2 BIT(4) -#define DSI_CMD2BK_MASK GENMASK(3, 0) +#define ST7701_CMD2BKX_SEL 0xFF +#define ST7701_CMD1 0 +#define ST7701_CMD2 BIT(4) +#define ST7701_CMD2BK_MASK GENMASK(3, 0) /* Command2, BK0 commands */ -#define DSI_CMD2_BK0_PVGAMCTRL 0xB0 /* Positive Voltage Gamma Control */ -#define DSI_CMD2_BK0_NVGAMCTRL 0xB1 /* Negative Voltage Gamma Control */ -#define DSI_CMD2_BK0_LNESET 0xC0 /* Display Line setting */ -#define DSI_CMD2_BK0_PORCTRL 0xC1 /* Porch control */ -#define DSI_CMD2_BK0_INVSEL 0xC2 /* Inversion selection, Frame Rate Control */ +#define ST7701_CMD2_BK0_PVGAMCTRL 0xB0 /* Positive Voltage Gamma Control */ +#define ST7701_CMD2_BK0_NVGAMCTRL 0xB1 /* Negative Voltage Gamma Control */ +#define ST7701_CMD2_BK0_LNESET 0xC0 /* Display Line setting */ +#define ST7701_CMD2_BK0_PORCTRL 0xC1 /* Porch control */ +#define ST7701_CMD2_BK0_INVSEL 0xC2 /* Inversion selection, Frame Rate Control */ /* Command2, BK1 commands */ -#define DSI_CMD2_BK1_VRHS 0xB0 /* Vop amplitude setting */ -#define DSI_CMD2_BK1_VCOM 0xB1 /* VCOM amplitude setting */ -#define DSI_CMD2_BK1_VGHSS 0xB2 /* VGH Voltage setting */ -#define DSI_CMD2_BK1_TESTCMD 0xB3 /* TEST Command Setting */ -#define DSI_CMD2_BK1_VGLS 0xB5 /* VGL Voltage setting */ -#define DSI_CMD2_BK1_PWCTLR1 0xB7 /* Power Control 1 */ -#define DSI_CMD2_BK1_PWCTLR2 0xB8 /* Power Control 2 */ -#define DSI_CMD2_BK1_SPD1 0xC1 /* Source pre_drive timing set1 */ -#define DSI_CMD2_BK1_SPD2 0xC2 /* Source EQ2 Setting */ -#define DSI_CMD2_BK1_MIPISET1 0xD0 /* MIPI Setting 1 */ +#define ST7701_CMD2_BK1_VRHS 0xB0 /* Vop amplitude setting */ +#define ST7701_CMD2_BK1_VCOM 0xB1 /* VCOM amplitude setting */ +#define ST7701_CMD2_BK1_VGHSS 0xB2 /* VGH Voltage setting */ +#define ST7701_CMD2_BK1_TESTCMD 0xB3 /* TEST Command Setting */ +#define ST7701_CMD2_BK1_VGLS 0xB5 /* VGL Voltage setting */ +#define ST7701_CMD2_BK1_PWCTLR1 0xB7 /* Power Control 1 */ +#define ST7701_CMD2_BK1_PWCTLR2 0xB8 /* Power Control 2 */ +#define ST7701_CMD2_BK1_SPD1 0xC1 /* Source pre_drive timing set1 */ +#define ST7701_CMD2_BK1_SPD2 0xC2 /* Source EQ2 Setting */ +#define ST7701_CMD2_BK1_MIPISET1 0xD0 /* MIPI Setting 1 */ /* Command2, BK0 bytes */ -#define DSI_CMD2_BK0_GAMCTRL_AJ_MASK GENMASK(7, 6) -#define DSI_CMD2_BK0_GAMCTRL_VC0_MASK GENMASK(3, 0) -#define DSI_CMD2_BK0_GAMCTRL_VC4_MASK GENMASK(5, 0) -#define DSI_CMD2_BK0_GAMCTRL_VC8_MASK GENMASK(5, 0) -#define DSI_CMD2_BK0_GAMCTRL_VC16_MASK GENMASK(4, 0) -#define DSI_CMD2_BK0_GAMCTRL_VC24_MASK GENMASK(4, 0) -#define DSI_CMD2_BK0_GAMCTRL_VC52_MASK GENMASK(3, 0) -#define DSI_CMD2_BK0_GAMCTRL_VC80_MASK GENMASK(5, 0) -#define DSI_CMD2_BK0_GAMCTRL_VC108_MASK GENMASK(3, 0) -#define DSI_CMD2_BK0_GAMCTRL_VC147_MASK GENMASK(3, 0) -#define DSI_CMD2_BK0_GAMCTRL_VC175_MASK GENMASK(5, 0) -#define DSI_CMD2_BK0_GAMCTRL_VC203_MASK GENMASK(3, 0) -#define DSI_CMD2_BK0_GAMCTRL_VC231_MASK GENMASK(4, 0) -#define DSI_CMD2_BK0_GAMCTRL_VC239_MASK GENMASK(4, 0) -#define DSI_CMD2_BK0_GAMCTRL_VC247_MASK GENMASK(5, 0) -#define DSI_CMD2_BK0_GAMCTRL_VC251_MASK GENMASK(5, 0) -#define DSI_CMD2_BK0_GAMCTRL_VC255_MASK GENMASK(4, 0) -#define DSI_CMD2_BK0_LNESET_LINE_MASK GENMASK(6, 0) -#define DSI_CMD2_BK0_LNESET_LDE_EN BIT(7) -#define DSI_CMD2_BK0_LNESET_LINEDELTA GENMASK(1, 0) -#define DSI_CMD2_BK0_PORCTRL_VBP_MASK GENMASK(7, 0) -#define DSI_CMD2_BK0_PORCTRL_VFP_MASK GENMASK(7, 0) -#define DSI_CMD2_BK0_INVSEL_ONES_MASK GENMASK(5, 4) -#define DSI_CMD2_BK0_INVSEL_NLINV_MASK GENMASK(2, 0) -#define DSI_CMD2_BK0_INVSEL_RTNI_MASK GENMASK(4, 0) +#define ST7701_CMD2_BK0_GAMCTRL_AJ_MASK GENMASK(7, 6) +#define ST7701_CMD2_BK0_GAMCTRL_VC0_MASK GENMASK(3, 0) +#define ST7701_CMD2_BK0_GAMCTRL_VC4_MASK GENMASK(5, 0) +#define ST7701_CMD2_BK0_GAMCTRL_VC8_MASK GENMASK(5, 0) +#define ST7701_CMD2_BK0_GAMCTRL_VC16_MASK GENMASK(4, 0) +#define ST7701_CMD2_BK0_GAMCTRL_VC24_MASK GENMASK(4, 0) +#define ST7701_CMD2_BK0_GAMCTRL_VC52_MASK GENMASK(3, 0) +#define ST7701_CMD2_BK0_GAMCTRL_VC80_MASK GENMASK(5, 0) +#define ST7701_CMD2_BK0_GAMCTRL_VC108_MASK GENMASK(3, 0) +#define ST7701_CMD2_BK0_GAMCTRL_VC147_MASK GENMASK(3, 0) +#define ST7701_CMD2_BK0_GAMCTRL_VC175_MASK GENMASK(5, 0) +#define ST7701_CMD2_BK0_GAMCTRL_VC203_MASK GENMASK(3, 0) +#define ST7701_CMD2_BK0_GAMCTRL_VC231_MASK GENMASK(4, 0) +#define ST7701_CMD2_BK0_GAMCTRL_VC239_MASK GENMASK(4, 0) +#define ST7701_CMD2_BK0_GAMCTRL_VC247_MASK GENMASK(5, 0) +#define ST7701_CMD2_BK0_GAMCTRL_VC251_MASK GENMASK(5, 0) +#define ST7701_CMD2_BK0_GAMCTRL_VC255_MASK GENMASK(4, 0) +#define ST7701_CMD2_BK0_LNESET_LINE_MASK GENMASK(6, 0) +#define ST7701_CMD2_BK0_LNESET_LDE_EN BIT(7) +#define ST7701_CMD2_BK0_LNESET_LINEDELTA GENMASK(1, 0) +#define ST7701_CMD2_BK0_PORCTRL_VBP_MASK GENMASK(7, 0) +#define ST7701_CMD2_BK0_PORCTRL_VFP_MASK GENMASK(7, 0) +#define ST7701_CMD2_BK0_INVSEL_ONES_MASK GENMASK(5, 4) +#define ST7701_CMD2_BK0_INVSEL_NLINV_MASK GENMASK(2, 0) +#define ST7701_CMD2_BK0_INVSEL_RTNI_MASK GENMASK(4, 0) /* Command2, BK1 bytes */ -#define DSI_CMD2_BK1_VRHA_MASK GENMASK(7, 0) -#define DSI_CMD2_BK1_VCOM_MASK GENMASK(7, 0) -#define DSI_CMD2_BK1_VGHSS_MASK GENMASK(3, 0) -#define DSI_CMD2_BK1_TESTCMD_VAL BIT(7) -#define DSI_CMD2_BK1_VGLS_ONES BIT(6) -#define DSI_CMD2_BK1_VGLS_MASK GENMASK(3, 0) -#define DSI_CMD2_BK1_PWRCTRL1_AP_MASK GENMASK(7, 6) -#define DSI_CMD2_BK1_PWRCTRL1_APIS_MASK GENMASK(3, 2) -#define DSI_CMD2_BK1_PWRCTRL1_APOS_MASK GENMASK(1, 0) -#define DSI_CMD2_BK1_PWRCTRL2_AVDD_MASK GENMASK(5, 4) -#define DSI_CMD2_BK1_PWRCTRL2_AVCL_MASK GENMASK(1, 0) -#define DSI_CMD2_BK1_SPD1_ONES_MASK GENMASK(6, 4) -#define DSI_CMD2_BK1_SPD1_T2D_MASK GENMASK(3, 0) -#define DSI_CMD2_BK1_SPD2_ONES_MASK GENMASK(6, 4) -#define DSI_CMD2_BK1_SPD2_T3D_MASK GENMASK(3, 0) -#define DSI_CMD2_BK1_MIPISET1_ONES BIT(7) -#define DSI_CMD2_BK1_MIPISET1_EOT_EN BIT(3) +#define ST7701_CMD2_BK1_VRHA_MASK GENMASK(7, 0) +#define ST7701_CMD2_BK1_VCOM_MASK GENMASK(7, 0) +#define ST7701_CMD2_BK1_VGHSS_MASK GENMASK(3, 0) +#define ST7701_CMD2_BK1_TESTCMD_VAL BIT(7) +#define ST7701_CMD2_BK1_VGLS_ONES BIT(6) +#define ST7701_CMD2_BK1_VGLS_MASK GENMASK(3, 0) +#define ST7701_CMD2_BK1_PWRCTRL1_AP_MASK GENMASK(7, 6) +#define ST7701_CMD2_BK1_PWRCTRL1_APIS_MASK GENMASK(3, 2) +#define ST7701_CMD2_BK1_PWRCTRL1_APOS_MASK GENMASK(1, 0) +#define ST7701_CMD2_BK1_PWRCTRL2_AVDD_MASK GENMASK(5, 4) +#define ST7701_CMD2_BK1_PWRCTRL2_AVCL_MASK GENMASK(1, 0) +#define ST7701_CMD2_BK1_SPD1_ONES_MASK GENMASK(6, 4) +#define ST7701_CMD2_BK1_SPD1_T2D_MASK GENMASK(3, 0) +#define ST7701_CMD2_BK1_SPD2_ONES_MASK GENMASK(6, 4) +#define ST7701_CMD2_BK1_SPD2_T3D_MASK GENMASK(3, 0) +#define ST7701_CMD2_BK1_MIPISET1_ONES BIT(7) +#define ST7701_CMD2_BK1_MIPISET1_EOT_EN BIT(3) #define CFIELD_PREP(_mask, _val) \ (((typeof(_mask))(_val) << (__builtin_ffsll(_mask) - 1)) & (_mask)) @@ -130,12 +132,16 @@ struct st7701_panel_desc { struct st7701 { struct drm_panel panel; struct mipi_dsi_device *dsi; + struct mipi_dbi dbi; const struct st7701_panel_desc *desc; struct regulator_bulk_data supplies[2]; struct gpio_desc *reset; unsigned int sleep_delay; enum drm_panel_orientation orientation; + + int (*write_command)(struct st7701 *st7701, u8 cmd, const u8 *seq, + size_t len); }; static inline struct st7701 *panel_to_st7701(struct drm_panel *panel) @@ -143,16 +149,22 @@ static inline struct st7701 *panel_to_st7701(struct drm_panel *panel) return container_of(panel, struct st7701, panel); } -static inline int st7701_dsi_write(struct st7701 *st7701, const void *seq, - size_t len) +static int st7701_dsi_write(struct st7701 *st7701, u8 cmd, const u8 *seq, + size_t len) +{ + return mipi_dsi_dcs_write(st7701->dsi, cmd, seq, len); +} + +static int st7701_dbi_write(struct st7701 *st7701, u8 cmd, const u8 *seq, + size_t len) { - return mipi_dsi_dcs_write_buffer(st7701->dsi, seq, len); + return mipi_dbi_command_stackbuf(&st7701->dbi, cmd, seq, len); } -#define ST7701_DSI(st7701, seq...) \ - { \ - const u8 d[] = { seq }; \ - st7701_dsi_write(st7701, d, ARRAY_SIZE(d)); \ +#define ST7701_WRITE(st7701, cmd, seq...) \ + { \ + const u8 d[] = { seq }; \ + st7701->write_command(st7701, cmd, d, ARRAY_SIZE(d)); \ } static u8 st7701_vgls_map(struct st7701 *st7701) @@ -185,11 +197,11 @@ static void st7701_switch_cmd_bkx(struct st7701 *st7701, bool cmd2, u8 bkx) u8 val; if (cmd2) - val = DSI_CMD2 | FIELD_PREP(DSI_CMD2BK_MASK, bkx); + val = ST7701_CMD2 | FIELD_PREP(ST7701_CMD2BK_MASK, bkx); else - val = DSI_CMD1; + val = ST7701_CMD1; - ST7701_DSI(st7701, DSI_CMD2BKX_SEL, 0x77, 0x01, 0x00, 0x00, val); + ST7701_WRITE(st7701, ST7701_CMD2BKX_SEL, 0x77, 0x01, 0x00, 0x00, val); } static void st7701_init_sequence(struct st7701 *st7701) @@ -199,22 +211,22 @@ static void st7701_init_sequence(struct st7701 *st7701) const u8 linecount8 = mode->vdisplay / 8; const u8 linecountrem2 = (mode->vdisplay % 8) / 2; - ST7701_DSI(st7701, MIPI_DCS_SOFT_RESET, 0x00); + ST7701_WRITE(st7701, MIPI_DCS_SOFT_RESET, 0x00); /* We need to wait 5ms before sending new commands */ msleep(5); - ST7701_DSI(st7701, MIPI_DCS_EXIT_SLEEP_MODE, 0x00); + ST7701_WRITE(st7701, MIPI_DCS_EXIT_SLEEP_MODE, 0x00); msleep(st7701->sleep_delay); /* Command2, BK0 */ st7701_switch_cmd_bkx(st7701, true, 0); - mipi_dsi_dcs_write(st7701->dsi, DSI_CMD2_BK0_PVGAMCTRL, - desc->pv_gamma, ARRAY_SIZE(desc->pv_gamma)); - mipi_dsi_dcs_write(st7701->dsi, DSI_CMD2_BK0_NVGAMCTRL, - desc->nv_gamma, ARRAY_SIZE(desc->nv_gamma)); + st7701->write_command(st7701, ST7701_CMD2_BK0_PVGAMCTRL, desc->pv_gamma, + ARRAY_SIZE(desc->pv_gamma)); + st7701->write_command(st7701, ST7701_CMD2_BK0_NVGAMCTRL, desc->nv_gamma, + ARRAY_SIZE(desc->nv_gamma)); /* * Vertical line count configuration: * Line[6:0]: select number of vertical lines of the TFT matrix in @@ -226,14 +238,14 @@ static void st7701_init_sequence(struct st7701 *st7701) * Total number of vertical lines: * LN = ((Line[6:0] + 1) * 8) + (LDE_EN ? Line_delta[1:0] * 2 : 0) */ - ST7701_DSI(st7701, DSI_CMD2_BK0_LNESET, - FIELD_PREP(DSI_CMD2_BK0_LNESET_LINE_MASK, linecount8 - 1) | - (linecountrem2 ? DSI_CMD2_BK0_LNESET_LDE_EN : 0), - FIELD_PREP(DSI_CMD2_BK0_LNESET_LINEDELTA, linecountrem2)); - ST7701_DSI(st7701, DSI_CMD2_BK0_PORCTRL, - FIELD_PREP(DSI_CMD2_BK0_PORCTRL_VBP_MASK, + ST7701_WRITE(st7701, ST7701_CMD2_BK0_LNESET, + FIELD_PREP(ST7701_CMD2_BK0_LNESET_LINE_MASK, linecount8 - 1) | + (linecountrem2 ? ST7701_CMD2_BK0_LNESET_LDE_EN : 0), + FIELD_PREP(ST7701_CMD2_BK0_LNESET_LINEDELTA, linecountrem2)); + ST7701_WRITE(st7701, ST7701_CMD2_BK0_PORCTRL, + FIELD_PREP(ST7701_CMD2_BK0_PORCTRL_VBP_MASK, mode->vtotal - mode->vsync_end), - FIELD_PREP(DSI_CMD2_BK0_PORCTRL_VFP_MASK, + FIELD_PREP(ST7701_CMD2_BK0_PORCTRL_VFP_MASK, mode->vsync_start - mode->vdisplay)); /* * Horizontal pixel count configuration: @@ -241,70 +253,70 @@ static void st7701_init_sequence(struct st7701 *st7701) * The PCLK is number of pixel clock per line, which matches * mode htotal. The minimum is 512 PCLK. */ - ST7701_DSI(st7701, DSI_CMD2_BK0_INVSEL, - DSI_CMD2_BK0_INVSEL_ONES_MASK | - FIELD_PREP(DSI_CMD2_BK0_INVSEL_NLINV_MASK, desc->nlinv), - FIELD_PREP(DSI_CMD2_BK0_INVSEL_RTNI_MASK, + ST7701_WRITE(st7701, ST7701_CMD2_BK0_INVSEL, + ST7701_CMD2_BK0_INVSEL_ONES_MASK | + FIELD_PREP(ST7701_CMD2_BK0_INVSEL_NLINV_MASK, desc->nlinv), + FIELD_PREP(ST7701_CMD2_BK0_INVSEL_RTNI_MASK, (clamp((u32)mode->htotal, 512U, 1008U) - 512) / 16)); /* Command2, BK1 */ st7701_switch_cmd_bkx(st7701, true, 1); /* Vop = 3.5375V + (VRHA[7:0] * 0.0125V) */ - ST7701_DSI(st7701, DSI_CMD2_BK1_VRHS, - FIELD_PREP(DSI_CMD2_BK1_VRHA_MASK, + ST7701_WRITE(st7701, ST7701_CMD2_BK1_VRHS, + FIELD_PREP(ST7701_CMD2_BK1_VRHA_MASK, DIV_ROUND_CLOSEST(desc->vop_uv - 3537500, 12500))); /* Vcom = 0.1V + (VCOM[7:0] * 0.0125V) */ - ST7701_DSI(st7701, DSI_CMD2_BK1_VCOM, - FIELD_PREP(DSI_CMD2_BK1_VCOM_MASK, + ST7701_WRITE(st7701, ST7701_CMD2_BK1_VCOM, + FIELD_PREP(ST7701_CMD2_BK1_VCOM_MASK, DIV_ROUND_CLOSEST(desc->vcom_uv - 100000, 12500))); /* Vgh = 11.5V + (VGHSS[7:0] * 0.5V) */ - ST7701_DSI(st7701, DSI_CMD2_BK1_VGHSS, - FIELD_PREP(DSI_CMD2_BK1_VGHSS_MASK, + ST7701_WRITE(st7701, ST7701_CMD2_BK1_VGHSS, + FIELD_PREP(ST7701_CMD2_BK1_VGHSS_MASK, DIV_ROUND_CLOSEST(clamp(desc->vgh_mv, (u16)11500, (u16)17000) - 11500, 500))); - ST7701_DSI(st7701, DSI_CMD2_BK1_TESTCMD, DSI_CMD2_BK1_TESTCMD_VAL); + ST7701_WRITE(st7701, ST7701_CMD2_BK1_TESTCMD, ST7701_CMD2_BK1_TESTCMD_VAL); /* Vgl is non-linear */ - ST7701_DSI(st7701, DSI_CMD2_BK1_VGLS, - DSI_CMD2_BK1_VGLS_ONES | - FIELD_PREP(DSI_CMD2_BK1_VGLS_MASK, st7701_vgls_map(st7701))); + ST7701_WRITE(st7701, ST7701_CMD2_BK1_VGLS, + ST7701_CMD2_BK1_VGLS_ONES | + FIELD_PREP(ST7701_CMD2_BK1_VGLS_MASK, st7701_vgls_map(st7701))); - ST7701_DSI(st7701, DSI_CMD2_BK1_PWCTLR1, - FIELD_PREP(DSI_CMD2_BK1_PWRCTRL1_AP_MASK, + ST7701_WRITE(st7701, ST7701_CMD2_BK1_PWCTLR1, + FIELD_PREP(ST7701_CMD2_BK1_PWRCTRL1_AP_MASK, desc->gamma_op_bias) | - FIELD_PREP(DSI_CMD2_BK1_PWRCTRL1_APIS_MASK, + FIELD_PREP(ST7701_CMD2_BK1_PWRCTRL1_APIS_MASK, desc->input_op_bias) | - FIELD_PREP(DSI_CMD2_BK1_PWRCTRL1_APOS_MASK, + FIELD_PREP(ST7701_CMD2_BK1_PWRCTRL1_APOS_MASK, desc->output_op_bias)); /* Avdd = 6.2V + (AVDD[1:0] * 0.2V) , Avcl = -4.4V - (AVCL[1:0] * 0.2V) */ - ST7701_DSI(st7701, DSI_CMD2_BK1_PWCTLR2, - FIELD_PREP(DSI_CMD2_BK1_PWRCTRL2_AVDD_MASK, + ST7701_WRITE(st7701, ST7701_CMD2_BK1_PWCTLR2, + FIELD_PREP(ST7701_CMD2_BK1_PWRCTRL2_AVDD_MASK, DIV_ROUND_CLOSEST(desc->avdd_mv - 6200, 200)) | - FIELD_PREP(DSI_CMD2_BK1_PWRCTRL2_AVCL_MASK, + FIELD_PREP(ST7701_CMD2_BK1_PWRCTRL2_AVCL_MASK, DIV_ROUND_CLOSEST(-4400 - desc->avcl_mv, 200))); /* T2D = 0.2us * T2D[3:0] */ - ST7701_DSI(st7701, DSI_CMD2_BK1_SPD1, - DSI_CMD2_BK1_SPD1_ONES_MASK | - FIELD_PREP(DSI_CMD2_BK1_SPD1_T2D_MASK, + ST7701_WRITE(st7701, ST7701_CMD2_BK1_SPD1, + ST7701_CMD2_BK1_SPD1_ONES_MASK | + FIELD_PREP(ST7701_CMD2_BK1_SPD1_T2D_MASK, DIV_ROUND_CLOSEST(desc->t2d_ns, 200))); /* T3D = 4us + (0.8us * T3D[3:0]) */ - ST7701_DSI(st7701, DSI_CMD2_BK1_SPD2, - DSI_CMD2_BK1_SPD2_ONES_MASK | - FIELD_PREP(DSI_CMD2_BK1_SPD2_T3D_MASK, + ST7701_WRITE(st7701, ST7701_CMD2_BK1_SPD2, + ST7701_CMD2_BK1_SPD2_ONES_MASK | + FIELD_PREP(ST7701_CMD2_BK1_SPD2_T3D_MASK, DIV_ROUND_CLOSEST(desc->t3d_ns - 4000, 800))); - ST7701_DSI(st7701, DSI_CMD2_BK1_MIPISET1, - DSI_CMD2_BK1_MIPISET1_ONES | - (desc->eot_en ? DSI_CMD2_BK1_MIPISET1_EOT_EN : 0)); + ST7701_WRITE(st7701, ST7701_CMD2_BK1_MIPISET1, + ST7701_CMD2_BK1_MIPISET1_ONES | + (desc->eot_en ? ST7701_CMD2_BK1_MIPISET1_EOT_EN : 0)); } static void ts8550b_gip_sequence(struct st7701 *st7701) @@ -313,89 +325,89 @@ static void ts8550b_gip_sequence(struct st7701 *st7701) * ST7701_SPEC_V1.2 is unable to provide enough information above this * specific command sequence, so grab the same from vendor BSP driver. */ - ST7701_DSI(st7701, 0xE0, 0x00, 0x00, 0x02); - ST7701_DSI(st7701, 0xE1, 0x0B, 0x00, 0x0D, 0x00, 0x0C, 0x00, 0x0E, + ST7701_WRITE(st7701, 0xE0, 0x00, 0x00, 0x02); + ST7701_WRITE(st7701, 0xE1, 0x0B, 0x00, 0x0D, 0x00, 0x0C, 0x00, 0x0E, 0x00, 0x00, 0x44, 0x44); - ST7701_DSI(st7701, 0xE2, 0x33, 0x33, 0x44, 0x44, 0x64, 0x00, 0x66, + ST7701_WRITE(st7701, 0xE2, 0x33, 0x33, 0x44, 0x44, 0x64, 0x00, 0x66, 0x00, 0x65, 0x00, 0x67, 0x00, 0x00); - ST7701_DSI(st7701, 0xE3, 0x00, 0x00, 0x33, 0x33); - ST7701_DSI(st7701, 0xE4, 0x44, 0x44); - ST7701_DSI(st7701, 0xE5, 0x0C, 0x78, 0x3C, 0xA0, 0x0E, 0x78, 0x3C, + ST7701_WRITE(st7701, 0xE3, 0x00, 0x00, 0x33, 0x33); + ST7701_WRITE(st7701, 0xE4, 0x44, 0x44); + ST7701_WRITE(st7701, 0xE5, 0x0C, 0x78, 0x3C, 0xA0, 0x0E, 0x78, 0x3C, 0xA0, 0x10, 0x78, 0x3C, 0xA0, 0x12, 0x78, 0x3C, 0xA0); - ST7701_DSI(st7701, 0xE6, 0x00, 0x00, 0x33, 0x33); - ST7701_DSI(st7701, 0xE7, 0x44, 0x44); - ST7701_DSI(st7701, 0xE8, 0x0D, 0x78, 0x3C, 0xA0, 0x0F, 0x78, 0x3C, + ST7701_WRITE(st7701, 0xE6, 0x00, 0x00, 0x33, 0x33); + ST7701_WRITE(st7701, 0xE7, 0x44, 0x44); + ST7701_WRITE(st7701, 0xE8, 0x0D, 0x78, 0x3C, 0xA0, 0x0F, 0x78, 0x3C, 0xA0, 0x11, 0x78, 0x3C, 0xA0, 0x13, 0x78, 0x3C, 0xA0); - ST7701_DSI(st7701, 0xEB, 0x02, 0x02, 0x39, 0x39, 0xEE, 0x44, 0x00); - ST7701_DSI(st7701, 0xEC, 0x00, 0x00); - ST7701_DSI(st7701, 0xED, 0xFF, 0xF1, 0x04, 0x56, 0x72, 0x3F, 0xFF, + ST7701_WRITE(st7701, 0xEB, 0x02, 0x02, 0x39, 0x39, 0xEE, 0x44, 0x00); + ST7701_WRITE(st7701, 0xEC, 0x00, 0x00); + ST7701_WRITE(st7701, 0xED, 0xFF, 0xF1, 0x04, 0x56, 0x72, 0x3F, 0xFF, 0xFF, 0xFF, 0xFF, 0xF3, 0x27, 0x65, 0x40, 0x1F, 0xFF); } static void dmt028vghmcmi_1a_gip_sequence(struct st7701 *st7701) { - ST7701_DSI(st7701, 0xEE, 0x42); - ST7701_DSI(st7701, 0xE0, 0x00, 0x00, 0x02); + ST7701_WRITE(st7701, 0xEE, 0x42); + ST7701_WRITE(st7701, 0xE0, 0x00, 0x00, 0x02); - ST7701_DSI(st7701, 0xE1, + ST7701_WRITE(st7701, 0xE1, 0x04, 0xA0, 0x06, 0xA0, 0x05, 0xA0, 0x07, 0xA0, 0x00, 0x44, 0x44); - ST7701_DSI(st7701, 0xE2, + ST7701_WRITE(st7701, 0xE2, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00); - ST7701_DSI(st7701, 0xE3, + ST7701_WRITE(st7701, 0xE3, 0x00, 0x00, 0x22, 0x22); - ST7701_DSI(st7701, 0xE4, 0x44, 0x44); - ST7701_DSI(st7701, 0xE5, + ST7701_WRITE(st7701, 0xE4, 0x44, 0x44); + ST7701_WRITE(st7701, 0xE5, 0x0C, 0x90, 0xA0, 0xA0, 0x0E, 0x92, 0xA0, 0xA0, 0x08, 0x8C, 0xA0, 0xA0, 0x0A, 0x8E, 0xA0, 0xA0); - ST7701_DSI(st7701, 0xE6, + ST7701_WRITE(st7701, 0xE6, 0x00, 0x00, 0x22, 0x22); - ST7701_DSI(st7701, 0xE7, 0x44, 0x44); - ST7701_DSI(st7701, 0xE8, + ST7701_WRITE(st7701, 0xE7, 0x44, 0x44); + ST7701_WRITE(st7701, 0xE8, 0x0D, 0x91, 0xA0, 0xA0, 0x0F, 0x93, 0xA0, 0xA0, 0x09, 0x8D, 0xA0, 0xA0, 0x0B, 0x8F, 0xA0, 0xA0); - ST7701_DSI(st7701, 0xEB, + ST7701_WRITE(st7701, 0xEB, 0x00, 0x00, 0xE4, 0xE4, 0x44, 0x00, 0x00); - ST7701_DSI(st7701, 0xED, + ST7701_WRITE(st7701, 0xED, 0xFF, 0xF5, 0x47, 0x6F, 0x0B, 0xA1, 0xAB, 0xFF, 0xFF, 0xBA, 0x1A, 0xB0, 0xF6, 0x74, 0x5F, 0xFF); - ST7701_DSI(st7701, 0xEF, + ST7701_WRITE(st7701, 0xEF, 0x08, 0x08, 0x08, 0x40, 0x3F, 0x64); st7701_switch_cmd_bkx(st7701, false, 0); st7701_switch_cmd_bkx(st7701, true, 3); - ST7701_DSI(st7701, 0xE6, 0x7C); - ST7701_DSI(st7701, 0xE8, 0x00, 0x0E); + ST7701_WRITE(st7701, 0xE6, 0x7C); + ST7701_WRITE(st7701, 0xE8, 0x00, 0x0E); st7701_switch_cmd_bkx(st7701, false, 0); - ST7701_DSI(st7701, 0x11); + ST7701_WRITE(st7701, 0x11); msleep(120); st7701_switch_cmd_bkx(st7701, true, 3); - ST7701_DSI(st7701, 0xE8, 0x00, 0x0C); + ST7701_WRITE(st7701, 0xE8, 0x00, 0x0C); msleep(10); - ST7701_DSI(st7701, 0xE8, 0x00, 0x00); + ST7701_WRITE(st7701, 0xE8, 0x00, 0x00); st7701_switch_cmd_bkx(st7701, false, 0); - ST7701_DSI(st7701, 0x11); + ST7701_WRITE(st7701, 0x11); msleep(120); - ST7701_DSI(st7701, 0xE8, 0x00, 0x00); + ST7701_WRITE(st7701, 0xE8, 0x00, 0x00); st7701_switch_cmd_bkx(st7701, false, 0); - ST7701_DSI(st7701, 0x3A, 0x70); + ST7701_WRITE(st7701, 0x3A, 0x70); } static void kd50t048a_gip_sequence(struct st7701 *st7701) @@ -404,59 +416,108 @@ static void kd50t048a_gip_sequence(struct st7701 *st7701) * ST7701_SPEC_V1.2 is unable to provide enough information above this * specific command sequence, so grab the same from vendor BSP driver. */ - ST7701_DSI(st7701, 0xE0, 0x00, 0x00, 0x02); - ST7701_DSI(st7701, 0xE1, 0x08, 0x00, 0x0A, 0x00, 0x07, 0x00, 0x09, + ST7701_WRITE(st7701, 0xE0, 0x00, 0x00, 0x02); + ST7701_WRITE(st7701, 0xE1, 0x08, 0x00, 0x0A, 0x00, 0x07, 0x00, 0x09, 0x00, 0x00, 0x33, 0x33); - ST7701_DSI(st7701, 0xE2, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + ST7701_WRITE(st7701, 0xE2, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00); - ST7701_DSI(st7701, 0xE3, 0x00, 0x00, 0x33, 0x33); - ST7701_DSI(st7701, 0xE4, 0x44, 0x44); - ST7701_DSI(st7701, 0xE5, 0x0E, 0x60, 0xA0, 0xA0, 0x10, 0x60, 0xA0, + ST7701_WRITE(st7701, 0xE3, 0x00, 0x00, 0x33, 0x33); + ST7701_WRITE(st7701, 0xE4, 0x44, 0x44); + ST7701_WRITE(st7701, 0xE5, 0x0E, 0x60, 0xA0, 0xA0, 0x10, 0x60, 0xA0, 0xA0, 0x0A, 0x60, 0xA0, 0xA0, 0x0C, 0x60, 0xA0, 0xA0); - ST7701_DSI(st7701, 0xE6, 0x00, 0x00, 0x33, 0x33); - ST7701_DSI(st7701, 0xE7, 0x44, 0x44); - ST7701_DSI(st7701, 0xE8, 0x0D, 0x60, 0xA0, 0xA0, 0x0F, 0x60, 0xA0, + ST7701_WRITE(st7701, 0xE6, 0x00, 0x00, 0x33, 0x33); + ST7701_WRITE(st7701, 0xE7, 0x44, 0x44); + ST7701_WRITE(st7701, 0xE8, 0x0D, 0x60, 0xA0, 0xA0, 0x0F, 0x60, 0xA0, 0xA0, 0x09, 0x60, 0xA0, 0xA0, 0x0B, 0x60, 0xA0, 0xA0); - ST7701_DSI(st7701, 0xEB, 0x02, 0x01, 0xE4, 0xE4, 0x44, 0x00, 0x40); - ST7701_DSI(st7701, 0xEC, 0x02, 0x01); - ST7701_DSI(st7701, 0xED, 0xAB, 0x89, 0x76, 0x54, 0x01, 0xFF, 0xFF, + ST7701_WRITE(st7701, 0xEB, 0x02, 0x01, 0xE4, 0xE4, 0x44, 0x00, 0x40); + ST7701_WRITE(st7701, 0xEC, 0x02, 0x01); + ST7701_WRITE(st7701, 0xED, 0xAB, 0x89, 0x76, 0x54, 0x01, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x10, 0x45, 0x67, 0x98, 0xBA); } static void rg_arc_gip_sequence(struct st7701 *st7701) { st7701_switch_cmd_bkx(st7701, true, 3); - ST7701_DSI(st7701, 0xEF, 0x08); + ST7701_WRITE(st7701, 0xEF, 0x08); st7701_switch_cmd_bkx(st7701, true, 0); - ST7701_DSI(st7701, 0xC7, 0x04); - ST7701_DSI(st7701, 0xCC, 0x38); + ST7701_WRITE(st7701, 0xC7, 0x04); + ST7701_WRITE(st7701, 0xCC, 0x38); st7701_switch_cmd_bkx(st7701, true, 1); - ST7701_DSI(st7701, 0xB9, 0x10); - ST7701_DSI(st7701, 0xBC, 0x03); - ST7701_DSI(st7701, 0xC0, 0x89); - ST7701_DSI(st7701, 0xE0, 0x00, 0x00, 0x02); - ST7701_DSI(st7701, 0xE1, 0x04, 0x00, 0x00, 0x00, 0x05, 0x00, 0x00, + ST7701_WRITE(st7701, 0xB9, 0x10); + ST7701_WRITE(st7701, 0xBC, 0x03); + ST7701_WRITE(st7701, 0xC0, 0x89); + ST7701_WRITE(st7701, 0xE0, 0x00, 0x00, 0x02); + ST7701_WRITE(st7701, 0xE1, 0x04, 0x00, 0x00, 0x00, 0x05, 0x00, 0x00, 0x00, 0x00, 0x20, 0x20); - ST7701_DSI(st7701, 0xE2, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + ST7701_WRITE(st7701, 0xE2, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00); - ST7701_DSI(st7701, 0xE3, 0x00, 0x00, 0x33, 0x00); - ST7701_DSI(st7701, 0xE4, 0x22, 0x00); - ST7701_DSI(st7701, 0xE5, 0x04, 0x5C, 0xA0, 0xA0, 0x06, 0x5C, 0xA0, + ST7701_WRITE(st7701, 0xE3, 0x00, 0x00, 0x33, 0x00); + ST7701_WRITE(st7701, 0xE4, 0x22, 0x00); + ST7701_WRITE(st7701, 0xE5, 0x04, 0x5C, 0xA0, 0xA0, 0x06, 0x5C, 0xA0, 0xA0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00); - ST7701_DSI(st7701, 0xE6, 0x00, 0x00, 0x33, 0x00); - ST7701_DSI(st7701, 0xE7, 0x22, 0x00); - ST7701_DSI(st7701, 0xE8, 0x05, 0x5C, 0xA0, 0xA0, 0x07, 0x5C, 0xA0, + ST7701_WRITE(st7701, 0xE6, 0x00, 0x00, 0x33, 0x00); + ST7701_WRITE(st7701, 0xE7, 0x22, 0x00); + ST7701_WRITE(st7701, 0xE8, 0x05, 0x5C, 0xA0, 0xA0, 0x07, 0x5C, 0xA0, 0xA0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00); - ST7701_DSI(st7701, 0xEB, 0x02, 0x00, 0x40, 0x40, 0x00, 0x00, 0x00); - ST7701_DSI(st7701, 0xEC, 0x00, 0x00); - ST7701_DSI(st7701, 0xED, 0xFA, 0x45, 0x0B, 0xFF, 0xFF, 0xFF, 0xFF, + ST7701_WRITE(st7701, 0xEB, 0x02, 0x00, 0x40, 0x40, 0x00, 0x00, 0x00); + ST7701_WRITE(st7701, 0xEC, 0x00, 0x00); + ST7701_WRITE(st7701, 0xED, 0xFA, 0x45, 0x0B, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xB0, 0x54, 0xAF); - ST7701_DSI(st7701, 0xEF, 0x08, 0x08, 0x08, 0x45, 0x3F, 0x54); + ST7701_WRITE(st7701, 0xEF, 0x08, 0x08, 0x08, 0x45, 0x3F, 0x54); + st7701_switch_cmd_bkx(st7701, false, 0); + ST7701_WRITE(st7701, MIPI_DCS_SET_ADDRESS_MODE, 0x17); + ST7701_WRITE(st7701, MIPI_DCS_SET_PIXEL_FORMAT, 0x77); + ST7701_WRITE(st7701, MIPI_DCS_EXIT_SLEEP_MODE, 0x00); + msleep(120); +} + +static void rg28xx_gip_sequence(struct st7701 *st7701) +{ + st7701_switch_cmd_bkx(st7701, true, 3); + ST7701_WRITE(st7701, 0xEF, 0x08); + + st7701_switch_cmd_bkx(st7701, true, 0); + ST7701_WRITE(st7701, 0xC3, 0x02, 0x10, 0x02); + ST7701_WRITE(st7701, 0xC7, 0x04); + ST7701_WRITE(st7701, 0xCC, 0x10); + + st7701_switch_cmd_bkx(st7701, true, 1); + ST7701_WRITE(st7701, 0xEE, 0x42); + ST7701_WRITE(st7701, 0xE0, 0x00, 0x00, 0x02); + + ST7701_WRITE(st7701, 0xE1, 0x04, 0xA0, 0x06, 0xA0, 0x05, 0xA0, 0x07, 0xA0, + 0x00, 0x44, 0x44); + ST7701_WRITE(st7701, 0xE2, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00); + ST7701_WRITE(st7701, 0xE3, 0x00, 0x00, 0x22, 0x22); + ST7701_WRITE(st7701, 0xE4, 0x44, 0x44); + ST7701_WRITE(st7701, 0xE5, 0x0C, 0x90, 0xA0, 0xA0, 0x0E, 0x92, 0xA0, 0xA0, + 0x08, 0x8C, 0xA0, 0xA0, 0x0A, 0x8E, 0xA0, 0xA0); + ST7701_WRITE(st7701, 0xE6, 0x00, 0x00, 0x22, 0x22); + ST7701_WRITE(st7701, 0xE7, 0x44, 0x44); + ST7701_WRITE(st7701, 0xE8, 0x0D, 0x91, 0xA0, 0xA0, 0x0F, 0x93, 0xA0, 0xA0, + 0x09, 0x8D, 0xA0, 0xA0, 0x0B, 0x8F, 0xA0, 0xA0); + ST7701_WRITE(st7701, 0xEB, 0x00, 0x00, 0xE4, 0xE4, 0x44, 0x00, 0x40); + ST7701_WRITE(st7701, 0xED, 0xFF, 0xF5, 0x47, 0x6F, 0x0B, 0xA1, 0xBA, 0xFF, + 0xFF, 0xAB, 0x1A, 0xB0, 0xF6, 0x74, 0x5F, 0xFF); + ST7701_WRITE(st7701, 0xEF, 0x08, 0x08, 0x08, 0x45, 0x3F, 0x54); + st7701_switch_cmd_bkx(st7701, false, 0); - ST7701_DSI(st7701, MIPI_DCS_SET_ADDRESS_MODE, 0x17); - ST7701_DSI(st7701, MIPI_DCS_SET_PIXEL_FORMAT, 0x77); - ST7701_DSI(st7701, MIPI_DCS_EXIT_SLEEP_MODE, 0x00); + + st7701_switch_cmd_bkx(st7701, true, 3); + ST7701_WRITE(st7701, 0xE6, 0x16); + ST7701_WRITE(st7701, 0xE8, 0x00, 0x0E); + + st7701_switch_cmd_bkx(st7701, false, 0); + ST7701_WRITE(st7701, MIPI_DCS_SET_ADDRESS_MODE, 0x10); + ST7701_WRITE(st7701, MIPI_DCS_EXIT_SLEEP_MODE); msleep(120); + + st7701_switch_cmd_bkx(st7701, true, 3); + ST7701_WRITE(st7701, 0xE8, 0x00, 0x0C); + msleep(10); + ST7701_WRITE(st7701, 0xE8, 0x00, 0x00); + st7701_switch_cmd_bkx(st7701, false, 0); } static int st7701_prepare(struct drm_panel *panel) @@ -490,7 +551,7 @@ static int st7701_enable(struct drm_panel *panel) { struct st7701 *st7701 = panel_to_st7701(panel); - ST7701_DSI(st7701, MIPI_DCS_SET_DISPLAY_ON, 0x00); + ST7701_WRITE(st7701, MIPI_DCS_SET_DISPLAY_ON, 0x00); return 0; } @@ -499,7 +560,7 @@ static int st7701_disable(struct drm_panel *panel) { struct st7701 *st7701 = panel_to_st7701(panel); - ST7701_DSI(st7701, MIPI_DCS_SET_DISPLAY_OFF, 0x00); + ST7701_WRITE(st7701, MIPI_DCS_SET_DISPLAY_OFF, 0x00); return 0; } @@ -508,7 +569,7 @@ static int st7701_unprepare(struct drm_panel *panel) { struct st7701 *st7701 = panel_to_st7701(panel); - ST7701_DSI(st7701, MIPI_DCS_ENTER_SLEEP_MODE, 0x00); + ST7701_WRITE(st7701, MIPI_DCS_ENTER_SLEEP_MODE, 0x00); msleep(st7701->sleep_delay); @@ -539,7 +600,7 @@ static int st7701_get_modes(struct drm_panel *panel, mode = drm_mode_duplicate(connector->dev, desc_mode); if (!mode) { - dev_err(&st7701->dsi->dev, "failed to add mode %ux%u@%u\n", + dev_err(panel->dev, "failed to add mode %ux%u@%u\n", desc_mode->hdisplay, desc_mode->vdisplay, drm_mode_vrefresh(desc_mode)); return -ENOMEM; @@ -602,62 +663,62 @@ static const struct st7701_panel_desc ts8550b_desc = { .panel_sleep_delay = 80, /* panel need extra 80ms for sleep out cmd */ .pv_gamma = { - CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) | - CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC0_MASK, 0), - CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) | - CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC4_MASK, 0xe), - CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) | - CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC8_MASK, 0x15), - CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC16_MASK, 0xf), - - CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) | - CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC24_MASK, 0x11), - CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC52_MASK, 0x8), - CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC80_MASK, 0x8), - CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC108_MASK, 0x8), - - CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC147_MASK, 0x8), - CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC175_MASK, 0x23), - CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC203_MASK, 0x4), - CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) | - CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC231_MASK, 0x13), - - CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC239_MASK, 0x12), - CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) | - CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC247_MASK, 0x2b), - CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) | - CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC251_MASK, 0x34), - CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) | - CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC255_MASK, 0x1f) + CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_AJ_MASK, 0) | + CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC0_MASK, 0), + CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_AJ_MASK, 0) | + CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC4_MASK, 0xe), + CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_AJ_MASK, 0) | + CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC8_MASK, 0x15), + CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC16_MASK, 0xf), + + CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_AJ_MASK, 0) | + CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC24_MASK, 0x11), + CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC52_MASK, 0x8), + CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC80_MASK, 0x8), + CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC108_MASK, 0x8), + + CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC147_MASK, 0x8), + CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC175_MASK, 0x23), + CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC203_MASK, 0x4), + CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_AJ_MASK, 0) | + CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC231_MASK, 0x13), + + CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC239_MASK, 0x12), + CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_AJ_MASK, 0) | + CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC247_MASK, 0x2b), + CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_AJ_MASK, 0) | + CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC251_MASK, 0x34), + CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_AJ_MASK, 0) | + CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC255_MASK, 0x1f) }, .nv_gamma = { - CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) | - CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC0_MASK, 0), - CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) | - CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC4_MASK, 0xe), - CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0x2) | - CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC8_MASK, 0x15), - CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC16_MASK, 0xf), - - CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) | - CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC24_MASK, 0x13), - CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC52_MASK, 0x7), - CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC80_MASK, 0x9), - CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC108_MASK, 0x8), - - CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC147_MASK, 0x8), - CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC175_MASK, 0x22), - CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC203_MASK, 0x4), - CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) | - CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC231_MASK, 0x10), - - CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC239_MASK, 0xe), - CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) | - CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC247_MASK, 0x2c), - CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) | - CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC251_MASK, 0x34), - CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) | - CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC255_MASK, 0x1f) + CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_AJ_MASK, 0) | + CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC0_MASK, 0), + CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_AJ_MASK, 0) | + CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC4_MASK, 0xe), + CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_AJ_MASK, 0x2) | + CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC8_MASK, 0x15), + CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC16_MASK, 0xf), + + CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_AJ_MASK, 0) | + CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC24_MASK, 0x13), + CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC52_MASK, 0x7), + CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC80_MASK, 0x9), + CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC108_MASK, 0x8), + + CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC147_MASK, 0x8), + CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC175_MASK, 0x22), + CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC203_MASK, 0x4), + CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_AJ_MASK, 0) | + CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC231_MASK, 0x10), + + CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC239_MASK, 0xe), + CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_AJ_MASK, 0) | + CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC247_MASK, 0x2c), + CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_AJ_MASK, 0) | + CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC251_MASK, 0x34), + CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_AJ_MASK, 0) | + CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC255_MASK, 0x1f) }, .nlinv = 7, .vop_uv = 4400000, @@ -703,62 +764,62 @@ static const struct st7701_panel_desc dmt028vghmcmi_1a_desc = { .panel_sleep_delay = 5, /* panel need extra 5ms for sleep out cmd */ .pv_gamma = { - CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) | - CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC0_MASK, 0), - CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) | - CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC4_MASK, 0x10), - CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) | - CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC8_MASK, 0x17), - CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC16_MASK, 0xd), - - CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) | - CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC24_MASK, 0x11), - CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC52_MASK, 0x6), - CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC80_MASK, 0x5), - CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC108_MASK, 0x8), - - CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC147_MASK, 0x7), - CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC175_MASK, 0x1f), - CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC203_MASK, 0x4), - CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) | - CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC231_MASK, 0x11), - - CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC239_MASK, 0xe), - CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) | - CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC247_MASK, 0x29), - CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) | - CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC251_MASK, 0x30), - CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) | - CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC255_MASK, 0x1f) + CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_AJ_MASK, 0) | + CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC0_MASK, 0), + CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_AJ_MASK, 0) | + CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC4_MASK, 0x10), + CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_AJ_MASK, 0) | + CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC8_MASK, 0x17), + CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC16_MASK, 0xd), + + CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_AJ_MASK, 0) | + CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC24_MASK, 0x11), + CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC52_MASK, 0x6), + CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC80_MASK, 0x5), + CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC108_MASK, 0x8), + + CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC147_MASK, 0x7), + CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC175_MASK, 0x1f), + CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC203_MASK, 0x4), + CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_AJ_MASK, 0) | + CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC231_MASK, 0x11), + + CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC239_MASK, 0xe), + CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_AJ_MASK, 0) | + CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC247_MASK, 0x29), + CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_AJ_MASK, 0) | + CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC251_MASK, 0x30), + CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_AJ_MASK, 0) | + CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC255_MASK, 0x1f) }, .nv_gamma = { - CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) | - CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC0_MASK, 0), - CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) | - CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC4_MASK, 0xd), - CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) | - CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC8_MASK, 0x14), - CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC16_MASK, 0xe), - - CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) | - CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC24_MASK, 0x11), - CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC52_MASK, 0x6), - CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC80_MASK, 0x4), - CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC108_MASK, 0x8), - - CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC147_MASK, 0x8), - CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC175_MASK, 0x20), - CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC203_MASK, 0x5), - CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) | - CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC231_MASK, 0x13), - - CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC239_MASK, 0x13), - CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) | - CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC247_MASK, 0x26), - CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) | - CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC251_MASK, 0x30), - CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) | - CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC255_MASK, 0x1f) + CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_AJ_MASK, 0) | + CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC0_MASK, 0), + CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_AJ_MASK, 0) | + CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC4_MASK, 0xd), + CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_AJ_MASK, 0) | + CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC8_MASK, 0x14), + CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC16_MASK, 0xe), + + CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_AJ_MASK, 0) | + CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC24_MASK, 0x11), + CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC52_MASK, 0x6), + CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC80_MASK, 0x4), + CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC108_MASK, 0x8), + + CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC147_MASK, 0x8), + CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC175_MASK, 0x20), + CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC203_MASK, 0x5), + CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_AJ_MASK, 0) | + CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC231_MASK, 0x13), + + CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC239_MASK, 0x13), + CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_AJ_MASK, 0) | + CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC247_MASK, 0x26), + CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_AJ_MASK, 0) | + CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC251_MASK, 0x30), + CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_AJ_MASK, 0) | + CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC255_MASK, 0x1f) }, .nlinv = 1, .vop_uv = 4800000, @@ -802,62 +863,62 @@ static const struct st7701_panel_desc kd50t048a_desc = { .panel_sleep_delay = 0, .pv_gamma = { - CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) | - CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC0_MASK, 0), - CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) | - CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC4_MASK, 0xd), - CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) | - CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC8_MASK, 0x14), - CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC16_MASK, 0xd), - - CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) | - CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC24_MASK, 0x10), - CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC52_MASK, 0x5), - CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC80_MASK, 0x2), - CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC108_MASK, 0x8), - - CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC147_MASK, 0x8), - CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC175_MASK, 0x1e), - CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC203_MASK, 0x5), - CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) | - CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC231_MASK, 0x13), - - CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC239_MASK, 0x11), - CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 2) | - CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC247_MASK, 0x23), - CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) | - CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC251_MASK, 0x29), - CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) | - CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC255_MASK, 0x18) + CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_AJ_MASK, 0) | + CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC0_MASK, 0), + CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_AJ_MASK, 0) | + CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC4_MASK, 0xd), + CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_AJ_MASK, 0) | + CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC8_MASK, 0x14), + CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC16_MASK, 0xd), + + CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_AJ_MASK, 0) | + CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC24_MASK, 0x10), + CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC52_MASK, 0x5), + CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC80_MASK, 0x2), + CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC108_MASK, 0x8), + + CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC147_MASK, 0x8), + CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC175_MASK, 0x1e), + CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC203_MASK, 0x5), + CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_AJ_MASK, 0) | + CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC231_MASK, 0x13), + + CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC239_MASK, 0x11), + CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_AJ_MASK, 2) | + CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC247_MASK, 0x23), + CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_AJ_MASK, 0) | + CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC251_MASK, 0x29), + CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_AJ_MASK, 0) | + CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC255_MASK, 0x18) }, .nv_gamma = { - CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) | - CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC0_MASK, 0), - CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) | - CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC4_MASK, 0xc), - CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) | - CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC8_MASK, 0x14), - CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC16_MASK, 0xc), - - CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) | - CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC24_MASK, 0x10), - CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC52_MASK, 0x5), - CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC80_MASK, 0x3), - CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC108_MASK, 0x8), - - CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC147_MASK, 0x7), - CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC175_MASK, 0x20), - CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC203_MASK, 0x5), - CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) | - CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC231_MASK, 0x13), - - CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC239_MASK, 0x11), - CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 2) | - CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC247_MASK, 0x24), - CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) | - CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC251_MASK, 0x29), - CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) | - CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC255_MASK, 0x18) + CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_AJ_MASK, 0) | + CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC0_MASK, 0), + CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_AJ_MASK, 0) | + CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC4_MASK, 0xc), + CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_AJ_MASK, 0) | + CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC8_MASK, 0x14), + CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC16_MASK, 0xc), + + CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_AJ_MASK, 0) | + CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC24_MASK, 0x10), + CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC52_MASK, 0x5), + CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC80_MASK, 0x3), + CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC108_MASK, 0x8), + + CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC147_MASK, 0x7), + CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC175_MASK, 0x20), + CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC203_MASK, 0x5), + CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_AJ_MASK, 0) | + CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC231_MASK, 0x13), + + CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC239_MASK, 0x11), + CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_AJ_MASK, 2) | + CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC247_MASK, 0x24), + CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_AJ_MASK, 0) | + CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC251_MASK, 0x29), + CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_AJ_MASK, 0) | + CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC255_MASK, 0x18) }, .nlinv = 1, .vop_uv = 4887500, @@ -901,62 +962,62 @@ static const struct st7701_panel_desc rg_arc_desc = { .panel_sleep_delay = 80, .pv_gamma = { - CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0x01) | - CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC0_MASK, 0), - CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) | - CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC4_MASK, 0x16), - CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) | - CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC8_MASK, 0x1d), - CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC16_MASK, 0x0e), - - CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) | - CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC24_MASK, 0x12), - CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC52_MASK, 0x06), - CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC80_MASK, 0x0c), - CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC108_MASK, 0x0a), - - CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC147_MASK, 0x09), - CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC175_MASK, 0x25), - CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC203_MASK, 0x00), - CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) | - CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC231_MASK, 0x03), - - CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC239_MASK, 0x00), - CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) | - CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC247_MASK, 0x3f), - CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) | - CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC251_MASK, 0x3f), - CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) | - CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC255_MASK, 0x1c) + CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_AJ_MASK, 0x01) | + CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC0_MASK, 0), + CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_AJ_MASK, 0) | + CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC4_MASK, 0x16), + CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_AJ_MASK, 0) | + CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC8_MASK, 0x1d), + CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC16_MASK, 0x0e), + + CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_AJ_MASK, 0) | + CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC24_MASK, 0x12), + CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC52_MASK, 0x06), + CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC80_MASK, 0x0c), + CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC108_MASK, 0x0a), + + CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC147_MASK, 0x09), + CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC175_MASK, 0x25), + CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC203_MASK, 0x00), + CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_AJ_MASK, 0) | + CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC231_MASK, 0x03), + + CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC239_MASK, 0x00), + CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_AJ_MASK, 0) | + CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC247_MASK, 0x3f), + CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_AJ_MASK, 0) | + CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC251_MASK, 0x3f), + CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_AJ_MASK, 0) | + CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC255_MASK, 0x1c) }, .nv_gamma = { - CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0x01) | - CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC0_MASK, 0), - CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) | - CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC4_MASK, 0x16), - CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) | - CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC8_MASK, 0x1e), - CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC16_MASK, 0x0e), - - CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) | - CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC24_MASK, 0x11), - CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC52_MASK, 0x06), - CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC80_MASK, 0x0c), - CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC108_MASK, 0x08), - - CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC147_MASK, 0x09), - CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC175_MASK, 0x26), - CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC203_MASK, 0x00), - CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) | - CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC231_MASK, 0x15), - - CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC239_MASK, 0x00), - CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) | - CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC247_MASK, 0x3f), - CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) | - CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC251_MASK, 0x3f), - CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) | - CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC255_MASK, 0x1c) + CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_AJ_MASK, 0x01) | + CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC0_MASK, 0), + CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_AJ_MASK, 0) | + CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC4_MASK, 0x16), + CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_AJ_MASK, 0) | + CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC8_MASK, 0x1e), + CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC16_MASK, 0x0e), + + CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_AJ_MASK, 0) | + CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC24_MASK, 0x11), + CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC52_MASK, 0x06), + CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC80_MASK, 0x0c), + CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC108_MASK, 0x08), + + CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC147_MASK, 0x09), + CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC175_MASK, 0x26), + CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC203_MASK, 0x00), + CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_AJ_MASK, 0) | + CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC231_MASK, 0x15), + + CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC239_MASK, 0x00), + CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_AJ_MASK, 0) | + CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC247_MASK, 0x3f), + CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_AJ_MASK, 0) | + CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC251_MASK, 0x3f), + CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_AJ_MASK, 0) | + CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC255_MASK, 0x1c) }, .nlinv = 0, .vop_uv = 4500000, @@ -974,42 +1035,148 @@ static const struct st7701_panel_desc rg_arc_desc = { .gip_sequence = rg_arc_gip_sequence, }; -static int st7701_dsi_probe(struct mipi_dsi_device *dsi) +static const struct drm_display_mode rg28xx_mode = { + .clock = 22325, + + .hdisplay = 480, + .hsync_start = 480 + 40, + .hsync_end = 480 + 40 + 4, + .htotal = 480 + 40 + 4 + 20, + + .vdisplay = 640, + .vsync_start = 640 + 2, + .vsync_end = 640 + 2 + 40, + .vtotal = 640 + 2 + 40 + 16, + + .width_mm = 44, + .height_mm = 58, + + .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, + + .type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED, +}; + +static const struct st7701_panel_desc rg28xx_desc = { + .mode = &rg28xx_mode, + + .panel_sleep_delay = 80, + + .pv_gamma = { + CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_AJ_MASK, 0) | + CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC0_MASK, 0), + CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_AJ_MASK, 0) | + CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC4_MASK, 0x10), + CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_AJ_MASK, 0) | + CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC8_MASK, 0x17), + CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC16_MASK, 0xd), + + CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_AJ_MASK, 0) | + CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC24_MASK, 0x11), + CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC52_MASK, 0x6), + CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC80_MASK, 0x5), + CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC108_MASK, 0x8), + + CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC147_MASK, 0x7), + CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC175_MASK, 0x1f), + CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC203_MASK, 0x4), + CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_AJ_MASK, 0) | + CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC231_MASK, 0x11), + + CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC239_MASK, 0xe), + CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_AJ_MASK, 0) | + CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC247_MASK, 0x29), + CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_AJ_MASK, 0) | + CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC251_MASK, 0x30), + CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_AJ_MASK, 0) | + CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC255_MASK, 0x1f) + }, + .nv_gamma = { + CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_AJ_MASK, 0) | + CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC0_MASK, 0), + CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_AJ_MASK, 0) | + CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC4_MASK, 0xd), + CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_AJ_MASK, 0) | + CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC8_MASK, 0x14), + CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC16_MASK, 0xe), + + CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_AJ_MASK, 0) | + CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC24_MASK, 0x11), + CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC52_MASK, 0x6), + CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC80_MASK, 0x4), + CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC108_MASK, 0x8), + + CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC147_MASK, 0x8), + CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC175_MASK, 0x20), + CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC203_MASK, 0x5), + CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_AJ_MASK, 0) | + CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC231_MASK, 0x13), + + CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC239_MASK, 0x13), + CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_AJ_MASK, 0) | + CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC247_MASK, 0x26), + CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_AJ_MASK, 0) | + CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC251_MASK, 0x30), + CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_AJ_MASK, 0) | + CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC255_MASK, 0x1f) + }, + .nlinv = 7, + .vop_uv = 4800000, + .vcom_uv = 1512500, + .vgh_mv = 15000, + .vgl_mv = -11730, + .avdd_mv = 6600, + .avcl_mv = -4400, + .gamma_op_bias = OP_BIAS_MIDDLE, + .input_op_bias = OP_BIAS_MIN, + .output_op_bias = OP_BIAS_MIN, + .t2d_ns = 1600, + .t3d_ns = 10400, + .eot_en = true, + .gip_sequence = rg28xx_gip_sequence, +}; + +static void st7701_cleanup(void *data) +{ + struct st7701 *st7701 = (struct st7701 *)data; + + drm_panel_remove(&st7701->panel); + drm_panel_disable(&st7701->panel); + drm_panel_unprepare(&st7701->panel); +} + +static int st7701_probe(struct device *dev, int connector_type) { const struct st7701_panel_desc *desc; struct st7701 *st7701; int ret; - st7701 = devm_kzalloc(&dsi->dev, sizeof(*st7701), GFP_KERNEL); + st7701 = devm_kzalloc(dev, sizeof(*st7701), GFP_KERNEL); if (!st7701) return -ENOMEM; - desc = of_device_get_match_data(&dsi->dev); - dsi->mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | - MIPI_DSI_MODE_LPM | MIPI_DSI_CLOCK_NON_CONTINUOUS; - dsi->format = desc->format; - dsi->lanes = desc->lanes; + desc = of_device_get_match_data(dev); + if (!desc) + return -ENODEV; st7701->supplies[0].supply = "VCC"; st7701->supplies[1].supply = "IOVCC"; - ret = devm_regulator_bulk_get(&dsi->dev, ARRAY_SIZE(st7701->supplies), + ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(st7701->supplies), st7701->supplies); if (ret < 0) return ret; - st7701->reset = devm_gpiod_get(&dsi->dev, "reset", GPIOD_OUT_LOW); + st7701->reset = devm_gpiod_get(dev, "reset", GPIOD_OUT_LOW); if (IS_ERR(st7701->reset)) { - dev_err(&dsi->dev, "Couldn't get our reset GPIO\n"); + dev_err(dev, "Couldn't get our reset GPIO\n"); return PTR_ERR(st7701->reset); } - ret = of_drm_get_panel_orientation(dsi->dev.of_node, &st7701->orientation); + ret = of_drm_get_panel_orientation(dev->of_node, &st7701->orientation); if (ret < 0) - return dev_err_probe(&dsi->dev, ret, "Failed to get orientation\n"); + return dev_err_probe(dev, ret, "Failed to get orientation\n"); - drm_panel_init(&st7701->panel, &dsi->dev, &st7701_funcs, - DRM_MODE_CONNECTOR_DSI); + drm_panel_init(&st7701->panel, dev, &st7701_funcs, connector_type); /** * Once sleep out has been issued, ST7701 IC required to wait 120ms @@ -1028,48 +1195,143 @@ static int st7701_dsi_probe(struct mipi_dsi_device *dsi) drm_panel_add(&st7701->panel); - mipi_dsi_set_drvdata(dsi, st7701); - st7701->dsi = dsi; + dev_set_drvdata(dev, st7701); st7701->desc = desc; - ret = mipi_dsi_attach(dsi); - if (ret) - goto err_attach; + return devm_add_action_or_reset(dev, st7701_cleanup, st7701); +} + +static int st7701_dsi_probe(struct mipi_dsi_device *dsi) +{ + struct st7701 *st7701; + int err; + + err = st7701_probe(&dsi->dev, DRM_MODE_CONNECTOR_DSI); + if (err) + return err; + + st7701 = dev_get_drvdata(&dsi->dev); + st7701->dsi = dsi; + st7701->write_command = st7701_dsi_write; + + if (!st7701->desc->lanes) + return dev_err_probe(&dsi->dev, -EINVAL, "This panel is not for MIPI DSI\n"); + + dsi->mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | + MIPI_DSI_MODE_LPM | MIPI_DSI_CLOCK_NON_CONTINUOUS; + dsi->format = st7701->desc->format; + dsi->lanes = st7701->desc->lanes; + + err = mipi_dsi_attach(dsi); + if (err) + return dev_err_probe(&dsi->dev, err, "Failed to init MIPI DSI\n"); return 0; +} -err_attach: - drm_panel_remove(&st7701->panel); - return ret; +static int st7701_spi_probe(struct spi_device *spi) +{ + struct st7701 *st7701; + struct gpio_desc *dc; + int err; + + err = st7701_probe(&spi->dev, DRM_MODE_CONNECTOR_DPI); + if (err) + return err; + + st7701 = dev_get_drvdata(&spi->dev); + st7701->write_command = st7701_dbi_write; + + dc = devm_gpiod_get_optional(&spi->dev, "dc", GPIOD_OUT_LOW); + if (IS_ERR(dc)) + return dev_err_probe(&spi->dev, PTR_ERR(dc), "Failed to get GPIO for D/CX\n"); + + err = mipi_dbi_spi_init(spi, &st7701->dbi, dc); + if (err) + return dev_err_probe(&spi->dev, err, "Failed to init MIPI DBI\n"); + st7701->dbi.read_commands = NULL; + + return 0; } static void st7701_dsi_remove(struct mipi_dsi_device *dsi) { - struct st7701 *st7701 = mipi_dsi_get_drvdata(dsi); - mipi_dsi_detach(dsi); - drm_panel_remove(&st7701->panel); } -static const struct of_device_id st7701_of_match[] = { +static const struct of_device_id st7701_dsi_of_match[] = { { .compatible = "anbernic,rg-arc-panel", .data = &rg_arc_desc }, { .compatible = "densitron,dmt028vghmcmi-1a", .data = &dmt028vghmcmi_1a_desc }, { .compatible = "elida,kd50t048a", .data = &kd50t048a_desc }, { .compatible = "techstar,ts8550b", .data = &ts8550b_desc }, { } }; -MODULE_DEVICE_TABLE(of, st7701_of_match); +MODULE_DEVICE_TABLE(of, st7701_dsi_of_match); + +static const struct of_device_id st7701_spi_of_match[] = { + { .compatible = "anbernic,rg28xx-panel", .data = &rg28xx_desc }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, st7701_spi_of_match); + +static const struct spi_device_id st7701_spi_ids[] = { + { "rg28xx-panel" }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(spi, st7701_spi_ids); static struct mipi_dsi_driver st7701_dsi_driver = { .probe = st7701_dsi_probe, .remove = st7701_dsi_remove, .driver = { .name = "st7701", - .of_match_table = st7701_of_match, + .of_match_table = st7701_dsi_of_match, }, }; -module_mipi_dsi_driver(st7701_dsi_driver); + +static struct spi_driver st7701_spi_driver = { + .probe = st7701_spi_probe, + .id_table = st7701_spi_ids, + .driver = { + .name = "st7701", + .of_match_table = st7701_spi_of_match, + }, +}; + +static int __init st7701_driver_init(void) +{ + int err; + + if (IS_ENABLED(CONFIG_SPI)) { + err = spi_register_driver(&st7701_spi_driver); + if (err) + return err; + } + + if (IS_ENABLED(CONFIG_DRM_MIPI_DSI)) { + err = mipi_dsi_driver_register(&st7701_dsi_driver); + if (err) { + if (IS_ENABLED(CONFIG_SPI)) + spi_unregister_driver(&st7701_spi_driver); + return err; + } + } + + return 0; +} +module_init(st7701_driver_init); + +static void __exit st7701_driver_exit(void) +{ + if (IS_ENABLED(CONFIG_DRM_MIPI_DSI)) + mipi_dsi_driver_unregister(&st7701_dsi_driver); + + if (IS_ENABLED(CONFIG_SPI)) + spi_unregister_driver(&st7701_spi_driver); +} +module_exit(st7701_driver_exit); MODULE_AUTHOR("Jagan Teki <jagan@amarulasolutions.com>"); +MODULE_AUTHOR("Hironori KIKUCHI <kikuchan98@gmail.com>"); MODULE_DESCRIPTION("Sitronix ST7701 LCD Panel Driver"); MODULE_LICENSE("GPL"); diff --git a/drivers/gpu/drm/panel/panel-sony-acx565akm.c b/drivers/gpu/drm/panel/panel-sony-acx565akm.c index 73ba93ff00fe..217f03569494 100644 --- a/drivers/gpu/drm/panel/panel-sony-acx565akm.c +++ b/drivers/gpu/drm/panel/panel-sony-acx565akm.c @@ -342,7 +342,7 @@ static const struct backlight_ops acx565akm_bl_ops = { static int acx565akm_backlight_init(struct acx565akm_panel *lcd) { struct backlight_properties props = { - .power = FB_BLANK_UNBLANK, + .power = BACKLIGHT_POWER_ON, .type = BACKLIGHT_RAW, }; int ret; diff --git a/drivers/gpu/drm/panel/panel-sony-tulip-truly-nt35521.c b/drivers/gpu/drm/panel/panel-sony-tulip-truly-nt35521.c index f2198fa29735..104b2290560e 100644 --- a/drivers/gpu/drm/panel/panel-sony-tulip-truly-nt35521.c +++ b/drivers/gpu/drm/panel/panel-sony-tulip-truly-nt35521.c @@ -25,6 +25,12 @@ struct truly_nt35521 { struct gpio_desc *blen_gpio; }; +#define NT35521_DCS_SWITCH_PAGE 0xf0 + +#define nt35521_switch_page(dsi_ctx, page) \ + mipi_dsi_dcs_write_seq_multi(dsi_ctx, NT35521_DCS_SWITCH_PAGE, \ + 0x55, 0xaa, 0x52, 0x08, (page)) + static inline struct truly_nt35521 *to_truly_nt35521(struct drm_panel *panel) { @@ -48,7 +54,7 @@ static int truly_nt35521_on(struct truly_nt35521 *ctx) dsi->mode_flags |= MIPI_DSI_MODE_LPM; - mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xf0, 0x55, 0xaa, 0x52, 0x08, 0x00); + nt35521_switch_page(&dsi_ctx, 0x00); mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xff, 0xaa, 0x55, 0xa5, 0x80); mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x6f, 0x11, 0x00); mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xf7, 0x20, 0x00); @@ -59,7 +65,8 @@ static int truly_nt35521_on(struct truly_nt35521 *ctx) mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xbb, 0x11, 0x11); mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xbc, 0x00, 0x00); mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xb6, 0x02); - mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xf0, 0x55, 0xaa, 0x52, 0x08, 0x01); + + nt35521_switch_page(&dsi_ctx, 0x01); mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xb0, 0x09, 0x09); mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xb1, 0x09, 0x09); mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xbc, 0x8c, 0x00); @@ -71,7 +78,8 @@ static int truly_nt35521_on(struct truly_nt35521 *ctx) mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xb4, 0x25, 0x25); mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xb9, 0x43, 0x43); mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xba, 0x24, 0x24); - mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xf0, 0x55, 0xaa, 0x52, 0x08, 0x02); + + nt35521_switch_page(&dsi_ctx, 0x02); mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xee, 0x03); mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xb0, 0x00, 0xb2, 0x00, 0xb3, 0x00, 0xb6, 0x00, 0xc3, @@ -103,7 +111,8 @@ static int truly_nt35521_on(struct truly_nt35521 *ctx) 0x02, 0x93, 0x02, 0xcd, 0x02, 0xf6, 0x03, 0x31, 0x03, 0x6c, 0x03, 0xe9, 0x03, 0xef, 0x03, 0xf4); mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xbb, 0x03, 0xf6, 0x03, 0xf7); - mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xf0, 0x55, 0xaa, 0x52, 0x08, 0x03); + + nt35521_switch_page(&dsi_ctx, 0x03); mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xb0, 0x22, 0x00); mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xb1, 0x22, 0x00); mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xb2, 0x05, 0x00, 0x60, 0x00, 0x00); @@ -122,7 +131,8 @@ static int truly_nt35521_on(struct truly_nt35521 *ctx) mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xc5, 0xc0); mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xc6, 0x00); mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xc7, 0x00); - mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xf0, 0x55, 0xaa, 0x52, 0x08, 0x05); + + nt35521_switch_page(&dsi_ctx, 0x05); mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xb0, 0x17, 0x06); mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xb1, 0x17, 0x06); mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xb2, 0x17, 0x06); @@ -178,7 +188,8 @@ static int truly_nt35521_on(struct truly_nt35521 *ctx) mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xeb, 0x00); mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xec, 0x00); mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xed, 0x30); - mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xf0, 0x55, 0xaa, 0x52, 0x08, 0x06); + + nt35521_switch_page(&dsi_ctx, 0x06); mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xb0, 0x31, 0x31); mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xb1, 0x31, 0x31); mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xb2, 0x2d, 0x2e); @@ -235,10 +246,12 @@ static int truly_nt35521_on(struct truly_nt35521 *ctx) mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x6f, 0x11); mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xf3, 0x01); mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x35, 0x00); - mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xf0, 0x55, 0xaa, 0x52, 0x08, 0x00); + + nt35521_switch_page(&dsi_ctx, 0x00); mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xd9, 0x02, 0x03, 0x00); mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xf0, 0x55, 0xaa, 0x52, 0x00, 0x00); - mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xf0, 0x55, 0xaa, 0x52, 0x08, 0x00); + + nt35521_switch_page(&dsi_ctx, 0x00); mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xb1, 0x6c, 0x21); mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0xf0, 0x55, 0xaa, 0x52, 0x00, 0x00); mipi_dsi_generic_write_seq_multi(&dsi_ctx, 0x35, 0x00); diff --git a/drivers/gpu/drm/panel/panel-startek-kd070fhfid015.c b/drivers/gpu/drm/panel/panel-startek-kd070fhfid015.c index 0156689f41cd..c0c95355b743 100644 --- a/drivers/gpu/drm/panel/panel-startek-kd070fhfid015.c +++ b/drivers/gpu/drm/panel/panel-startek-kd070fhfid015.c @@ -24,10 +24,10 @@ #include <drm/drm_modes.h> #include <drm/drm_panel.h> -#define DSI_REG_MCAP 0xB0 -#define DSI_REG_IS 0xB3 /* Interface Setting */ -#define DSI_REG_IIS 0xB4 /* Interface ID Setting */ -#define DSI_REG_CTRL 0xB6 +#define DSI_REG_MCAP 0xb0 +#define DSI_REG_IS 0xb3 /* Interface Setting */ +#define DSI_REG_IIS 0xb4 /* Interface ID Setting */ +#define DSI_REG_CTRL 0xb6 enum { IOVCC = 0, @@ -52,92 +52,55 @@ static inline struct stk_panel *to_stk_panel(struct drm_panel *panel) static int stk_panel_init(struct stk_panel *stk) { struct mipi_dsi_device *dsi = stk->dsi; - struct device *dev = &stk->dsi->dev; - int ret; - - ret = mipi_dsi_dcs_soft_reset(dsi); - if (ret < 0) { - dev_err(dev, "failed to mipi_dsi_dcs_soft_reset: %d\n", ret); - return ret; - } - mdelay(5); + struct mipi_dsi_multi_context dsi_ctx = {.dsi = dsi}; - ret = mipi_dsi_dcs_exit_sleep_mode(dsi); - if (ret < 0) { - dev_err(dev, "failed to set exit sleep mode: %d\n", ret); - return ret; - } - msleep(120); + mipi_dsi_dcs_soft_reset_multi(&dsi_ctx); + mipi_dsi_msleep(&dsi_ctx, 5); + mipi_dsi_dcs_exit_sleep_mode_multi(&dsi_ctx); + mipi_dsi_msleep(&dsi_ctx, 120); - mipi_dsi_generic_write_seq(dsi, DSI_REG_MCAP, 0x04); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, DSI_REG_MCAP, 0x04); /* Interface setting, video mode */ - mipi_dsi_generic_write_seq(dsi, DSI_REG_IS, 0x14, 0x08, 0x00, 0x22, 0x00); - mipi_dsi_generic_write_seq(dsi, DSI_REG_IIS, 0x0C, 0x00); - mipi_dsi_generic_write_seq(dsi, DSI_REG_CTRL, 0x3A, 0xD3); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, DSI_REG_IS, 0x14, 0x08, 0x00, 0x22, 0x00); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, DSI_REG_IIS, 0x0c, 0x00); + mipi_dsi_generic_write_seq_multi(&dsi_ctx, DSI_REG_CTRL, 0x3a, 0xd3); - ret = mipi_dsi_dcs_set_display_brightness(dsi, 0x77); - if (ret < 0) { - dev_err(dev, "failed to write display brightness: %d\n", ret); - return ret; - } + mipi_dsi_dcs_set_display_brightness_multi(&dsi_ctx, 0x77); - mipi_dsi_dcs_write_seq(dsi, MIPI_DCS_WRITE_CONTROL_DISPLAY, - MIPI_DCS_WRITE_MEMORY_START); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, MIPI_DCS_WRITE_CONTROL_DISPLAY, + MIPI_DCS_WRITE_MEMORY_START); - ret = mipi_dsi_dcs_set_pixel_format(dsi, 0x77); - if (ret < 0) { - dev_err(dev, "failed to set pixel format: %d\n", ret); - return ret; - } + mipi_dsi_dcs_set_pixel_format_multi(&dsi_ctx, 0x77); + mipi_dsi_dcs_set_column_address_multi(&dsi_ctx, 0, stk->mode->hdisplay - 1); + mipi_dsi_dcs_set_page_address_multi(&dsi_ctx, 0, stk->mode->vdisplay - 1); - ret = mipi_dsi_dcs_set_column_address(dsi, 0, stk->mode->hdisplay - 1); - if (ret < 0) { - dev_err(dev, "failed to set column address: %d\n", ret); - return ret; - } - - ret = mipi_dsi_dcs_set_page_address(dsi, 0, stk->mode->vdisplay - 1); - if (ret < 0) { - dev_err(dev, "failed to set page address: %d\n", ret); - return ret; - } - - return 0; + return dsi_ctx.accum_err; } static int stk_panel_on(struct stk_panel *stk) { struct mipi_dsi_device *dsi = stk->dsi; - struct device *dev = &stk->dsi->dev; - int ret; + struct mipi_dsi_multi_context dsi_ctx = {.dsi = dsi}; - ret = mipi_dsi_dcs_set_display_on(dsi); - if (ret < 0) - dev_err(dev, "failed to set display on: %d\n", ret); + mipi_dsi_dcs_set_display_on_multi(&dsi_ctx); - mdelay(20); + mipi_dsi_msleep(&dsi_ctx, 20); - return ret; + return dsi_ctx.accum_err; } static void stk_panel_off(struct stk_panel *stk) { struct mipi_dsi_device *dsi = stk->dsi; - struct device *dev = &stk->dsi->dev; - int ret; + struct mipi_dsi_multi_context dsi_ctx = {.dsi = dsi}; dsi->mode_flags &= ~MIPI_DSI_MODE_LPM; - ret = mipi_dsi_dcs_set_display_off(dsi); - if (ret < 0) - dev_err(dev, "failed to set display off: %d\n", ret); + mipi_dsi_dcs_set_display_off_multi(&dsi_ctx); + mipi_dsi_dcs_enter_sleep_mode_multi(&dsi_ctx); - ret = mipi_dsi_dcs_enter_sleep_mode(dsi); - if (ret < 0) - dev_err(dev, "failed to enter sleep mode: %d\n", ret); - - msleep(100); + mipi_dsi_msleep(&dsi_ctx, 100); } static int stk_panel_unprepare(struct drm_panel *panel) @@ -155,7 +118,6 @@ static int stk_panel_unprepare(struct drm_panel *panel) static int stk_panel_prepare(struct drm_panel *panel) { struct stk_panel *stk = to_stk_panel(panel); - struct device *dev = &stk->dsi->dev; int ret; gpiod_set_value(stk->reset_gpio, 0); @@ -175,16 +137,12 @@ static int stk_panel_prepare(struct drm_panel *panel) gpiod_set_value(stk->reset_gpio, 1); mdelay(10); ret = stk_panel_init(stk); - if (ret < 0) { - dev_err(dev, "failed to init panel: %d\n", ret); + if (ret < 0) goto poweroff; - } ret = stk_panel_on(stk); - if (ret < 0) { - dev_err(dev, "failed to set panel on: %d\n", ret); + if (ret < 0) goto poweroff; - } return 0; @@ -250,18 +208,15 @@ static int dsi_dcs_bl_get_brightness(struct backlight_device *bl) static int dsi_dcs_bl_update_status(struct backlight_device *bl) { struct mipi_dsi_device *dsi = bl_get_data(bl); - struct device *dev = &dsi->dev; - int ret; + struct mipi_dsi_multi_context dsi_ctx = {.dsi = dsi}; dsi->mode_flags &= ~MIPI_DSI_MODE_LPM; - ret = mipi_dsi_dcs_set_display_brightness(dsi, bl->props.brightness); - if (ret < 0) { - dev_err(dev, "failed to set DSI control: %d\n", ret); - return ret; - } + mipi_dsi_dcs_set_display_brightness_multi(&dsi_ctx, bl->props.brightness); + if (dsi_ctx.accum_err) + return dsi_ctx.accum_err; dsi->mode_flags |= MIPI_DSI_MODE_LPM; - return 0; + return dsi_ctx.accum_err; } static const struct backlight_ops dsi_bl_ops = { diff --git a/drivers/gpu/drm/panel/panel-visionox-vtdr6130.c b/drivers/gpu/drm/panel/panel-visionox-vtdr6130.c index 540099253e1b..17b8defe79c1 100644 --- a/drivers/gpu/drm/panel/panel-visionox-vtdr6130.c +++ b/drivers/gpu/drm/panel/panel-visionox-vtdr6130.c @@ -19,7 +19,13 @@ struct visionox_vtdr6130 { struct drm_panel panel; struct mipi_dsi_device *dsi; struct gpio_desc *reset_gpio; - struct regulator_bulk_data supplies[3]; + struct regulator_bulk_data *supplies; +}; + +static const struct regulator_bulk_data visionox_vtdr6130_supplies[] = { + { .supply = "vddio" }, + { .supply = "vci" }, + { .supply = "vdd" }, }; static inline struct visionox_vtdr6130 *to_visionox_vtdr6130(struct drm_panel *panel) @@ -40,123 +46,106 @@ static void visionox_vtdr6130_reset(struct visionox_vtdr6130 *ctx) static int visionox_vtdr6130_on(struct visionox_vtdr6130 *ctx) { struct mipi_dsi_device *dsi = ctx->dsi; - struct device *dev = &dsi->dev; - int ret; + struct mipi_dsi_multi_context dsi_ctx = { .dsi = dsi }; dsi->mode_flags |= MIPI_DSI_MODE_LPM; - ret = mipi_dsi_dcs_set_tear_on(dsi, MIPI_DSI_DCS_TEAR_MODE_VBLANK); - if (ret) - return ret; - - mipi_dsi_dcs_write_seq(dsi, MIPI_DCS_WRITE_CONTROL_DISPLAY, 0x20); - mipi_dsi_dcs_write_seq(dsi, MIPI_DCS_SET_DISPLAY_BRIGHTNESS, 0x00, 0x00); - mipi_dsi_dcs_write_seq(dsi, 0x59, 0x09); - mipi_dsi_dcs_write_seq(dsi, 0x6c, 0x01); - mipi_dsi_dcs_write_seq(dsi, 0x6d, 0x00); - mipi_dsi_dcs_write_seq(dsi, 0x6f, 0x01); - mipi_dsi_dcs_write_seq(dsi, 0x70, - 0x12, 0x00, 0x00, 0xab, 0x30, 0x80, 0x09, 0x60, 0x04, - 0x38, 0x00, 0x28, 0x02, 0x1c, 0x02, 0x1c, 0x02, 0x00, - 0x02, 0x0e, 0x00, 0x20, 0x03, 0xdd, 0x00, 0x07, 0x00, - 0x0c, 0x02, 0x77, 0x02, 0x8b, 0x18, 0x00, 0x10, 0xf0, - 0x07, 0x10, 0x20, 0x00, 0x06, 0x0f, 0x0f, 0x33, 0x0e, - 0x1c, 0x2a, 0x38, 0x46, 0x54, 0x62, 0x69, 0x70, 0x77, - 0x79, 0x7b, 0x7d, 0x7e, 0x02, 0x02, 0x22, 0x00, 0x2a, - 0x40, 0x2a, 0xbe, 0x3a, 0xfc, 0x3a, 0xfa, 0x3a, 0xf8, - 0x3b, 0x38, 0x3b, 0x78, 0x3b, 0xb6, 0x4b, 0xb6, 0x4b, - 0xf4, 0x4b, 0xf4, 0x6c, 0x34, 0x84, 0x74, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00); - mipi_dsi_dcs_write_seq(dsi, 0xf0, 0xaa, 0x10); - mipi_dsi_dcs_write_seq(dsi, 0xb1, - 0x01, 0x38, 0x00, 0x14, 0x00, 0x1c, 0x00, 0x01, 0x66, - 0x00, 0x14, 0x00, 0x14, 0x00, 0x01, 0x66, 0x00, 0x14, - 0x05, 0xcc, 0x00); - mipi_dsi_dcs_write_seq(dsi, 0xf0, 0xaa, 0x13); - mipi_dsi_dcs_write_seq(dsi, 0xce, - 0x09, 0x11, 0x09, 0x11, 0x08, 0xc1, 0x07, 0xfa, 0x05, - 0xa4, 0x00, 0x3c, 0x00, 0x34, 0x00, 0x24, 0x00, 0x0c, - 0x00, 0x0c, 0x04, 0x00, 0x35); - mipi_dsi_dcs_write_seq(dsi, 0xf0, 0xaa, 0x14); - mipi_dsi_dcs_write_seq(dsi, 0xb2, 0x03, 0x33); - mipi_dsi_dcs_write_seq(dsi, 0xb4, - 0x00, 0x33, 0x00, 0x00, 0x00, 0x3e, 0x00, 0x00, 0x00, - 0x3e, 0x00, 0x00); - mipi_dsi_dcs_write_seq(dsi, 0xb5, - 0x00, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x06, 0x01); - mipi_dsi_dcs_write_seq(dsi, 0xb9, 0x00, 0x00, 0x08, 0x09, 0x09, 0x09); - mipi_dsi_dcs_write_seq(dsi, 0xbc, - 0x10, 0x00, 0x00, 0x06, 0x11, 0x09, 0x3b, 0x09, 0x47, - 0x09, 0x47, 0x00); - mipi_dsi_dcs_write_seq(dsi, 0xbe, - 0x10, 0x10, 0x00, 0x08, 0x22, 0x09, 0x19, 0x09, 0x25, - 0x09, 0x25, 0x00); - mipi_dsi_dcs_write_seq(dsi, 0xff, 0x5a, 0x80); - mipi_dsi_dcs_write_seq(dsi, 0x65, 0x14); - mipi_dsi_dcs_write_seq(dsi, 0xfa, 0x08, 0x08, 0x08); - mipi_dsi_dcs_write_seq(dsi, 0xff, 0x5a, 0x81); - mipi_dsi_dcs_write_seq(dsi, 0x65, 0x05); - mipi_dsi_dcs_write_seq(dsi, 0xf3, 0x0f); - mipi_dsi_dcs_write_seq(dsi, 0xf0, 0xaa, 0x00); - mipi_dsi_dcs_write_seq(dsi, 0xff, 0x5a, 0x82); - mipi_dsi_dcs_write_seq(dsi, 0xf9, 0x00); - mipi_dsi_dcs_write_seq(dsi, 0xff, 0x51, 0x83); - mipi_dsi_dcs_write_seq(dsi, 0x65, 0x04); - mipi_dsi_dcs_write_seq(dsi, 0xf8, 0x00); - mipi_dsi_dcs_write_seq(dsi, 0xff, 0x5a, 0x00); - mipi_dsi_dcs_write_seq(dsi, 0x65, 0x01); - mipi_dsi_dcs_write_seq(dsi, 0xf4, 0x9a); - mipi_dsi_dcs_write_seq(dsi, 0xff, 0x5a, 0x00); - - ret = mipi_dsi_dcs_exit_sleep_mode(dsi); - if (ret < 0) { - dev_err(dev, "Failed to exit sleep mode: %d\n", ret); - return ret; - } - msleep(120); - - ret = mipi_dsi_dcs_set_display_on(dsi); - if (ret < 0) { - dev_err(dev, "Failed to set display on: %d\n", ret); - return ret; - } - msleep(20); - - return 0; + mipi_dsi_dcs_set_tear_on_multi(&dsi_ctx, MIPI_DSI_DCS_TEAR_MODE_VBLANK); + + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, + MIPI_DCS_WRITE_CONTROL_DISPLAY, 0x20); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, + MIPI_DCS_SET_DISPLAY_BRIGHTNESS, 0x00, + 0x00); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x59, 0x09); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6c, 0x01); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6d, 0x00); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6f, 0x01); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x70, 0x12, 0x00, 0x00, 0xab, + 0x30, 0x80, 0x09, 0x60, 0x04, 0x38, 0x00, + 0x28, 0x02, 0x1c, 0x02, 0x1c, 0x02, 0x00, + 0x02, 0x0e, 0x00, 0x20, 0x03, 0xdd, 0x00, + 0x07, 0x00, 0x0c, 0x02, 0x77, 0x02, 0x8b, + 0x18, 0x00, 0x10, 0xf0, 0x07, 0x10, 0x20, + 0x00, 0x06, 0x0f, 0x0f, 0x33, 0x0e, 0x1c, + 0x2a, 0x38, 0x46, 0x54, 0x62, 0x69, 0x70, + 0x77, 0x79, 0x7b, 0x7d, 0x7e, 0x02, 0x02, + 0x22, 0x00, 0x2a, 0x40, 0x2a, 0xbe, 0x3a, + 0xfc, 0x3a, 0xfa, 0x3a, 0xf8, 0x3b, 0x38, + 0x3b, 0x78, 0x3b, 0xb6, 0x4b, 0xb6, 0x4b, + 0xf4, 0x4b, 0xf4, 0x6c, 0x34, 0x84, 0x74, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xf0, 0xaa, 0x10); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xb1, 0x01, 0x38, 0x00, 0x14, + 0x00, 0x1c, 0x00, 0x01, 0x66, 0x00, 0x14, + 0x00, 0x14, 0x00, 0x01, 0x66, 0x00, 0x14, + 0x05, 0xcc, 0x00); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xf0, 0xaa, 0x13); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xce, 0x09, 0x11, 0x09, 0x11, + 0x08, 0xc1, 0x07, 0xfa, 0x05, 0xa4, 0x00, + 0x3c, 0x00, 0x34, 0x00, 0x24, 0x00, 0x0c, + 0x00, 0x0c, 0x04, 0x00, 0x35); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xf0, 0xaa, 0x14); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xb2, 0x03, 0x33); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xb4, 0x00, 0x33, 0x00, 0x00, + 0x00, 0x3e, 0x00, 0x00, 0x00, 0x3e, 0x00, + 0x00); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xb5, 0x00, 0x09, 0x09, 0x09, + 0x09, 0x09, 0x09, 0x06, 0x01); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xb9, 0x00, 0x00, 0x08, 0x09, + 0x09, 0x09); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xbc, 0x10, 0x00, 0x00, 0x06, + 0x11, 0x09, 0x3b, 0x09, 0x47, 0x09, 0x47, + 0x00); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xbe, 0x10, 0x10, 0x00, 0x08, + 0x22, 0x09, 0x19, 0x09, 0x25, 0x09, 0x25, + 0x00); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xff, 0x5a, 0x80); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x65, 0x14); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xfa, 0x08, 0x08, 0x08); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xff, 0x5a, 0x81); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x65, 0x05); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xf3, 0x0f); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xf0, 0xaa, 0x00); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xff, 0x5a, 0x82); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xf9, 0x00); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xff, 0x51, 0x83); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x65, 0x04); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xf8, 0x00); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xff, 0x5a, 0x00); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x65, 0x01); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xf4, 0x9a); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xff, 0x5a, 0x00); + + mipi_dsi_dcs_exit_sleep_mode_multi(&dsi_ctx); + mipi_dsi_msleep(&dsi_ctx, 120); + + mipi_dsi_dcs_set_display_on_multi(&dsi_ctx); + mipi_dsi_msleep(&dsi_ctx, 20); + + return dsi_ctx.accum_err; } -static int visionox_vtdr6130_off(struct visionox_vtdr6130 *ctx) +static void visionox_vtdr6130_off(struct visionox_vtdr6130 *ctx) { struct mipi_dsi_device *dsi = ctx->dsi; - struct device *dev = &dsi->dev; - int ret; + struct mipi_dsi_multi_context dsi_ctx = { .dsi = dsi }; dsi->mode_flags &= ~MIPI_DSI_MODE_LPM; - ret = mipi_dsi_dcs_set_display_off(dsi); - if (ret < 0) { - dev_err(dev, "Failed to set display off: %d\n", ret); - return ret; - } - msleep(20); - - ret = mipi_dsi_dcs_enter_sleep_mode(dsi); - if (ret < 0) { - dev_err(dev, "Failed to enter sleep mode: %d\n", ret); - return ret; - } - msleep(120); + mipi_dsi_dcs_set_display_off_multi(&dsi_ctx); + mipi_dsi_msleep(&dsi_ctx, 20); - return 0; + mipi_dsi_dcs_enter_sleep_mode_multi(&dsi_ctx); + mipi_dsi_msleep(&dsi_ctx, 120); } static int visionox_vtdr6130_prepare(struct drm_panel *panel) { struct visionox_vtdr6130 *ctx = to_visionox_vtdr6130(panel); - struct device *dev = &ctx->dsi->dev; int ret; - ret = regulator_bulk_enable(ARRAY_SIZE(ctx->supplies), + ret = regulator_bulk_enable(ARRAY_SIZE(visionox_vtdr6130_supplies), ctx->supplies); if (ret < 0) return ret; @@ -165,9 +154,9 @@ static int visionox_vtdr6130_prepare(struct drm_panel *panel) ret = visionox_vtdr6130_on(ctx); if (ret < 0) { - dev_err(dev, "Failed to initialize panel: %d\n", ret); gpiod_set_value_cansleep(ctx->reset_gpio, 1); - regulator_bulk_disable(ARRAY_SIZE(ctx->supplies), ctx->supplies); + regulator_bulk_disable(ARRAY_SIZE(visionox_vtdr6130_supplies), + ctx->supplies); return ret; } @@ -177,16 +166,13 @@ static int visionox_vtdr6130_prepare(struct drm_panel *panel) static int visionox_vtdr6130_unprepare(struct drm_panel *panel) { struct visionox_vtdr6130 *ctx = to_visionox_vtdr6130(panel); - struct device *dev = &ctx->dsi->dev; - int ret; - ret = visionox_vtdr6130_off(ctx); - if (ret < 0) - dev_err(dev, "Failed to un-initialize panel: %d\n", ret); + visionox_vtdr6130_off(ctx); gpiod_set_value_cansleep(ctx->reset_gpio, 1); - regulator_bulk_disable(ARRAY_SIZE(ctx->supplies), ctx->supplies); + regulator_bulk_disable(ARRAY_SIZE(visionox_vtdr6130_supplies), + ctx->supplies); return 0; } @@ -266,12 +252,10 @@ static int visionox_vtdr6130_probe(struct mipi_dsi_device *dsi) if (!ctx) return -ENOMEM; - ctx->supplies[0].supply = "vddio"; - ctx->supplies[1].supply = "vci"; - ctx->supplies[2].supply = "vdd"; - - ret = devm_regulator_bulk_get(&dsi->dev, ARRAY_SIZE(ctx->supplies), - ctx->supplies); + ret = devm_regulator_bulk_get_const(&dsi->dev, + ARRAY_SIZE(visionox_vtdr6130_supplies), + visionox_vtdr6130_supplies, + &ctx->supplies); if (ret < 0) return ret; |