diff options
Diffstat (limited to 'drivers/gpu/drm/imx')
| -rw-r--r-- | drivers/gpu/drm/imx/Kconfig | 3 | ||||
| -rw-r--r-- | drivers/gpu/drm/imx/Makefile | 2 | ||||
| -rw-r--r-- | drivers/gpu/drm/imx/dw_hdmi-imx.c | 258 | ||||
| -rw-r--r-- | drivers/gpu/drm/imx/imx-drm-core.c | 87 | ||||
| -rw-r--r-- | drivers/gpu/drm/imx/imx-drm.h | 2 | ||||
| -rw-r--r-- | drivers/gpu/drm/imx/imx-hdmi.c | 1766 | ||||
| -rw-r--r-- | drivers/gpu/drm/imx/imx-hdmi.h | 1032 | ||||
| -rw-r--r-- | drivers/gpu/drm/imx/imx-ldb.c | 8 | ||||
| -rw-r--r-- | drivers/gpu/drm/imx/imx-tve.c | 28 | ||||
| -rw-r--r-- | drivers/gpu/drm/imx/ipuv3-crtc.c | 78 | ||||
| -rw-r--r-- | drivers/gpu/drm/imx/parallel-display.c | 7 |
11 files changed, 350 insertions, 2921 deletions
diff --git a/drivers/gpu/drm/imx/Kconfig b/drivers/gpu/drm/imx/Kconfig index ab31848e92cf..33cdddf26684 100644 --- a/drivers/gpu/drm/imx/Kconfig +++ b/drivers/gpu/drm/imx/Kconfig @@ -5,7 +5,7 @@ config DRM_IMX select VIDEOMODE_HELPERS select DRM_GEM_CMA_HELPER select DRM_KMS_CMA_HELPER - depends on DRM && (ARCH_MXC || ARCH_MULTIPLATFORM) + depends on DRM && (ARCH_MXC || ARCH_MULTIPLATFORM) && HAVE_DMA_ATTRS depends on IMX_IPUV3_CORE help enable i.MX graphics support @@ -49,6 +49,7 @@ config DRM_IMX_IPUV3 config DRM_IMX_HDMI tristate "Freescale i.MX DRM HDMI" + select DRM_DW_HDMI depends on DRM_IMX help Choose this if you want to use HDMI on i.MX6. diff --git a/drivers/gpu/drm/imx/Makefile b/drivers/gpu/drm/imx/Makefile index 582c438d8cbd..f3ecd8903d97 100644 --- a/drivers/gpu/drm/imx/Makefile +++ b/drivers/gpu/drm/imx/Makefile @@ -9,4 +9,4 @@ obj-$(CONFIG_DRM_IMX_LDB) += imx-ldb.o imx-ipuv3-crtc-objs := ipuv3-crtc.o ipuv3-plane.o obj-$(CONFIG_DRM_IMX_IPUV3) += imx-ipuv3-crtc.o -obj-$(CONFIG_DRM_IMX_HDMI) += imx-hdmi.o +obj-$(CONFIG_DRM_IMX_HDMI) += dw_hdmi-imx.o diff --git a/drivers/gpu/drm/imx/dw_hdmi-imx.c b/drivers/gpu/drm/imx/dw_hdmi-imx.c new file mode 100644 index 000000000000..121d30ca2d44 --- /dev/null +++ b/drivers/gpu/drm/imx/dw_hdmi-imx.c @@ -0,0 +1,258 @@ +/* Copyright (C) 2011-2013 Freescale Semiconductor, Inc. + * + * derived from imx-hdmi.c(renamed to bridge/dw_hdmi.c now) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +#include <linux/module.h> +#include <linux/platform_device.h> +#include <linux/component.h> +#include <linux/mfd/syscon.h> +#include <linux/mfd/syscon/imx6q-iomuxc-gpr.h> +#include <drm/bridge/dw_hdmi.h> +#include <video/imx-ipu-v3.h> +#include <linux/regmap.h> +#include <drm/drm_of.h> +#include <drm/drmP.h> +#include <drm/drm_crtc_helper.h> +#include <drm/drm_edid.h> +#include <drm/drm_encoder_slave.h> + +#include "imx-drm.h" + +struct imx_hdmi { + struct device *dev; + struct drm_encoder encoder; + struct regmap *regmap; +}; + +static const struct dw_hdmi_mpll_config imx_mpll_cfg[] = { + { + 45250000, { + { 0x01e0, 0x0000 }, + { 0x21e1, 0x0000 }, + { 0x41e2, 0x0000 } + }, + }, { + 92500000, { + { 0x0140, 0x0005 }, + { 0x2141, 0x0005 }, + { 0x4142, 0x0005 }, + }, + }, { + 148500000, { + { 0x00a0, 0x000a }, + { 0x20a1, 0x000a }, + { 0x40a2, 0x000a }, + }, + }, { + ~0UL, { + { 0x00a0, 0x000a }, + { 0x2001, 0x000f }, + { 0x4002, 0x000f }, + }, + } +}; + +static const struct dw_hdmi_curr_ctrl imx_cur_ctr[] = { + /* pixelclk bpp8 bpp10 bpp12 */ + { + 54000000, { 0x091c, 0x091c, 0x06dc }, + }, { + 58400000, { 0x091c, 0x06dc, 0x06dc }, + }, { + 72000000, { 0x06dc, 0x06dc, 0x091c }, + }, { + 74250000, { 0x06dc, 0x0b5c, 0x091c }, + }, { + 118800000, { 0x091c, 0x091c, 0x06dc }, + }, { + 216000000, { 0x06dc, 0x0b5c, 0x091c }, + } +}; + +static const struct dw_hdmi_sym_term imx_sym_term[] = { + /*pixelclk symbol term*/ + { 148500000, 0x800d, 0x0005 }, + { ~0UL, 0x0000, 0x0000 } +}; + +static int dw_hdmi_imx_parse_dt(struct imx_hdmi *hdmi) +{ + struct device_node *np = hdmi->dev->of_node; + + hdmi->regmap = syscon_regmap_lookup_by_phandle(np, "gpr"); + if (IS_ERR(hdmi->regmap)) { + dev_err(hdmi->dev, "Unable to get gpr\n"); + return PTR_ERR(hdmi->regmap); + } + + return 0; +} + +static void dw_hdmi_imx_encoder_disable(struct drm_encoder *encoder) +{ +} + +static bool dw_hdmi_imx_encoder_mode_fixup(struct drm_encoder *encoder, + const struct drm_display_mode *mode, + struct drm_display_mode *adj_mode) +{ + return true; +} + +static void dw_hdmi_imx_encoder_mode_set(struct drm_encoder *encoder, + struct drm_display_mode *mode, + struct drm_display_mode *adj_mode) +{ +} + +static void dw_hdmi_imx_encoder_commit(struct drm_encoder *encoder) +{ + struct imx_hdmi *hdmi = container_of(encoder, struct imx_hdmi, encoder); + int mux = imx_drm_encoder_get_mux_id(hdmi->dev->of_node, encoder); + + regmap_update_bits(hdmi->regmap, IOMUXC_GPR3, + IMX6Q_GPR3_HDMI_MUX_CTL_MASK, + mux << IMX6Q_GPR3_HDMI_MUX_CTL_SHIFT); +} + +static void dw_hdmi_imx_encoder_prepare(struct drm_encoder *encoder) +{ + imx_drm_panel_format(encoder, V4L2_PIX_FMT_RGB24); +} + +static struct drm_encoder_helper_funcs dw_hdmi_imx_encoder_helper_funcs = { + .mode_fixup = dw_hdmi_imx_encoder_mode_fixup, + .mode_set = dw_hdmi_imx_encoder_mode_set, + .prepare = dw_hdmi_imx_encoder_prepare, + .commit = dw_hdmi_imx_encoder_commit, + .disable = dw_hdmi_imx_encoder_disable, +}; + +static struct drm_encoder_funcs dw_hdmi_imx_encoder_funcs = { + .destroy = drm_encoder_cleanup, +}; + +static struct dw_hdmi_plat_data imx6q_hdmi_drv_data = { + .mpll_cfg = imx_mpll_cfg, + .cur_ctr = imx_cur_ctr, + .sym_term = imx_sym_term, + .dev_type = IMX6Q_HDMI, +}; + +static struct dw_hdmi_plat_data imx6dl_hdmi_drv_data = { + .mpll_cfg = imx_mpll_cfg, + .cur_ctr = imx_cur_ctr, + .sym_term = imx_sym_term, + .dev_type = IMX6DL_HDMI, +}; + +static const struct of_device_id dw_hdmi_imx_dt_ids[] = { + { .compatible = "fsl,imx6q-hdmi", + .data = &imx6q_hdmi_drv_data + }, { + .compatible = "fsl,imx6dl-hdmi", + .data = &imx6dl_hdmi_drv_data + }, + {}, +}; +MODULE_DEVICE_TABLE(of, dw_hdmi_imx_dt_ids); + +static int dw_hdmi_imx_bind(struct device *dev, struct device *master, + void *data) +{ + struct platform_device *pdev = to_platform_device(dev); + const struct dw_hdmi_plat_data *plat_data; + const struct of_device_id *match; + struct drm_device *drm = data; + struct drm_encoder *encoder; + struct imx_hdmi *hdmi; + struct resource *iores; + int irq; + int ret; + + if (!pdev->dev.of_node) + return -ENODEV; + + hdmi = devm_kzalloc(&pdev->dev, sizeof(*hdmi), GFP_KERNEL); + if (!hdmi) + return -ENOMEM; + + match = of_match_node(dw_hdmi_imx_dt_ids, pdev->dev.of_node); + plat_data = match->data; + hdmi->dev = &pdev->dev; + encoder = &hdmi->encoder; + + irq = platform_get_irq(pdev, 0); + if (irq < 0) + return irq; + + iores = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!iores) + return -ENXIO; + + platform_set_drvdata(pdev, hdmi); + + encoder->possible_crtcs = drm_of_find_possible_crtcs(drm, dev->of_node); + /* + * If we failed to find the CRTC(s) which this encoder is + * supposed to be connected to, it's because the CRTC has + * not been registered yet. Defer probing, and hope that + * the required CRTC is added later. + */ + if (encoder->possible_crtcs == 0) + return -EPROBE_DEFER; + + ret = dw_hdmi_imx_parse_dt(hdmi); + if (ret < 0) + return ret; + + drm_encoder_helper_add(encoder, &dw_hdmi_imx_encoder_helper_funcs); + drm_encoder_init(drm, encoder, &dw_hdmi_imx_encoder_funcs, + DRM_MODE_ENCODER_TMDS); + + return dw_hdmi_bind(dev, master, data, encoder, iores, irq, plat_data); +} + +static void dw_hdmi_imx_unbind(struct device *dev, struct device *master, + void *data) +{ + return dw_hdmi_unbind(dev, master, data); +} + +static const struct component_ops dw_hdmi_imx_ops = { + .bind = dw_hdmi_imx_bind, + .unbind = dw_hdmi_imx_unbind, +}; + +static int dw_hdmi_imx_probe(struct platform_device *pdev) +{ + return component_add(&pdev->dev, &dw_hdmi_imx_ops); +} + +static int dw_hdmi_imx_remove(struct platform_device *pdev) +{ + component_del(&pdev->dev, &dw_hdmi_imx_ops); + + return 0; +} + +static struct platform_driver dw_hdmi_imx_platform_driver = { + .probe = dw_hdmi_imx_probe, + .remove = dw_hdmi_imx_remove, + .driver = { + .name = "dwhdmi-imx", + .of_match_table = dw_hdmi_imx_dt_ids, + }, +}; + +module_platform_driver(dw_hdmi_imx_platform_driver); + +MODULE_AUTHOR("Andy Yan <andy.yan@rock-chips.com>"); +MODULE_AUTHOR("Yakir Yang <ykk@rock-chips.com>"); +MODULE_DESCRIPTION("IMX6 Specific DW-HDMI Driver Extension"); +MODULE_LICENSE("GPL"); +MODULE_ALIAS("platform:dwhdmi-imx"); diff --git a/drivers/gpu/drm/imx/imx-drm-core.c b/drivers/gpu/drm/imx/imx-drm-core.c index b250130debc8..a002f53aab0e 100644 --- a/drivers/gpu/drm/imx/imx-drm-core.c +++ b/drivers/gpu/drm/imx/imx-drm-core.c @@ -25,6 +25,7 @@ #include <drm/drm_gem_cma_helper.h> #include <drm/drm_fb_cma_helper.h> #include <drm/drm_plane_helper.h> +#include <drm/drm_of.h> #include "imx-drm.h" @@ -46,7 +47,6 @@ struct imx_drm_crtc { struct drm_crtc *crtc; int pipe; struct imx_drm_crtc_helper_funcs imx_drm_helper_funcs; - struct device_node *port; }; static int legacyfb_depth = 16; @@ -116,8 +116,7 @@ int imx_drm_panel_format_pins(struct drm_encoder *encoder, helper = &imx_crtc->imx_drm_helper_funcs; if (helper->set_interface_pix_fmt) return helper->set_interface_pix_fmt(encoder->crtc, - encoder->encoder_type, interface_pix_fmt, - hsync_pin, vsync_pin); + interface_pix_fmt, hsync_pin, vsync_pin); return 0; } EXPORT_SYMBOL_GPL(imx_drm_panel_format_pins); @@ -365,9 +364,10 @@ int imx_drm_add_crtc(struct drm_device *drm, struct drm_crtc *crtc, imx_drm_crtc->imx_drm_helper_funcs = *imx_drm_helper_funcs; imx_drm_crtc->pipe = imxdrm->pipes++; - imx_drm_crtc->port = port; imx_drm_crtc->crtc = crtc; + crtc->port = port; + imxdrm->crtc[imx_drm_crtc->pipe] = imx_drm_crtc; *new_crtc = imx_drm_crtc; @@ -408,33 +408,28 @@ int imx_drm_remove_crtc(struct imx_drm_crtc *imx_drm_crtc) } EXPORT_SYMBOL_GPL(imx_drm_remove_crtc); -/* - * Find the DRM CRTC possible mask for the connected endpoint. - * - * The encoder possible masks are defined by their position in the - * mode_config crtc_list. This means that CRTCs must not be added - * or removed once the DRM device has been fully initialised. - */ -static uint32_t imx_drm_find_crtc_mask(struct imx_drm_device *imxdrm, - struct device_node *endpoint) +int imx_drm_encoder_parse_of(struct drm_device *drm, + struct drm_encoder *encoder, struct device_node *np) { - struct device_node *port; - unsigned i; + uint32_t crtc_mask = drm_of_find_possible_crtcs(drm, np); - port = of_graph_get_remote_port(endpoint); - if (!port) - return 0; - of_node_put(port); + /* + * If we failed to find the CRTC(s) which this encoder is + * supposed to be connected to, it's because the CRTC has + * not been registered yet. Defer probing, and hope that + * the required CRTC is added later. + */ + if (crtc_mask == 0) + return -EPROBE_DEFER; - for (i = 0; i < MAX_CRTC; i++) { - struct imx_drm_crtc *imx_drm_crtc = imxdrm->crtc[i]; + encoder->possible_crtcs = crtc_mask; - if (imx_drm_crtc && imx_drm_crtc->port == port) - return drm_crtc_mask(imx_drm_crtc->crtc); - } + /* FIXME: this is the mask of outputs which can clone this output. */ + encoder->possible_clones = ~0; return 0; } +EXPORT_SYMBOL_GPL(imx_drm_encoder_parse_of); static struct device_node *imx_drm_of_get_next_endpoint( const struct device_node *parent, struct device_node *prev) @@ -445,48 +440,6 @@ static struct device_node *imx_drm_of_get_next_endpoint( return node; } -int imx_drm_encoder_parse_of(struct drm_device *drm, - struct drm_encoder *encoder, struct device_node *np) -{ - struct imx_drm_device *imxdrm = drm->dev_private; - struct device_node *ep = NULL; - uint32_t crtc_mask = 0; - int i; - - for (i = 0; ; i++) { - u32 mask; - - ep = imx_drm_of_get_next_endpoint(np, ep); - if (!ep) - break; - - mask = imx_drm_find_crtc_mask(imxdrm, ep); - - /* - * If we failed to find the CRTC(s) which this encoder is - * supposed to be connected to, it's because the CRTC has - * not been registered yet. Defer probing, and hope that - * the required CRTC is added later. - */ - if (mask == 0) - return -EPROBE_DEFER; - - crtc_mask |= mask; - } - - of_node_put(ep); - if (i == 0) - return -ENOENT; - - encoder->possible_crtcs = crtc_mask; - - /* FIXME: this is the mask of outputs which can clone this output. */ - encoder->possible_clones = ~0; - - return 0; -} -EXPORT_SYMBOL_GPL(imx_drm_encoder_parse_of); - /* * @node: device tree node containing encoder input ports * @encoder: drm_encoder @@ -510,7 +463,7 @@ int imx_drm_encoder_get_mux_id(struct device_node *node, port = of_graph_get_remote_port(ep); of_node_put(port); - if (port == imx_crtc->port) { + if (port == imx_crtc->crtc->port) { ret = of_graph_parse_endpoint(ep, &endpoint); return ret ? ret : endpoint.port; } diff --git a/drivers/gpu/drm/imx/imx-drm.h b/drivers/gpu/drm/imx/imx-drm.h index 7453ae00c412..3c559ccd6af0 100644 --- a/drivers/gpu/drm/imx/imx-drm.h +++ b/drivers/gpu/drm/imx/imx-drm.h @@ -17,7 +17,7 @@ int imx_drm_crtc_id(struct imx_drm_crtc *crtc); struct imx_drm_crtc_helper_funcs { int (*enable_vblank)(struct drm_crtc *crtc); void (*disable_vblank)(struct drm_crtc *crtc); - int (*set_interface_pix_fmt)(struct drm_crtc *crtc, u32 encoder_type, + int (*set_interface_pix_fmt)(struct drm_crtc *crtc, u32 pix_fmt, int hsync_pin, int vsync_pin); const struct drm_crtc_helper_funcs *crtc_helper_funcs; const struct drm_crtc_funcs *crtc_funcs; diff --git a/drivers/gpu/drm/imx/imx-hdmi.c b/drivers/gpu/drm/imx/imx-hdmi.c deleted file mode 100644 index ddc53e039530..000000000000 --- a/drivers/gpu/drm/imx/imx-hdmi.c +++ /dev/null @@ -1,1766 +0,0 @@ -/* - * Copyright (C) 2011-2013 Freescale Semiconductor, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * SH-Mobile High-Definition Multimedia Interface (HDMI) driver - * for SLISHDMI13T and SLIPHDMIT IP cores - * - * Copyright (C) 2010, Guennadi Liakhovetski <g.liakhovetski@gmx.de> - */ - -#include <linux/component.h> -#include <linux/irq.h> -#include <linux/delay.h> -#include <linux/err.h> -#include <linux/clk.h> -#include <linux/hdmi.h> -#include <linux/regmap.h> -#include <linux/mfd/syscon.h> -#include <linux/mfd/syscon/imx6q-iomuxc-gpr.h> -#include <linux/of_device.h> - -#include <drm/drmP.h> -#include <drm/drm_crtc_helper.h> -#include <drm/drm_edid.h> -#include <drm/drm_encoder_slave.h> -#include <video/imx-ipu-v3.h> - -#include "imx-hdmi.h" -#include "imx-drm.h" - -#define HDMI_EDID_LEN 512 - -#define RGB 0 -#define YCBCR444 1 -#define YCBCR422_16BITS 2 -#define YCBCR422_8BITS 3 -#define XVYCC444 4 - -enum hdmi_datamap { - RGB444_8B = 0x01, - RGB444_10B = 0x03, - RGB444_12B = 0x05, - RGB444_16B = 0x07, - YCbCr444_8B = 0x09, - YCbCr444_10B = 0x0B, - YCbCr444_12B = 0x0D, - YCbCr444_16B = 0x0F, - YCbCr422_8B = 0x16, - YCbCr422_10B = 0x14, - YCbCr422_12B = 0x12, -}; - -enum imx_hdmi_devtype { - IMX6Q_HDMI, - IMX6DL_HDMI, -}; - -static const u16 csc_coeff_default[3][4] = { - { 0x2000, 0x0000, 0x0000, 0x0000 }, - { 0x0000, 0x2000, 0x0000, 0x0000 }, - { 0x0000, 0x0000, 0x2000, 0x0000 } -}; - -static const u16 csc_coeff_rgb_out_eitu601[3][4] = { - { 0x2000, 0x6926, 0x74fd, 0x010e }, - { 0x2000, 0x2cdd, 0x0000, 0x7e9a }, - { 0x2000, 0x0000, 0x38b4, 0x7e3b } -}; - -static const u16 csc_coeff_rgb_out_eitu709[3][4] = { - { 0x2000, 0x7106, 0x7a02, 0x00a7 }, - { 0x2000, 0x3264, 0x0000, 0x7e6d }, - { 0x2000, 0x0000, 0x3b61, 0x7e25 } -}; - -static const u16 csc_coeff_rgb_in_eitu601[3][4] = { - { 0x2591, 0x1322, 0x074b, 0x0000 }, - { 0x6535, 0x2000, 0x7acc, 0x0200 }, - { 0x6acd, 0x7534, 0x2000, 0x0200 } -}; - -static const u16 csc_coeff_rgb_in_eitu709[3][4] = { - { 0x2dc5, 0x0d9b, 0x049e, 0x0000 }, - { 0x62f0, 0x2000, 0x7d11, 0x0200 }, - { 0x6756, 0x78ab, 0x2000, 0x0200 } -}; - -struct hdmi_vmode { - bool mdvi; - bool mhsyncpolarity; - bool mvsyncpolarity; - bool minterlaced; - bool mdataenablepolarity; - - unsigned int mpixelclock; - unsigned int mpixelrepetitioninput; - unsigned int mpixelrepetitionoutput; -}; - -struct hdmi_data_info { - unsigned int enc_in_format; - unsigned int enc_out_format; - unsigned int enc_color_depth; - unsigned int colorimetry; - unsigned int pix_repet_factor; - unsigned int hdcp_enable; - struct hdmi_vmode video_mode; -}; - -struct imx_hdmi { - struct drm_connector connector; - struct drm_encoder encoder; - - enum imx_hdmi_devtype dev_type; - struct device *dev; - struct clk *isfr_clk; - struct clk *iahb_clk; - - struct hdmi_data_info hdmi_data; - int vic; - - u8 edid[HDMI_EDID_LEN]; - bool cable_plugin; - - bool phy_enabled; - struct drm_display_mode previous_mode; - - struct regmap *regmap; - struct i2c_adapter *ddc; - void __iomem *regs; - - unsigned int sample_rate; - int ratio; -}; - -static void imx_hdmi_set_ipu_di_mux(struct imx_hdmi *hdmi, int ipu_di) -{ - regmap_update_bits(hdmi->regmap, IOMUXC_GPR3, - IMX6Q_GPR3_HDMI_MUX_CTL_MASK, - ipu_di << IMX6Q_GPR3_HDMI_MUX_CTL_SHIFT); -} - -static inline void hdmi_writeb(struct imx_hdmi *hdmi, u8 val, int offset) -{ - writeb(val, hdmi->regs + offset); -} - -static inline u8 hdmi_readb(struct imx_hdmi *hdmi, int offset) -{ - return readb(hdmi->regs + offset); -} - -static void hdmi_modb(struct imx_hdmi *hdmi, u8 data, u8 mask, unsigned reg) -{ - u8 val = hdmi_readb(hdmi, reg) & ~mask; - - val |= data & mask; - hdmi_writeb(hdmi, val, reg); -} - -static void hdmi_mask_writeb(struct imx_hdmi *hdmi, u8 data, unsigned int reg, - u8 shift, u8 mask) -{ - hdmi_modb(hdmi, data << shift, mask, reg); -} - -static void hdmi_set_clock_regenerator_n(struct imx_hdmi *hdmi, - unsigned int value) -{ - hdmi_writeb(hdmi, value & 0xff, HDMI_AUD_N1); - hdmi_writeb(hdmi, (value >> 8) & 0xff, HDMI_AUD_N2); - hdmi_writeb(hdmi, (value >> 16) & 0x0f, HDMI_AUD_N3); - - /* nshift factor = 0 */ - hdmi_modb(hdmi, 0, HDMI_AUD_CTS3_N_SHIFT_MASK, HDMI_AUD_CTS3); -} - -static void hdmi_regenerate_cts(struct imx_hdmi *hdmi, unsigned int cts) -{ - /* Must be set/cleared first */ - hdmi_modb(hdmi, 0, HDMI_AUD_CTS3_CTS_MANUAL, HDMI_AUD_CTS3); - - hdmi_writeb(hdmi, cts & 0xff, HDMI_AUD_CTS1); - hdmi_writeb(hdmi, (cts >> 8) & 0xff, HDMI_AUD_CTS2); - hdmi_writeb(hdmi, ((cts >> 16) & HDMI_AUD_CTS3_AUDCTS19_16_MASK) | - HDMI_AUD_CTS3_CTS_MANUAL, HDMI_AUD_CTS3); -} - -static unsigned int hdmi_compute_n(unsigned int freq, unsigned long pixel_clk, - unsigned int ratio) -{ - unsigned int n = (128 * freq) / 1000; - - switch (freq) { - case 32000: - if (pixel_clk == 25170000) - n = (ratio == 150) ? 9152 : 4576; - else if (pixel_clk == 27020000) - n = (ratio == 150) ? 8192 : 4096; - else if (pixel_clk == 74170000 || pixel_clk == 148350000) - n = 11648; - else - n = 4096; - break; - - case 44100: - if (pixel_clk == 25170000) - n = 7007; - else if (pixel_clk == 74170000) - n = 17836; - else if (pixel_clk == 148350000) - n = (ratio == 150) ? 17836 : 8918; - else - n = 6272; - break; - - case 48000: - if (pixel_clk == 25170000) - n = (ratio == 150) ? 9152 : 6864; - else if (pixel_clk == 27020000) - n = (ratio == 150) ? 8192 : 6144; - else if (pixel_clk == 74170000) - n = 11648; - else if (pixel_clk == 148350000) - n = (ratio == 150) ? 11648 : 5824; - else - n = 6144; - break; - - case 88200: - n = hdmi_compute_n(44100, pixel_clk, ratio) * 2; - break; - - case 96000: - n = hdmi_compute_n(48000, pixel_clk, ratio) * 2; - break; - - case 176400: - n = hdmi_compute_n(44100, pixel_clk, ratio) * 4; - break; - - case 192000: - n = hdmi_compute_n(48000, pixel_clk, ratio) * 4; - break; - - default: - break; - } - - return n; -} - -static unsigned int hdmi_compute_cts(unsigned int freq, unsigned long pixel_clk, - unsigned int ratio) -{ - unsigned int cts = 0; - - pr_debug("%s: freq: %d pixel_clk: %ld ratio: %d\n", __func__, freq, - pixel_clk, ratio); - - switch (freq) { - case 32000: - if (pixel_clk == 297000000) { - cts = 222750; - break; - } - case 48000: - case 96000: - case 192000: - switch (pixel_clk) { - case 25200000: - case 27000000: - case 54000000: - case 74250000: - case 148500000: - cts = pixel_clk / 1000; - break; - case 297000000: - cts = 247500; - break; - /* - * All other TMDS clocks are not supported by - * DWC_hdmi_tx. The TMDS clocks divided or - * multiplied by 1,001 coefficients are not - * supported. - */ - default: - break; - } - break; - case 44100: - case 88200: - case 176400: - switch (pixel_clk) { - case 25200000: - cts = 28000; - break; - case 27000000: - cts = 30000; - break; - case 54000000: - cts = 60000; - break; - case 74250000: - cts = 82500; - break; - case 148500000: - cts = 165000; - break; - case 297000000: - cts = 247500; - break; - default: - break; - } - break; - default: - break; - } - if (ratio == 100) - return cts; - return (cts * ratio) / 100; -} - -static void hdmi_set_clk_regenerator(struct imx_hdmi *hdmi, - unsigned long pixel_clk) -{ - unsigned int clk_n, clk_cts; - - clk_n = hdmi_compute_n(hdmi->sample_rate, pixel_clk, - hdmi->ratio); - clk_cts = hdmi_compute_cts(hdmi->sample_rate, pixel_clk, - hdmi->ratio); - - if (!clk_cts) { - dev_dbg(hdmi->dev, "%s: pixel clock not supported: %lu\n", - __func__, pixel_clk); - return; - } - - dev_dbg(hdmi->dev, "%s: samplerate=%d ratio=%d pixelclk=%lu N=%d cts=%d\n", - __func__, hdmi->sample_rate, hdmi->ratio, - pixel_clk, clk_n, clk_cts); - - hdmi_set_clock_regenerator_n(hdmi, clk_n); - hdmi_regenerate_cts(hdmi, clk_cts); -} - -static void hdmi_init_clk_regenerator(struct imx_hdmi *hdmi) -{ - hdmi_set_clk_regenerator(hdmi, 74250000); -} - -static void hdmi_clk_regenerator_update_pixel_clock(struct imx_hdmi *hdmi) -{ - hdmi_set_clk_regenerator(hdmi, hdmi->hdmi_data.video_mode.mpixelclock); -} - -/* - * this submodule is responsible for the video data synchronization. - * for example, for RGB 4:4:4 input, the data map is defined as - * pin{47~40} <==> R[7:0] - * pin{31~24} <==> G[7:0] - * pin{15~8} <==> B[7:0] - */ -static void hdmi_video_sample(struct imx_hdmi *hdmi) -{ - int color_format = 0; - u8 val; - - if (hdmi->hdmi_data.enc_in_format == RGB) { - if (hdmi->hdmi_data.enc_color_depth == 8) - color_format = 0x01; - else if (hdmi->hdmi_data.enc_color_depth == 10) - color_format = 0x03; - else if (hdmi->hdmi_data.enc_color_depth == 12) - color_format = 0x05; - else if (hdmi->hdmi_data.enc_color_depth == 16) - color_format = 0x07; - else - return; - } else if (hdmi->hdmi_data.enc_in_format == YCBCR444) { - if (hdmi->hdmi_data.enc_color_depth == 8) - color_format = 0x09; - else if (hdmi->hdmi_data.enc_color_depth == 10) - color_format = 0x0B; - else if (hdmi->hdmi_data.enc_color_depth == 12) - color_format = 0x0D; - else if (hdmi->hdmi_data.enc_color_depth == 16) - color_format = 0x0F; - else - return; - } else if (hdmi->hdmi_data.enc_in_format == YCBCR422_8BITS) { - if (hdmi->hdmi_data.enc_color_depth == 8) - color_format = 0x16; - else if (hdmi->hdmi_data.enc_color_depth == 10) - color_format = 0x14; - else if (hdmi->hdmi_data.enc_color_depth == 12) - color_format = 0x12; - else - return; - } - - val = HDMI_TX_INVID0_INTERNAL_DE_GENERATOR_DISABLE | - ((color_format << HDMI_TX_INVID0_VIDEO_MAPPING_OFFSET) & - HDMI_TX_INVID0_VIDEO_MAPPING_MASK); - hdmi_writeb(hdmi, val, HDMI_TX_INVID0); - - /* Enable TX stuffing: When DE is inactive, fix the output data to 0 */ - val = HDMI_TX_INSTUFFING_BDBDATA_STUFFING_ENABLE | - HDMI_TX_INSTUFFING_RCRDATA_STUFFING_ENABLE | - HDMI_TX_INSTUFFING_GYDATA_STUFFING_ENABLE; - hdmi_writeb(hdmi, val, HDMI_TX_INSTUFFING); - hdmi_writeb(hdmi, 0x0, HDMI_TX_GYDATA0); - hdmi_writeb(hdmi, 0x0, HDMI_TX_GYDATA1); - hdmi_writeb(hdmi, 0x0, HDMI_TX_RCRDATA0); - hdmi_writeb(hdmi, 0x0, HDMI_TX_RCRDATA1); - hdmi_writeb(hdmi, 0x0, HDMI_TX_BCBDATA0); - hdmi_writeb(hdmi, 0x0, HDMI_TX_BCBDATA1); -} - -static int is_color_space_conversion(struct imx_hdmi *hdmi) -{ - return hdmi->hdmi_data.enc_in_format != hdmi->hdmi_data.enc_out_format; -} - -static int is_color_space_decimation(struct imx_hdmi *hdmi) -{ - if (hdmi->hdmi_data.enc_out_format != YCBCR422_8BITS) - return 0; - if (hdmi->hdmi_data.enc_in_format == RGB || - hdmi->hdmi_data.enc_in_format == YCBCR444) - return 1; - return 0; -} - -static int is_color_space_interpolation(struct imx_hdmi *hdmi) -{ - if (hdmi->hdmi_data.enc_in_format != YCBCR422_8BITS) - return 0; - if (hdmi->hdmi_data.enc_out_format == RGB || - hdmi->hdmi_data.enc_out_format == YCBCR444) - return 1; - return 0; -} - -static void imx_hdmi_update_csc_coeffs(struct imx_hdmi *hdmi) -{ - const u16 (*csc_coeff)[3][4] = &csc_coeff_default; - unsigned i; - u32 csc_scale = 1; - - if (is_color_space_conversion(hdmi)) { - if (hdmi->hdmi_data.enc_out_format == RGB) { - if (hdmi->hdmi_data.colorimetry == - HDMI_COLORIMETRY_ITU_601) - csc_coeff = &csc_coeff_rgb_out_eitu601; - else - csc_coeff = &csc_coeff_rgb_out_eitu709; - } else if (hdmi->hdmi_data.enc_in_format == RGB) { - if (hdmi->hdmi_data.colorimetry == - HDMI_COLORIMETRY_ITU_601) - csc_coeff = &csc_coeff_rgb_in_eitu601; - else - csc_coeff = &csc_coeff_rgb_in_eitu709; - csc_scale = 0; - } - } - - /* The CSC registers are sequential, alternating MSB then LSB */ - for (i = 0; i < ARRAY_SIZE(csc_coeff_default[0]); i++) { - u16 coeff_a = (*csc_coeff)[0][i]; - u16 coeff_b = (*csc_coeff)[1][i]; - u16 coeff_c = (*csc_coeff)[2][i]; - - hdmi_writeb(hdmi, coeff_a & 0xff, - HDMI_CSC_COEF_A1_LSB + i * 2); - hdmi_writeb(hdmi, coeff_a >> 8, HDMI_CSC_COEF_A1_MSB + i * 2); - hdmi_writeb(hdmi, coeff_b & 0xff, HDMI_CSC_COEF_B1_LSB + i * 2); - hdmi_writeb(hdmi, coeff_b >> 8, HDMI_CSC_COEF_B1_MSB + i * 2); - hdmi_writeb(hdmi, coeff_c & 0xff, - HDMI_CSC_COEF_C1_LSB + i * 2); - hdmi_writeb(hdmi, coeff_c >> 8, HDMI_CSC_COEF_C1_MSB + i * 2); - } - - hdmi_modb(hdmi, csc_scale, HDMI_CSC_SCALE_CSCSCALE_MASK, - HDMI_CSC_SCALE); -} - -static void hdmi_video_csc(struct imx_hdmi *hdmi) -{ - int color_depth = 0; - int interpolation = HDMI_CSC_CFG_INTMODE_DISABLE; - int decimation = 0; - - /* YCC422 interpolation to 444 mode */ - if (is_color_space_interpolation(hdmi)) - interpolation = HDMI_CSC_CFG_INTMODE_CHROMA_INT_FORMULA1; - else if (is_color_space_decimation(hdmi)) - decimation = HDMI_CSC_CFG_DECMODE_CHROMA_INT_FORMULA3; - - if (hdmi->hdmi_data.enc_color_depth == 8) - color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_24BPP; - else if (hdmi->hdmi_data.enc_color_depth == 10) - color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_30BPP; - else if (hdmi->hdmi_data.enc_color_depth == 12) - color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_36BPP; - else if (hdmi->hdmi_data.enc_color_depth == 16) - color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_48BPP; - else - return; - - /* Configure the CSC registers */ - hdmi_writeb(hdmi, interpolation | decimation, HDMI_CSC_CFG); - hdmi_modb(hdmi, color_depth, HDMI_CSC_SCALE_CSC_COLORDE_PTH_MASK, - HDMI_CSC_SCALE); - - imx_hdmi_update_csc_coeffs(hdmi); -} - -/* - * HDMI video packetizer is used to packetize the data. - * for example, if input is YCC422 mode or repeater is used, - * data should be repacked this module can be bypassed. - */ -static void hdmi_video_packetize(struct imx_hdmi *hdmi) -{ - unsigned int color_depth = 0; - unsigned int remap_size = HDMI_VP_REMAP_YCC422_16bit; - unsigned int output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_PP; - struct hdmi_data_info *hdmi_data = &hdmi->hdmi_data; - u8 val, vp_conf; - - if (hdmi_data->enc_out_format == RGB - || hdmi_data->enc_out_format == YCBCR444) { - if (!hdmi_data->enc_color_depth) - output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS; - else if (hdmi_data->enc_color_depth == 8) { - color_depth = 4; - output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS; - } else if (hdmi_data->enc_color_depth == 10) - color_depth = 5; - else if (hdmi_data->enc_color_depth == 12) - color_depth = 6; - else if (hdmi_data->enc_color_depth == 16) - color_depth = 7; - else - return; - } else if (hdmi_data->enc_out_format == YCBCR422_8BITS) { - if (!hdmi_data->enc_color_depth || - hdmi_data->enc_color_depth == 8) - remap_size = HDMI_VP_REMAP_YCC422_16bit; - else if (hdmi_data->enc_color_depth == 10) - remap_size = HDMI_VP_REMAP_YCC422_20bit; - else if (hdmi_data->enc_color_depth == 12) - remap_size = HDMI_VP_REMAP_YCC422_24bit; - else - return; - output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_YCC422; - } else - return; - - /* set the packetizer registers */ - val = ((color_depth << HDMI_VP_PR_CD_COLOR_DEPTH_OFFSET) & - HDMI_VP_PR_CD_COLOR_DEPTH_MASK) | - ((hdmi_data->pix_repet_factor << - HDMI_VP_PR_CD_DESIRED_PR_FACTOR_OFFSET) & - HDMI_VP_PR_CD_DESIRED_PR_FACTOR_MASK); - hdmi_writeb(hdmi, val, HDMI_VP_PR_CD); - - hdmi_modb(hdmi, HDMI_VP_STUFF_PR_STUFFING_STUFFING_MODE, - HDMI_VP_STUFF_PR_STUFFING_MASK, HDMI_VP_STUFF); - - /* Data from pixel repeater block */ - if (hdmi_data->pix_repet_factor > 1) { - vp_conf = HDMI_VP_CONF_PR_EN_ENABLE | - HDMI_VP_CONF_BYPASS_SELECT_PIX_REPEATER; - } else { /* data from packetizer block */ - vp_conf = HDMI_VP_CONF_PR_EN_DISABLE | - HDMI_VP_CONF_BYPASS_SELECT_VID_PACKETIZER; - } - - hdmi_modb(hdmi, vp_conf, - HDMI_VP_CONF_PR_EN_MASK | - HDMI_VP_CONF_BYPASS_SELECT_MASK, HDMI_VP_CONF); - - hdmi_modb(hdmi, 1 << HDMI_VP_STUFF_IDEFAULT_PHASE_OFFSET, - HDMI_VP_STUFF_IDEFAULT_PHASE_MASK, HDMI_VP_STUFF); - - hdmi_writeb(hdmi, remap_size, HDMI_VP_REMAP); - - if (output_select == HDMI_VP_CONF_OUTPUT_SELECTOR_PP) { - vp_conf = HDMI_VP_CONF_BYPASS_EN_DISABLE | - HDMI_VP_CONF_PP_EN_ENABLE | - HDMI_VP_CONF_YCC422_EN_DISABLE; - } else if (output_select == HDMI_VP_CONF_OUTPUT_SELECTOR_YCC422) { - vp_conf = HDMI_VP_CONF_BYPASS_EN_DISABLE | - HDMI_VP_CONF_PP_EN_DISABLE | - HDMI_VP_CONF_YCC422_EN_ENABLE; - } else if (output_select == HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS) { - vp_conf = HDMI_VP_CONF_BYPASS_EN_ENABLE | - HDMI_VP_CONF_PP_EN_DISABLE | - HDMI_VP_CONF_YCC422_EN_DISABLE; - } else { - return; - } - - hdmi_modb(hdmi, vp_conf, - HDMI_VP_CONF_BYPASS_EN_MASK | HDMI_VP_CONF_PP_EN_ENMASK | - HDMI_VP_CONF_YCC422_EN_MASK, HDMI_VP_CONF); - - hdmi_modb(hdmi, HDMI_VP_STUFF_PP_STUFFING_STUFFING_MODE | - HDMI_VP_STUFF_YCC422_STUFFING_STUFFING_MODE, - HDMI_VP_STUFF_PP_STUFFING_MASK | - HDMI_VP_STUFF_YCC422_STUFFING_MASK, HDMI_VP_STUFF); - - hdmi_modb(hdmi, output_select, HDMI_VP_CONF_OUTPUT_SELECTOR_MASK, - HDMI_VP_CONF); -} - -static inline void hdmi_phy_test_clear(struct imx_hdmi *hdmi, - unsigned char bit) -{ - hdmi_modb(hdmi, bit << HDMI_PHY_TST0_TSTCLR_OFFSET, - HDMI_PHY_TST0_TSTCLR_MASK, HDMI_PHY_TST0); -} - -static inline void hdmi_phy_test_enable(struct imx_hdmi *hdmi, - unsigned char bit) -{ - hdmi_modb(hdmi, bit << HDMI_PHY_TST0_TSTEN_OFFSET, - HDMI_PHY_TST0_TSTEN_MASK, HDMI_PHY_TST0); -} - -static inline void hdmi_phy_test_clock(struct imx_hdmi *hdmi, - unsigned char bit) -{ - hdmi_modb(hdmi, bit << HDMI_PHY_TST0_TSTCLK_OFFSET, - HDMI_PHY_TST0_TSTCLK_MASK, HDMI_PHY_TST0); -} - -static inline void hdmi_phy_test_din(struct imx_hdmi *hdmi, - unsigned char bit) -{ - hdmi_writeb(hdmi, bit, HDMI_PHY_TST1); -} - -static inline void hdmi_phy_test_dout(struct imx_hdmi *hdmi, - unsigned char bit) -{ - hdmi_writeb(hdmi, bit, HDMI_PHY_TST2); -} - -static bool hdmi_phy_wait_i2c_done(struct imx_hdmi *hdmi, int msec) -{ - while ((hdmi_readb(hdmi, HDMI_IH_I2CMPHY_STAT0) & 0x3) == 0) { - if (msec-- == 0) - return false; - udelay(1000); - } - return true; -} - -static void __hdmi_phy_i2c_write(struct imx_hdmi *hdmi, unsigned short data, - unsigned char addr) -{ - hdmi_writeb(hdmi, 0xFF, HDMI_IH_I2CMPHY_STAT0); - hdmi_writeb(hdmi, addr, HDMI_PHY_I2CM_ADDRESS_ADDR); - hdmi_writeb(hdmi, (unsigned char)(data >> 8), - HDMI_PHY_I2CM_DATAO_1_ADDR); - hdmi_writeb(hdmi, (unsigned char)(data >> 0), - HDMI_PHY_I2CM_DATAO_0_ADDR); - hdmi_writeb(hdmi, HDMI_PHY_I2CM_OPERATION_ADDR_WRITE, - HDMI_PHY_I2CM_OPERATION_ADDR); - hdmi_phy_wait_i2c_done(hdmi, 1000); -} - -static int hdmi_phy_i2c_write(struct imx_hdmi *hdmi, unsigned short data, - unsigned char addr) -{ - __hdmi_phy_i2c_write(hdmi, data, addr); - return 0; -} - -static void imx_hdmi_phy_enable_power(struct imx_hdmi *hdmi, u8 enable) -{ - hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0, - HDMI_PHY_CONF0_PDZ_OFFSET, - HDMI_PHY_CONF0_PDZ_MASK); -} - -static void imx_hdmi_phy_enable_tmds(struct imx_hdmi *hdmi, u8 enable) -{ - hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0, - HDMI_PHY_CONF0_ENTMDS_OFFSET, - HDMI_PHY_CONF0_ENTMDS_MASK); -} - -static void imx_hdmi_phy_gen2_pddq(struct imx_hdmi *hdmi, u8 enable) -{ - hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0, - HDMI_PHY_CONF0_GEN2_PDDQ_OFFSET, - HDMI_PHY_CONF0_GEN2_PDDQ_MASK); -} - -static void imx_hdmi_phy_gen2_txpwron(struct imx_hdmi *hdmi, u8 enable) -{ - hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0, - HDMI_PHY_CONF0_GEN2_TXPWRON_OFFSET, - HDMI_PHY_CONF0_GEN2_TXPWRON_MASK); -} - -static void imx_hdmi_phy_sel_data_en_pol(struct imx_hdmi *hdmi, u8 enable) -{ - hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0, - HDMI_PHY_CONF0_SELDATAENPOL_OFFSET, - HDMI_PHY_CONF0_SELDATAENPOL_MASK); -} - -static void imx_hdmi_phy_sel_interface_control(struct imx_hdmi *hdmi, u8 enable) -{ - hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0, - HDMI_PHY_CONF0_SELDIPIF_OFFSET, - HDMI_PHY_CONF0_SELDIPIF_MASK); -} - -enum { - RES_8, - RES_10, - RES_12, - RES_MAX, -}; - -struct mpll_config { - unsigned long mpixelclock; - struct { - u16 cpce; - u16 gmp; - } res[RES_MAX]; -}; - -static const struct mpll_config mpll_config[] = { - { - 45250000, { - { 0x01e0, 0x0000 }, - { 0x21e1, 0x0000 }, - { 0x41e2, 0x0000 } - }, - }, { - 92500000, { - { 0x0140, 0x0005 }, - { 0x2141, 0x0005 }, - { 0x4142, 0x0005 }, - }, - }, { - 148500000, { - { 0x00a0, 0x000a }, - { 0x20a1, 0x000a }, - { 0x40a2, 0x000a }, - }, - }, { - ~0UL, { - { 0x00a0, 0x000a }, - { 0x2001, 0x000f }, - { 0x4002, 0x000f }, - }, - } -}; - -struct curr_ctrl { - unsigned long mpixelclock; - u16 curr[RES_MAX]; -}; - -static const struct curr_ctrl curr_ctrl[] = { - /* pixelclk bpp8 bpp10 bpp12 */ - { - 54000000, { 0x091c, 0x091c, 0x06dc }, - }, { - 58400000, { 0x091c, 0x06dc, 0x06dc }, - }, { - 72000000, { 0x06dc, 0x06dc, 0x091c }, - }, { - 74250000, { 0x06dc, 0x0b5c, 0x091c }, - }, { - 118800000, { 0x091c, 0x091c, 0x06dc }, - }, { - 216000000, { 0x06dc, 0x0b5c, 0x091c }, - } -}; - -static int hdmi_phy_configure(struct imx_hdmi *hdmi, unsigned char prep, - unsigned char res, int cscon) -{ - unsigned res_idx, i; - u8 val, msec; - - if (prep) - return -EINVAL; - - switch (res) { - case 0: /* color resolution 0 is 8 bit colour depth */ - case 8: - res_idx = RES_8; - break; - case 10: - res_idx = RES_10; - break; - case 12: - res_idx = RES_12; - break; - default: - return -EINVAL; - } - - /* Enable csc path */ - if (cscon) - val = HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_CSC_IN_PATH; - else - val = HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_CSC_BYPASS; - - hdmi_writeb(hdmi, val, HDMI_MC_FLOWCTRL); - - /* gen2 tx power off */ - imx_hdmi_phy_gen2_txpwron(hdmi, 0); - - /* gen2 pddq */ - imx_hdmi_phy_gen2_pddq(hdmi, 1); - - /* PHY reset */ - hdmi_writeb(hdmi, HDMI_MC_PHYRSTZ_DEASSERT, HDMI_MC_PHYRSTZ); - hdmi_writeb(hdmi, HDMI_MC_PHYRSTZ_ASSERT, HDMI_MC_PHYRSTZ); - - hdmi_writeb(hdmi, HDMI_MC_HEACPHY_RST_ASSERT, HDMI_MC_HEACPHY_RST); - - hdmi_phy_test_clear(hdmi, 1); - hdmi_writeb(hdmi, HDMI_PHY_I2CM_SLAVE_ADDR_PHY_GEN2, - HDMI_PHY_I2CM_SLAVE_ADDR); - hdmi_phy_test_clear(hdmi, 0); - - /* PLL/MPLL Cfg - always match on final entry */ - for (i = 0; i < ARRAY_SIZE(mpll_config) - 1; i++) - if (hdmi->hdmi_data.video_mode.mpixelclock <= - mpll_config[i].mpixelclock) - break; - - hdmi_phy_i2c_write(hdmi, mpll_config[i].res[res_idx].cpce, 0x06); - hdmi_phy_i2c_write(hdmi, mpll_config[i].res[res_idx].gmp, 0x15); - - for (i = 0; i < ARRAY_SIZE(curr_ctrl); i++) - if (hdmi->hdmi_data.video_mode.mpixelclock <= - curr_ctrl[i].mpixelclock) - break; - - if (i >= ARRAY_SIZE(curr_ctrl)) { - dev_err(hdmi->dev, - "Pixel clock %d - unsupported by HDMI\n", - hdmi->hdmi_data.video_mode.mpixelclock); - return -EINVAL; - } - - /* CURRCTRL */ - hdmi_phy_i2c_write(hdmi, curr_ctrl[i].curr[res_idx], 0x10); - - hdmi_phy_i2c_write(hdmi, 0x0000, 0x13); /* PLLPHBYCTRL */ - hdmi_phy_i2c_write(hdmi, 0x0006, 0x17); - /* RESISTANCE TERM 133Ohm Cfg */ - hdmi_phy_i2c_write(hdmi, 0x0005, 0x19); /* TXTERM */ - /* PREEMP Cgf 0.00 */ - hdmi_phy_i2c_write(hdmi, 0x800d, 0x09); /* CKSYMTXCTRL */ - /* TX/CK LVL 10 */ - hdmi_phy_i2c_write(hdmi, 0x01ad, 0x0E); /* VLEVCTRL */ - /* REMOVE CLK TERM */ - hdmi_phy_i2c_write(hdmi, 0x8000, 0x05); /* CKCALCTRL */ - - imx_hdmi_phy_enable_power(hdmi, 1); - - /* toggle TMDS enable */ - imx_hdmi_phy_enable_tmds(hdmi, 0); - imx_hdmi_phy_enable_tmds(hdmi, 1); - - /* gen2 tx power on */ - imx_hdmi_phy_gen2_txpwron(hdmi, 1); - imx_hdmi_phy_gen2_pddq(hdmi, 0); - - /*Wait for PHY PLL lock */ - msec = 5; - do { - val = hdmi_readb(hdmi, HDMI_PHY_STAT0) & HDMI_PHY_TX_PHY_LOCK; - if (!val) - break; - - if (msec == 0) { - dev_err(hdmi->dev, "PHY PLL not locked\n"); - return -ETIMEDOUT; - } - - udelay(1000); - msec--; - } while (1); - - return 0; -} - -static int imx_hdmi_phy_init(struct imx_hdmi *hdmi) -{ - int i, ret; - bool cscon = false; - - /*check csc whether needed activated in HDMI mode */ - cscon = (is_color_space_conversion(hdmi) && - !hdmi->hdmi_data.video_mode.mdvi); - - /* HDMI Phy spec says to do the phy initialization sequence twice */ - for (i = 0; i < 2; i++) { - imx_hdmi_phy_sel_data_en_pol(hdmi, 1); - imx_hdmi_phy_sel_interface_control(hdmi, 0); - imx_hdmi_phy_enable_tmds(hdmi, 0); - imx_hdmi_phy_enable_power(hdmi, 0); - - /* Enable CSC */ - ret = hdmi_phy_configure(hdmi, 0, 8, cscon); - if (ret) - return ret; - } - - hdmi->phy_enabled = true; - return 0; -} - -static void hdmi_tx_hdcp_config(struct imx_hdmi *hdmi) -{ - u8 de; - - if (hdmi->hdmi_data.video_mode.mdataenablepolarity) - de = HDMI_A_VIDPOLCFG_DATAENPOL_ACTIVE_HIGH; - else - de = HDMI_A_VIDPOLCFG_DATAENPOL_ACTIVE_LOW; - - /* disable rx detect */ - hdmi_modb(hdmi, HDMI_A_HDCPCFG0_RXDETECT_DISABLE, - HDMI_A_HDCPCFG0_RXDETECT_MASK, HDMI_A_HDCPCFG0); - - hdmi_modb(hdmi, de, HDMI_A_VIDPOLCFG_DATAENPOL_MASK, HDMI_A_VIDPOLCFG); - - hdmi_modb(hdmi, HDMI_A_HDCPCFG1_ENCRYPTIONDISABLE_DISABLE, - HDMI_A_HDCPCFG1_ENCRYPTIONDISABLE_MASK, HDMI_A_HDCPCFG1); -} - -static void hdmi_config_AVI(struct imx_hdmi *hdmi) -{ - u8 val, pix_fmt, under_scan; - u8 act_ratio, coded_ratio, colorimetry, ext_colorimetry; - bool aspect_16_9; - - aspect_16_9 = false; /* FIXME */ - - /* AVI Data Byte 1 */ - if (hdmi->hdmi_data.enc_out_format == YCBCR444) - pix_fmt = HDMI_FC_AVICONF0_PIX_FMT_YCBCR444; - else if (hdmi->hdmi_data.enc_out_format == YCBCR422_8BITS) - pix_fmt = HDMI_FC_AVICONF0_PIX_FMT_YCBCR422; - else - pix_fmt = HDMI_FC_AVICONF0_PIX_FMT_RGB; - - under_scan = HDMI_FC_AVICONF0_SCAN_INFO_NODATA; - - /* - * Active format identification data is present in the AVI InfoFrame. - * Under scan info, no bar data - */ - val = pix_fmt | under_scan | - HDMI_FC_AVICONF0_ACTIVE_FMT_INFO_PRESENT | - HDMI_FC_AVICONF0_BAR_DATA_NO_DATA; - - hdmi_writeb(hdmi, val, HDMI_FC_AVICONF0); - - /* AVI Data Byte 2 -Set the Aspect Ratio */ - if (aspect_16_9) { - act_ratio = HDMI_FC_AVICONF1_ACTIVE_ASPECT_RATIO_16_9; - coded_ratio = HDMI_FC_AVICONF1_CODED_ASPECT_RATIO_16_9; - } else { - act_ratio = HDMI_FC_AVICONF1_ACTIVE_ASPECT_RATIO_4_3; - coded_ratio = HDMI_FC_AVICONF1_CODED_ASPECT_RATIO_4_3; - } - - /* Set up colorimetry */ - if (hdmi->hdmi_data.enc_out_format == XVYCC444) { - colorimetry = HDMI_FC_AVICONF1_COLORIMETRY_EXTENDED_INFO; - if (hdmi->hdmi_data.colorimetry == HDMI_COLORIMETRY_ITU_601) - ext_colorimetry = - HDMI_FC_AVICONF2_EXT_COLORIMETRY_XVYCC601; - else /*hdmi->hdmi_data.colorimetry == HDMI_COLORIMETRY_ITU_709*/ - ext_colorimetry = - HDMI_FC_AVICONF2_EXT_COLORIMETRY_XVYCC709; - } else if (hdmi->hdmi_data.enc_out_format != RGB) { - if (hdmi->hdmi_data.colorimetry == HDMI_COLORIMETRY_ITU_601) - colorimetry = HDMI_FC_AVICONF1_COLORIMETRY_SMPTE; - else /*hdmi->hdmi_data.colorimetry == HDMI_COLORIMETRY_ITU_709*/ - colorimetry = HDMI_FC_AVICONF1_COLORIMETRY_ITUR; - ext_colorimetry = HDMI_FC_AVICONF2_EXT_COLORIMETRY_XVYCC601; - } else { /* Carries no data */ - colorimetry = HDMI_FC_AVICONF1_COLORIMETRY_NO_DATA; - ext_colorimetry = HDMI_FC_AVICONF2_EXT_COLORIMETRY_XVYCC601; - } - - val = colorimetry | coded_ratio | act_ratio; - hdmi_writeb(hdmi, val, HDMI_FC_AVICONF1); - - /* AVI Data Byte 3 */ - val = HDMI_FC_AVICONF2_IT_CONTENT_NO_DATA | ext_colorimetry | - HDMI_FC_AVICONF2_RGB_QUANT_DEFAULT | - HDMI_FC_AVICONF2_SCALING_NONE; - hdmi_writeb(hdmi, val, HDMI_FC_AVICONF2); - - /* AVI Data Byte 4 */ - hdmi_writeb(hdmi, hdmi->vic, HDMI_FC_AVIVID); - - /* AVI Data Byte 5- set up input and output pixel repetition */ - val = (((hdmi->hdmi_data.video_mode.mpixelrepetitioninput + 1) << - HDMI_FC_PRCONF_INCOMING_PR_FACTOR_OFFSET) & - HDMI_FC_PRCONF_INCOMING_PR_FACTOR_MASK) | - ((hdmi->hdmi_data.video_mode.mpixelrepetitionoutput << - HDMI_FC_PRCONF_OUTPUT_PR_FACTOR_OFFSET) & - HDMI_FC_PRCONF_OUTPUT_PR_FACTOR_MASK); - hdmi_writeb(hdmi, val, HDMI_FC_PRCONF); - - /* IT Content and quantization range = don't care */ - val = HDMI_FC_AVICONF3_IT_CONTENT_TYPE_GRAPHICS | - HDMI_FC_AVICONF3_QUANT_RANGE_LIMITED; - hdmi_writeb(hdmi, val, HDMI_FC_AVICONF3); - - /* AVI Data Bytes 6-13 */ - hdmi_writeb(hdmi, 0, HDMI_FC_AVIETB0); - hdmi_writeb(hdmi, 0, HDMI_FC_AVIETB1); - hdmi_writeb(hdmi, 0, HDMI_FC_AVISBB0); - hdmi_writeb(hdmi, 0, HDMI_FC_AVISBB1); - hdmi_writeb(hdmi, 0, HDMI_FC_AVIELB0); - hdmi_writeb(hdmi, 0, HDMI_FC_AVIELB1); - hdmi_writeb(hdmi, 0, HDMI_FC_AVISRB0); - hdmi_writeb(hdmi, 0, HDMI_FC_AVISRB1); -} - -static void hdmi_av_composer(struct imx_hdmi *hdmi, - const struct drm_display_mode *mode) -{ - u8 inv_val; - struct hdmi_vmode *vmode = &hdmi->hdmi_data.video_mode; - int hblank, vblank, h_de_hs, v_de_vs, hsync_len, vsync_len; - - vmode->mhsyncpolarity = !!(mode->flags & DRM_MODE_FLAG_PHSYNC); - vmode->mvsyncpolarity = !!(mode->flags & DRM_MODE_FLAG_PVSYNC); - vmode->minterlaced = !!(mode->flags & DRM_MODE_FLAG_INTERLACE); - vmode->mpixelclock = mode->clock * 1000; - - dev_dbg(hdmi->dev, "final pixclk = %d\n", vmode->mpixelclock); - - /* Set up HDMI_FC_INVIDCONF */ - inv_val = (hdmi->hdmi_data.hdcp_enable ? - HDMI_FC_INVIDCONF_HDCP_KEEPOUT_ACTIVE : - HDMI_FC_INVIDCONF_HDCP_KEEPOUT_INACTIVE); - - inv_val |= (vmode->mvsyncpolarity ? - HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_ACTIVE_HIGH : - HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_ACTIVE_LOW); - - inv_val |= (vmode->mhsyncpolarity ? - HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_ACTIVE_HIGH : - HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_ACTIVE_LOW); - - inv_val |= (vmode->mdataenablepolarity ? - HDMI_FC_INVIDCONF_DE_IN_POLARITY_ACTIVE_HIGH : - HDMI_FC_INVIDCONF_DE_IN_POLARITY_ACTIVE_LOW); - - if (hdmi->vic == 39) - inv_val |= HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_HIGH; - else - inv_val |= (vmode->minterlaced ? - HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_HIGH : - HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_LOW); - - inv_val |= (vmode->minterlaced ? - HDMI_FC_INVIDCONF_IN_I_P_INTERLACED : - HDMI_FC_INVIDCONF_IN_I_P_PROGRESSIVE); - - inv_val |= (vmode->mdvi ? - HDMI_FC_INVIDCONF_DVI_MODEZ_DVI_MODE : - HDMI_FC_INVIDCONF_DVI_MODEZ_HDMI_MODE); - - hdmi_writeb(hdmi, inv_val, HDMI_FC_INVIDCONF); - - /* Set up horizontal active pixel width */ - hdmi_writeb(hdmi, mode->hdisplay >> 8, HDMI_FC_INHACTV1); - hdmi_writeb(hdmi, mode->hdisplay, HDMI_FC_INHACTV0); - - /* Set up vertical active lines */ - hdmi_writeb(hdmi, mode->vdisplay >> 8, HDMI_FC_INVACTV1); - hdmi_writeb(hdmi, mode->vdisplay, HDMI_FC_INVACTV0); - - /* Set up horizontal blanking pixel region width */ - hblank = mode->htotal - mode->hdisplay; - hdmi_writeb(hdmi, hblank >> 8, HDMI_FC_INHBLANK1); - hdmi_writeb(hdmi, hblank, HDMI_FC_INHBLANK0); - - /* Set up vertical blanking pixel region width */ - vblank = mode->vtotal - mode->vdisplay; - hdmi_writeb(hdmi, vblank, HDMI_FC_INVBLANK); - - /* Set up HSYNC active edge delay width (in pixel clks) */ - h_de_hs = mode->hsync_start - mode->hdisplay; - hdmi_writeb(hdmi, h_de_hs >> 8, HDMI_FC_HSYNCINDELAY1); - hdmi_writeb(hdmi, h_de_hs, HDMI_FC_HSYNCINDELAY0); - - /* Set up VSYNC active edge delay (in lines) */ - v_de_vs = mode->vsync_start - mode->vdisplay; - hdmi_writeb(hdmi, v_de_vs, HDMI_FC_VSYNCINDELAY); - - /* Set up HSYNC active pulse width (in pixel clks) */ - hsync_len = mode->hsync_end - mode->hsync_start; - hdmi_writeb(hdmi, hsync_len >> 8, HDMI_FC_HSYNCINWIDTH1); - hdmi_writeb(hdmi, hsync_len, HDMI_FC_HSYNCINWIDTH0); - - /* Set up VSYNC active edge delay (in lines) */ - vsync_len = mode->vsync_end - mode->vsync_start; - hdmi_writeb(hdmi, vsync_len, HDMI_FC_VSYNCINWIDTH); -} - -static void imx_hdmi_phy_disable(struct imx_hdmi *hdmi) -{ - if (!hdmi->phy_enabled) - return; - - imx_hdmi_phy_enable_tmds(hdmi, 0); - imx_hdmi_phy_enable_power(hdmi, 0); - - hdmi->phy_enabled = false; -} - -/* HDMI Initialization Step B.4 */ -static void imx_hdmi_enable_video_path(struct imx_hdmi *hdmi) -{ - u8 clkdis; - - /* control period minimum duration */ - hdmi_writeb(hdmi, 12, HDMI_FC_CTRLDUR); - hdmi_writeb(hdmi, 32, HDMI_FC_EXCTRLDUR); - hdmi_writeb(hdmi, 1, HDMI_FC_EXCTRLSPAC); - - /* Set to fill TMDS data channels */ - hdmi_writeb(hdmi, 0x0B, HDMI_FC_CH0PREAM); - hdmi_writeb(hdmi, 0x16, HDMI_FC_CH1PREAM); - hdmi_writeb(hdmi, 0x21, HDMI_FC_CH2PREAM); - - /* Enable pixel clock and tmds data path */ - clkdis = 0x7F; - clkdis &= ~HDMI_MC_CLKDIS_PIXELCLK_DISABLE; - hdmi_writeb(hdmi, clkdis, HDMI_MC_CLKDIS); - - clkdis &= ~HDMI_MC_CLKDIS_TMDSCLK_DISABLE; - hdmi_writeb(hdmi, clkdis, HDMI_MC_CLKDIS); - - /* Enable csc path */ - if (is_color_space_conversion(hdmi)) { - clkdis &= ~HDMI_MC_CLKDIS_CSCCLK_DISABLE; - hdmi_writeb(hdmi, clkdis, HDMI_MC_CLKDIS); - } -} - -static void hdmi_enable_audio_clk(struct imx_hdmi *hdmi) -{ - hdmi_modb(hdmi, 0, HDMI_MC_CLKDIS_AUDCLK_DISABLE, HDMI_MC_CLKDIS); -} - -/* Workaround to clear the overflow condition */ -static void imx_hdmi_clear_overflow(struct imx_hdmi *hdmi) -{ - int count; - u8 val; - - /* TMDS software reset */ - hdmi_writeb(hdmi, (u8)~HDMI_MC_SWRSTZ_TMDSSWRST_REQ, HDMI_MC_SWRSTZ); - - val = hdmi_readb(hdmi, HDMI_FC_INVIDCONF); - if (hdmi->dev_type == IMX6DL_HDMI) { - hdmi_writeb(hdmi, val, HDMI_FC_INVIDCONF); - return; - } - - for (count = 0; count < 4; count++) - hdmi_writeb(hdmi, val, HDMI_FC_INVIDCONF); -} - -static void hdmi_enable_overflow_interrupts(struct imx_hdmi *hdmi) -{ - hdmi_writeb(hdmi, 0, HDMI_FC_MASK2); - hdmi_writeb(hdmi, 0, HDMI_IH_MUTE_FC_STAT2); -} - -static void hdmi_disable_overflow_interrupts(struct imx_hdmi *hdmi) -{ - hdmi_writeb(hdmi, HDMI_IH_MUTE_FC_STAT2_OVERFLOW_MASK, - HDMI_IH_MUTE_FC_STAT2); -} - -static int imx_hdmi_setup(struct imx_hdmi *hdmi, struct drm_display_mode *mode) -{ - int ret; - - hdmi_disable_overflow_interrupts(hdmi); - - hdmi->vic = drm_match_cea_mode(mode); - - if (!hdmi->vic) { - dev_dbg(hdmi->dev, "Non-CEA mode used in HDMI\n"); - hdmi->hdmi_data.video_mode.mdvi = true; - } else { - dev_dbg(hdmi->dev, "CEA mode used vic=%d\n", hdmi->vic); - hdmi->hdmi_data.video_mode.mdvi = false; - } - - if ((hdmi->vic == 6) || (hdmi->vic == 7) || - (hdmi->vic == 21) || (hdmi->vic == 22) || - (hdmi->vic == 2) || (hdmi->vic == 3) || - (hdmi->vic == 17) || (hdmi->vic == 18)) - hdmi->hdmi_data.colorimetry = HDMI_COLORIMETRY_ITU_601; - else - hdmi->hdmi_data.colorimetry = HDMI_COLORIMETRY_ITU_709; - - if ((hdmi->vic == 10) || (hdmi->vic == 11) || - (hdmi->vic == 12) || (hdmi->vic == 13) || - (hdmi->vic == 14) || (hdmi->vic == 15) || - (hdmi->vic == 25) || (hdmi->vic == 26) || - (hdmi->vic == 27) || (hdmi->vic == 28) || - (hdmi->vic == 29) || (hdmi->vic == 30) || - (hdmi->vic == 35) || (hdmi->vic == 36) || - (hdmi->vic == 37) || (hdmi->vic == 38)) - hdmi->hdmi_data.video_mode.mpixelrepetitionoutput = 1; - else - hdmi->hdmi_data.video_mode.mpixelrepetitionoutput = 0; - - hdmi->hdmi_data.video_mode.mpixelrepetitioninput = 0; - - /* TODO: Get input format from IPU (via FB driver interface) */ - hdmi->hdmi_data.enc_in_format = RGB; - - hdmi->hdmi_data.enc_out_format = RGB; - - hdmi->hdmi_data.enc_color_depth = 8; - hdmi->hdmi_data.pix_repet_factor = 0; - hdmi->hdmi_data.hdcp_enable = 0; - hdmi->hdmi_data.video_mode.mdataenablepolarity = true; - - /* HDMI Initialization Step B.1 */ - hdmi_av_composer(hdmi, mode); - - /* HDMI Initializateion Step B.2 */ - ret = imx_hdmi_phy_init(hdmi); - if (ret) - return ret; - - /* HDMI Initialization Step B.3 */ - imx_hdmi_enable_video_path(hdmi); - - /* not for DVI mode */ - if (hdmi->hdmi_data.video_mode.mdvi) - dev_dbg(hdmi->dev, "%s DVI mode\n", __func__); - else { - dev_dbg(hdmi->dev, "%s CEA mode\n", __func__); - - /* HDMI Initialization Step E - Configure audio */ - hdmi_clk_regenerator_update_pixel_clock(hdmi); - hdmi_enable_audio_clk(hdmi); - - /* HDMI Initialization Step F - Configure AVI InfoFrame */ - hdmi_config_AVI(hdmi); - } - - hdmi_video_packetize(hdmi); - hdmi_video_csc(hdmi); - hdmi_video_sample(hdmi); - hdmi_tx_hdcp_config(hdmi); - - imx_hdmi_clear_overflow(hdmi); - if (hdmi->cable_plugin && !hdmi->hdmi_data.video_mode.mdvi) - hdmi_enable_overflow_interrupts(hdmi); - - return 0; -} - -/* Wait until we are registered to enable interrupts */ -static int imx_hdmi_fb_registered(struct imx_hdmi *hdmi) -{ - hdmi_writeb(hdmi, HDMI_PHY_I2CM_INT_ADDR_DONE_POL, - HDMI_PHY_I2CM_INT_ADDR); - - hdmi_writeb(hdmi, HDMI_PHY_I2CM_CTLINT_ADDR_NAC_POL | - HDMI_PHY_I2CM_CTLINT_ADDR_ARBITRATION_POL, - HDMI_PHY_I2CM_CTLINT_ADDR); - - /* enable cable hot plug irq */ - hdmi_writeb(hdmi, (u8)~HDMI_PHY_HPD, HDMI_PHY_MASK0); - - /* Clear Hotplug interrupts */ - hdmi_writeb(hdmi, HDMI_IH_PHY_STAT0_HPD, HDMI_IH_PHY_STAT0); - - return 0; -} - -static void initialize_hdmi_ih_mutes(struct imx_hdmi *hdmi) -{ - u8 ih_mute; - - /* - * Boot up defaults are: - * HDMI_IH_MUTE = 0x03 (disabled) - * HDMI_IH_MUTE_* = 0x00 (enabled) - * - * Disable top level interrupt bits in HDMI block - */ - ih_mute = hdmi_readb(hdmi, HDMI_IH_MUTE) | - HDMI_IH_MUTE_MUTE_WAKEUP_INTERRUPT | - HDMI_IH_MUTE_MUTE_ALL_INTERRUPT; - - hdmi_writeb(hdmi, ih_mute, HDMI_IH_MUTE); - - /* by default mask all interrupts */ - hdmi_writeb(hdmi, 0xff, HDMI_VP_MASK); - hdmi_writeb(hdmi, 0xff, HDMI_FC_MASK0); - hdmi_writeb(hdmi, 0xff, HDMI_FC_MASK1); - hdmi_writeb(hdmi, 0xff, HDMI_FC_MASK2); - hdmi_writeb(hdmi, 0xff, HDMI_PHY_MASK0); - hdmi_writeb(hdmi, 0xff, HDMI_PHY_I2CM_INT_ADDR); - hdmi_writeb(hdmi, 0xff, HDMI_PHY_I2CM_CTLINT_ADDR); - hdmi_writeb(hdmi, 0xff, HDMI_AUD_INT); - hdmi_writeb(hdmi, 0xff, HDMI_AUD_SPDIFINT); - hdmi_writeb(hdmi, 0xff, HDMI_AUD_HBR_MASK); - hdmi_writeb(hdmi, 0xff, HDMI_GP_MASK); - hdmi_writeb(hdmi, 0xff, HDMI_A_APIINTMSK); - hdmi_writeb(hdmi, 0xff, HDMI_CEC_MASK); - hdmi_writeb(hdmi, 0xff, HDMI_I2CM_INT); - hdmi_writeb(hdmi, 0xff, HDMI_I2CM_CTLINT); - - /* Disable interrupts in the IH_MUTE_* registers */ - hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_FC_STAT0); - hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_FC_STAT1); - hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_FC_STAT2); - hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_AS_STAT0); - hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_PHY_STAT0); - hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_I2CM_STAT0); - hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_CEC_STAT0); - hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_VP_STAT0); - hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_I2CMPHY_STAT0); - hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_AHBDMAAUD_STAT0); - - /* Enable top level interrupt bits in HDMI block */ - ih_mute &= ~(HDMI_IH_MUTE_MUTE_WAKEUP_INTERRUPT | - HDMI_IH_MUTE_MUTE_ALL_INTERRUPT); - hdmi_writeb(hdmi, ih_mute, HDMI_IH_MUTE); -} - -static void imx_hdmi_poweron(struct imx_hdmi *hdmi) -{ - imx_hdmi_setup(hdmi, &hdmi->previous_mode); -} - -static void imx_hdmi_poweroff(struct imx_hdmi *hdmi) -{ - imx_hdmi_phy_disable(hdmi); -} - -static enum drm_connector_status imx_hdmi_connector_detect(struct drm_connector - *connector, bool force) -{ - struct imx_hdmi *hdmi = container_of(connector, struct imx_hdmi, - connector); - - return hdmi_readb(hdmi, HDMI_PHY_STAT0) & HDMI_PHY_HPD ? - connector_status_connected : connector_status_disconnected; -} - -static int imx_hdmi_connector_get_modes(struct drm_connector *connector) -{ - struct imx_hdmi *hdmi = container_of(connector, struct imx_hdmi, - connector); - struct edid *edid; - int ret; - - if (!hdmi->ddc) - return 0; - - edid = drm_get_edid(connector, hdmi->ddc); - if (edid) { - dev_dbg(hdmi->dev, "got edid: width[%d] x height[%d]\n", - edid->width_cm, edid->height_cm); - - drm_mode_connector_update_edid_property(connector, edid); - ret = drm_add_edid_modes(connector, edid); - kfree(edid); - } else { - dev_dbg(hdmi->dev, "failed to get edid\n"); - } - - return 0; -} - -static struct drm_encoder *imx_hdmi_connector_best_encoder(struct drm_connector - *connector) -{ - struct imx_hdmi *hdmi = container_of(connector, struct imx_hdmi, - connector); - - return &hdmi->encoder; -} - -static void imx_hdmi_encoder_mode_set(struct drm_encoder *encoder, - struct drm_display_mode *mode, - struct drm_display_mode *adjusted_mode) -{ - struct imx_hdmi *hdmi = container_of(encoder, struct imx_hdmi, encoder); - - imx_hdmi_setup(hdmi, mode); - - /* Store the display mode for plugin/DKMS poweron events */ - memcpy(&hdmi->previous_mode, mode, sizeof(hdmi->previous_mode)); -} - -static bool imx_hdmi_encoder_mode_fixup(struct drm_encoder *encoder, - const struct drm_display_mode *mode, - struct drm_display_mode *adjusted_mode) -{ - return true; -} - -static void imx_hdmi_encoder_disable(struct drm_encoder *encoder) -{ -} - -static void imx_hdmi_encoder_dpms(struct drm_encoder *encoder, int mode) -{ - struct imx_hdmi *hdmi = container_of(encoder, struct imx_hdmi, encoder); - - if (mode) - imx_hdmi_poweroff(hdmi); - else - imx_hdmi_poweron(hdmi); -} - -static void imx_hdmi_encoder_prepare(struct drm_encoder *encoder) -{ - struct imx_hdmi *hdmi = container_of(encoder, struct imx_hdmi, encoder); - - imx_hdmi_poweroff(hdmi); - imx_drm_panel_format(encoder, V4L2_PIX_FMT_RGB24); -} - -static void imx_hdmi_encoder_commit(struct drm_encoder *encoder) -{ - struct imx_hdmi *hdmi = container_of(encoder, struct imx_hdmi, encoder); - int mux = imx_drm_encoder_get_mux_id(hdmi->dev->of_node, encoder); - - imx_hdmi_set_ipu_di_mux(hdmi, mux); - - imx_hdmi_poweron(hdmi); -} - -static struct drm_encoder_funcs imx_hdmi_encoder_funcs = { - .destroy = imx_drm_encoder_destroy, -}; - -static struct drm_encoder_helper_funcs imx_hdmi_encoder_helper_funcs = { - .dpms = imx_hdmi_encoder_dpms, - .prepare = imx_hdmi_encoder_prepare, - .commit = imx_hdmi_encoder_commit, - .mode_set = imx_hdmi_encoder_mode_set, - .mode_fixup = imx_hdmi_encoder_mode_fixup, - .disable = imx_hdmi_encoder_disable, -}; - -static struct drm_connector_funcs imx_hdmi_connector_funcs = { - .dpms = drm_helper_connector_dpms, - .fill_modes = drm_helper_probe_single_connector_modes, - .detect = imx_hdmi_connector_detect, - .destroy = imx_drm_connector_destroy, -}; - -static struct drm_connector_helper_funcs imx_hdmi_connector_helper_funcs = { - .get_modes = imx_hdmi_connector_get_modes, - .best_encoder = imx_hdmi_connector_best_encoder, -}; - -static irqreturn_t imx_hdmi_hardirq(int irq, void *dev_id) -{ - struct imx_hdmi *hdmi = dev_id; - u8 intr_stat; - - intr_stat = hdmi_readb(hdmi, HDMI_IH_PHY_STAT0); - if (intr_stat) - hdmi_writeb(hdmi, ~0, HDMI_IH_MUTE_PHY_STAT0); - - return intr_stat ? IRQ_WAKE_THREAD : IRQ_NONE; -} - -static irqreturn_t imx_hdmi_irq(int irq, void *dev_id) -{ - struct imx_hdmi *hdmi = dev_id; - u8 intr_stat; - u8 phy_int_pol; - - intr_stat = hdmi_readb(hdmi, HDMI_IH_PHY_STAT0); - - phy_int_pol = hdmi_readb(hdmi, HDMI_PHY_POL0); - - if (intr_stat & HDMI_IH_PHY_STAT0_HPD) { - if (phy_int_pol & HDMI_PHY_HPD) { - dev_dbg(hdmi->dev, "EVENT=plugin\n"); - - hdmi_modb(hdmi, 0, HDMI_PHY_HPD, HDMI_PHY_POL0); - - imx_hdmi_poweron(hdmi); - } else { - dev_dbg(hdmi->dev, "EVENT=plugout\n"); - - hdmi_modb(hdmi, HDMI_PHY_HPD, HDMI_PHY_HPD, - HDMI_PHY_POL0); - - imx_hdmi_poweroff(hdmi); - } - drm_helper_hpd_irq_event(hdmi->connector.dev); - } - - hdmi_writeb(hdmi, intr_stat, HDMI_IH_PHY_STAT0); - hdmi_writeb(hdmi, ~HDMI_IH_PHY_STAT0_HPD, HDMI_IH_MUTE_PHY_STAT0); - - return IRQ_HANDLED; -} - -static int imx_hdmi_register(struct drm_device *drm, struct imx_hdmi *hdmi) -{ - int ret; - - ret = imx_drm_encoder_parse_of(drm, &hdmi->encoder, - hdmi->dev->of_node); - if (ret) - return ret; - - hdmi->connector.polled = DRM_CONNECTOR_POLL_HPD; - - drm_encoder_helper_add(&hdmi->encoder, &imx_hdmi_encoder_helper_funcs); - drm_encoder_init(drm, &hdmi->encoder, &imx_hdmi_encoder_funcs, - DRM_MODE_ENCODER_TMDS); - - drm_connector_helper_add(&hdmi->connector, - &imx_hdmi_connector_helper_funcs); - drm_connector_init(drm, &hdmi->connector, &imx_hdmi_connector_funcs, - DRM_MODE_CONNECTOR_HDMIA); - - hdmi->connector.encoder = &hdmi->encoder; - - drm_mode_connector_attach_encoder(&hdmi->connector, &hdmi->encoder); - - return 0; -} - -static struct platform_device_id imx_hdmi_devtype[] = { - { - .name = "imx6q-hdmi", - .driver_data = IMX6Q_HDMI, - }, { - .name = "imx6dl-hdmi", - .driver_data = IMX6DL_HDMI, - }, { /* sentinel */ } -}; -MODULE_DEVICE_TABLE(platform, imx_hdmi_devtype); - -static const struct of_device_id imx_hdmi_dt_ids[] = { -{ .compatible = "fsl,imx6q-hdmi", .data = &imx_hdmi_devtype[IMX6Q_HDMI], }, -{ .compatible = "fsl,imx6dl-hdmi", .data = &imx_hdmi_devtype[IMX6DL_HDMI], }, -{ /* sentinel */ } -}; -MODULE_DEVICE_TABLE(of, imx_hdmi_dt_ids); - -static int imx_hdmi_bind(struct device *dev, struct device *master, void *data) -{ - struct platform_device *pdev = to_platform_device(dev); - const struct of_device_id *of_id = - of_match_device(imx_hdmi_dt_ids, dev); - struct drm_device *drm = data; - struct device_node *np = dev->of_node; - struct device_node *ddc_node; - struct imx_hdmi *hdmi; - struct resource *iores; - int ret, irq; - - hdmi = devm_kzalloc(dev, sizeof(*hdmi), GFP_KERNEL); - if (!hdmi) - return -ENOMEM; - - hdmi->dev = dev; - hdmi->sample_rate = 48000; - hdmi->ratio = 100; - - if (of_id) { - const struct platform_device_id *device_id = of_id->data; - - hdmi->dev_type = device_id->driver_data; - } - - ddc_node = of_parse_phandle(np, "ddc-i2c-bus", 0); - if (ddc_node) { - hdmi->ddc = of_find_i2c_adapter_by_node(ddc_node); - if (!hdmi->ddc) - dev_dbg(hdmi->dev, "failed to read ddc node\n"); - - of_node_put(ddc_node); - } else { - dev_dbg(hdmi->dev, "no ddc property found\n"); - } - - irq = platform_get_irq(pdev, 0); - if (irq < 0) - return irq; - - ret = devm_request_threaded_irq(dev, irq, imx_hdmi_hardirq, - imx_hdmi_irq, IRQF_SHARED, - dev_name(dev), hdmi); - if (ret) - return ret; - - iores = platform_get_resource(pdev, IORESOURCE_MEM, 0); - hdmi->regs = devm_ioremap_resource(dev, iores); - if (IS_ERR(hdmi->regs)) - return PTR_ERR(hdmi->regs); - - hdmi->regmap = syscon_regmap_lookup_by_phandle(np, "gpr"); - if (IS_ERR(hdmi->regmap)) - return PTR_ERR(hdmi->regmap); - - hdmi->isfr_clk = devm_clk_get(hdmi->dev, "isfr"); - if (IS_ERR(hdmi->isfr_clk)) { - ret = PTR_ERR(hdmi->isfr_clk); - dev_err(hdmi->dev, - "Unable to get HDMI isfr clk: %d\n", ret); - return ret; - } - - ret = clk_prepare_enable(hdmi->isfr_clk); - if (ret) { - dev_err(hdmi->dev, - "Cannot enable HDMI isfr clock: %d\n", ret); - return ret; - } - - hdmi->iahb_clk = devm_clk_get(hdmi->dev, "iahb"); - if (IS_ERR(hdmi->iahb_clk)) { - ret = PTR_ERR(hdmi->iahb_clk); - dev_err(hdmi->dev, - "Unable to get HDMI iahb clk: %d\n", ret); - goto err_isfr; - } - - ret = clk_prepare_enable(hdmi->iahb_clk); - if (ret) { - dev_err(hdmi->dev, - "Cannot enable HDMI iahb clock: %d\n", ret); - goto err_isfr; - } - - /* Product and revision IDs */ - dev_info(dev, - "Detected HDMI controller 0x%x:0x%x:0x%x:0x%x\n", - hdmi_readb(hdmi, HDMI_DESIGN_ID), - hdmi_readb(hdmi, HDMI_REVISION_ID), - hdmi_readb(hdmi, HDMI_PRODUCT_ID0), - hdmi_readb(hdmi, HDMI_PRODUCT_ID1)); - - initialize_hdmi_ih_mutes(hdmi); - - /* - * To prevent overflows in HDMI_IH_FC_STAT2, set the clk regenerator - * N and cts values before enabling phy - */ - hdmi_init_clk_regenerator(hdmi); - - /* - * Configure registers related to HDMI interrupt - * generation before registering IRQ. - */ - hdmi_writeb(hdmi, HDMI_PHY_HPD, HDMI_PHY_POL0); - - /* Clear Hotplug interrupts */ - hdmi_writeb(hdmi, HDMI_IH_PHY_STAT0_HPD, HDMI_IH_PHY_STAT0); - - ret = imx_hdmi_fb_registered(hdmi); - if (ret) - goto err_iahb; - - ret = imx_hdmi_register(drm, hdmi); - if (ret) - goto err_iahb; - - /* Unmute interrupts */ - hdmi_writeb(hdmi, ~HDMI_IH_PHY_STAT0_HPD, HDMI_IH_MUTE_PHY_STAT0); - - dev_set_drvdata(dev, hdmi); - - return 0; - -err_iahb: - clk_disable_unprepare(hdmi->iahb_clk); -err_isfr: - clk_disable_unprepare(hdmi->isfr_clk); - - return ret; -} - -static void imx_hdmi_unbind(struct device *dev, struct device *master, - void *data) -{ - struct imx_hdmi *hdmi = dev_get_drvdata(dev); - - /* Disable all interrupts */ - hdmi_writeb(hdmi, ~0, HDMI_IH_MUTE_PHY_STAT0); - - hdmi->connector.funcs->destroy(&hdmi->connector); - hdmi->encoder.funcs->destroy(&hdmi->encoder); - - clk_disable_unprepare(hdmi->iahb_clk); - clk_disable_unprepare(hdmi->isfr_clk); - i2c_put_adapter(hdmi->ddc); -} - -static const struct component_ops hdmi_ops = { - .bind = imx_hdmi_bind, - .unbind = imx_hdmi_unbind, -}; - -static int imx_hdmi_platform_probe(struct platform_device *pdev) -{ - return component_add(&pdev->dev, &hdmi_ops); -} - -static int imx_hdmi_platform_remove(struct platform_device *pdev) -{ - component_del(&pdev->dev, &hdmi_ops); - return 0; -} - -static struct platform_driver imx_hdmi_driver = { - .probe = imx_hdmi_platform_probe, - .remove = imx_hdmi_platform_remove, - .driver = { - .name = "imx-hdmi", - .of_match_table = imx_hdmi_dt_ids, - }, -}; - -module_platform_driver(imx_hdmi_driver); - -MODULE_AUTHOR("Sascha Hauer <s.hauer@pengutronix.de>"); -MODULE_DESCRIPTION("i.MX6 HDMI transmitter driver"); -MODULE_LICENSE("GPL"); -MODULE_ALIAS("platform:imx-hdmi"); diff --git a/drivers/gpu/drm/imx/imx-hdmi.h b/drivers/gpu/drm/imx/imx-hdmi.h deleted file mode 100644 index 39b677689db6..000000000000 --- a/drivers/gpu/drm/imx/imx-hdmi.h +++ /dev/null @@ -1,1032 +0,0 @@ -/* - * Copyright (C) 2011 Freescale Semiconductor, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - */ - -#ifndef __IMX_HDMI_H__ -#define __IMX_HDMI_H__ - -/* Identification Registers */ -#define HDMI_DESIGN_ID 0x0000 -#define HDMI_REVISION_ID 0x0001 -#define HDMI_PRODUCT_ID0 0x0002 -#define HDMI_PRODUCT_ID1 0x0003 -#define HDMI_CONFIG0_ID 0x0004 -#define HDMI_CONFIG1_ID 0x0005 -#define HDMI_CONFIG2_ID 0x0006 -#define HDMI_CONFIG3_ID 0x0007 - -/* Interrupt Registers */ -#define HDMI_IH_FC_STAT0 0x0100 -#define HDMI_IH_FC_STAT1 0x0101 -#define HDMI_IH_FC_STAT2 0x0102 -#define HDMI_IH_AS_STAT0 0x0103 -#define HDMI_IH_PHY_STAT0 0x0104 -#define HDMI_IH_I2CM_STAT0 0x0105 -#define HDMI_IH_CEC_STAT0 0x0106 -#define HDMI_IH_VP_STAT0 0x0107 -#define HDMI_IH_I2CMPHY_STAT0 0x0108 -#define HDMI_IH_AHBDMAAUD_STAT0 0x0109 - -#define HDMI_IH_MUTE_FC_STAT0 0x0180 -#define HDMI_IH_MUTE_FC_STAT1 0x0181 -#define HDMI_IH_MUTE_FC_STAT2 0x0182 -#define HDMI_IH_MUTE_AS_STAT0 0x0183 -#define HDMI_IH_MUTE_PHY_STAT0 0x0184 -#define HDMI_IH_MUTE_I2CM_STAT0 0x0185 -#define HDMI_IH_MUTE_CEC_STAT0 0x0186 -#define HDMI_IH_MUTE_VP_STAT0 0x0187 -#define HDMI_IH_MUTE_I2CMPHY_STAT0 0x0188 -#define HDMI_IH_MUTE_AHBDMAAUD_STAT0 0x0189 -#define HDMI_IH_MUTE 0x01FF - -/* Video Sample Registers */ -#define HDMI_TX_INVID0 0x0200 -#define HDMI_TX_INSTUFFING 0x0201 -#define HDMI_TX_GYDATA0 0x0202 -#define HDMI_TX_GYDATA1 0x0203 -#define HDMI_TX_RCRDATA0 0x0204 -#define HDMI_TX_RCRDATA1 0x0205 -#define HDMI_TX_BCBDATA0 0x0206 -#define HDMI_TX_BCBDATA1 0x0207 - -/* Video Packetizer Registers */ -#define HDMI_VP_STATUS 0x0800 -#define HDMI_VP_PR_CD 0x0801 -#define HDMI_VP_STUFF 0x0802 -#define HDMI_VP_REMAP 0x0803 -#define HDMI_VP_CONF 0x0804 -#define HDMI_VP_STAT 0x0805 -#define HDMI_VP_INT 0x0806 -#define HDMI_VP_MASK 0x0807 -#define HDMI_VP_POL 0x0808 - -/* Frame Composer Registers */ -#define HDMI_FC_INVIDCONF 0x1000 -#define HDMI_FC_INHACTV0 0x1001 -#define HDMI_FC_INHACTV1 0x1002 -#define HDMI_FC_INHBLANK0 0x1003 -#define HDMI_FC_INHBLANK1 0x1004 -#define HDMI_FC_INVACTV0 0x1005 -#define HDMI_FC_INVACTV1 0x1006 -#define HDMI_FC_INVBLANK 0x1007 -#define HDMI_FC_HSYNCINDELAY0 0x1008 -#define HDMI_FC_HSYNCINDELAY1 0x1009 -#define HDMI_FC_HSYNCINWIDTH0 0x100A -#define HDMI_FC_HSYNCINWIDTH1 0x100B -#define HDMI_FC_VSYNCINDELAY 0x100C -#define HDMI_FC_VSYNCINWIDTH 0x100D -#define HDMI_FC_INFREQ0 0x100E -#define HDMI_FC_INFREQ1 0x100F -#define HDMI_FC_INFREQ2 0x1010 -#define HDMI_FC_CTRLDUR 0x1011 -#define HDMI_FC_EXCTRLDUR 0x1012 -#define HDMI_FC_EXCTRLSPAC 0x1013 -#define HDMI_FC_CH0PREAM 0x1014 -#define HDMI_FC_CH1PREAM 0x1015 -#define HDMI_FC_CH2PREAM 0x1016 -#define HDMI_FC_AVICONF3 0x1017 -#define HDMI_FC_GCP 0x1018 -#define HDMI_FC_AVICONF0 0x1019 -#define HDMI_FC_AVICONF1 0x101A -#define HDMI_FC_AVICONF2 0x101B -#define HDMI_FC_AVIVID 0x101C -#define HDMI_FC_AVIETB0 0x101D -#define HDMI_FC_AVIETB1 0x101E -#define HDMI_FC_AVISBB0 0x101F -#define HDMI_FC_AVISBB1 0x1020 -#define HDMI_FC_AVIELB0 0x1021 -#define HDMI_FC_AVIELB1 0x1022 -#define HDMI_FC_AVISRB0 0x1023 -#define HDMI_FC_AVISRB1 0x1024 -#define HDMI_FC_AUDICONF0 0x1025 -#define HDMI_FC_AUDICONF1 0x1026 -#define HDMI_FC_AUDICONF2 0x1027 -#define HDMI_FC_AUDICONF3 0x1028 -#define HDMI_FC_VSDIEEEID0 0x1029 -#define HDMI_FC_VSDSIZE 0x102A -#define HDMI_FC_VSDIEEEID1 0x1030 -#define HDMI_FC_VSDIEEEID2 0x1031 -#define HDMI_FC_VSDPAYLOAD0 0x1032 -#define HDMI_FC_VSDPAYLOAD1 0x1033 -#define HDMI_FC_VSDPAYLOAD2 0x1034 -#define HDMI_FC_VSDPAYLOAD3 0x1035 -#define HDMI_FC_VSDPAYLOAD4 0x1036 -#define HDMI_FC_VSDPAYLOAD5 0x1037 -#define HDMI_FC_VSDPAYLOAD6 0x1038 -#define HDMI_FC_VSDPAYLOAD7 0x1039 -#define HDMI_FC_VSDPAYLOAD8 0x103A -#define HDMI_FC_VSDPAYLOAD9 0x103B -#define HDMI_FC_VSDPAYLOAD10 0x103C -#define HDMI_FC_VSDPAYLOAD11 0x103D -#define HDMI_FC_VSDPAYLOAD12 0x103E -#define HDMI_FC_VSDPAYLOAD13 0x103F -#define HDMI_FC_VSDPAYLOAD14 0x1040 -#define HDMI_FC_VSDPAYLOAD15 0x1041 -#define HDMI_FC_VSDPAYLOAD16 0x1042 -#define HDMI_FC_VSDPAYLOAD17 0x1043 -#define HDMI_FC_VSDPAYLOAD18 0x1044 -#define HDMI_FC_VSDPAYLOAD19 0x1045 -#define HDMI_FC_VSDPAYLOAD20 0x1046 -#define HDMI_FC_VSDPAYLOAD21 0x1047 -#define HDMI_FC_VSDPAYLOAD22 0x1048 -#define HDMI_FC_VSDPAYLOAD23 0x1049 -#define HDMI_FC_SPDVENDORNAME0 0x104A -#define HDMI_FC_SPDVENDORNAME1 0x104B -#define HDMI_FC_SPDVENDORNAME2 0x104C -#define HDMI_FC_SPDVENDORNAME3 0x104D -#define HDMI_FC_SPDVENDORNAME4 0x104E -#define HDMI_FC_SPDVENDORNAME5 0x104F -#define HDMI_FC_SPDVENDORNAME6 0x1050 -#define HDMI_FC_SPDVENDORNAME7 0x1051 -#define HDMI_FC_SDPPRODUCTNAME0 0x1052 -#define HDMI_FC_SDPPRODUCTNAME1 0x1053 -#define HDMI_FC_SDPPRODUCTNAME2 0x1054 -#define HDMI_FC_SDPPRODUCTNAME3 0x1055 -#define HDMI_FC_SDPPRODUCTNAME4 0x1056 -#define HDMI_FC_SDPPRODUCTNAME5 0x1057 -#define HDMI_FC_SDPPRODUCTNAME6 0x1058 -#define HDMI_FC_SDPPRODUCTNAME7 0x1059 -#define HDMI_FC_SDPPRODUCTNAME8 0x105A -#define HDMI_FC_SDPPRODUCTNAME9 0x105B -#define HDMI_FC_SDPPRODUCTNAME10 0x105C -#define HDMI_FC_SDPPRODUCTNAME11 0x105D -#define HDMI_FC_SDPPRODUCTNAME12 0x105E -#define HDMI_FC_SDPPRODUCTNAME13 0x105F -#define HDMI_FC_SDPPRODUCTNAME14 0x1060 -#define HDMI_FC_SPDPRODUCTNAME15 0x1061 -#define HDMI_FC_SPDDEVICEINF 0x1062 -#define HDMI_FC_AUDSCONF 0x1063 -#define HDMI_FC_AUDSSTAT 0x1064 -#define HDMI_FC_DATACH0FILL 0x1070 -#define HDMI_FC_DATACH1FILL 0x1071 -#define HDMI_FC_DATACH2FILL 0x1072 -#define HDMI_FC_CTRLQHIGH 0x1073 -#define HDMI_FC_CTRLQLOW 0x1074 -#define HDMI_FC_ACP0 0x1075 -#define HDMI_FC_ACP28 0x1076 -#define HDMI_FC_ACP27 0x1077 -#define HDMI_FC_ACP26 0x1078 -#define HDMI_FC_ACP25 0x1079 -#define HDMI_FC_ACP24 0x107A -#define HDMI_FC_ACP23 0x107B -#define HDMI_FC_ACP22 0x107C -#define HDMI_FC_ACP21 0x107D -#define HDMI_FC_ACP20 0x107E -#define HDMI_FC_ACP19 0x107F -#define HDMI_FC_ACP18 0x1080 -#define HDMI_FC_ACP17 0x1081 -#define HDMI_FC_ACP16 0x1082 -#define HDMI_FC_ACP15 0x1083 -#define HDMI_FC_ACP14 0x1084 -#define HDMI_FC_ACP13 0x1085 -#define HDMI_FC_ACP12 0x1086 -#define HDMI_FC_ACP11 0x1087 -#define HDMI_FC_ACP10 0x1088 -#define HDMI_FC_ACP9 0x1089 -#define HDMI_FC_ACP8 0x108A -#define HDMI_FC_ACP7 0x108B -#define HDMI_FC_ACP6 0x108C -#define HDMI_FC_ACP5 0x108D -#define HDMI_FC_ACP4 0x108E -#define HDMI_FC_ACP3 0x108F -#define HDMI_FC_ACP2 0x1090 -#define HDMI_FC_ACP1 0x1091 -#define HDMI_FC_ISCR1_0 0x1092 -#define HDMI_FC_ISCR1_16 0x1093 -#define HDMI_FC_ISCR1_15 0x1094 -#define HDMI_FC_ISCR1_14 0x1095 -#define HDMI_FC_ISCR1_13 0x1096 -#define HDMI_FC_ISCR1_12 0x1097 -#define HDMI_FC_ISCR1_11 0x1098 -#define HDMI_FC_ISCR1_10 0x1099 -#define HDMI_FC_ISCR1_9 0x109A -#define HDMI_FC_ISCR1_8 0x109B -#define HDMI_FC_ISCR1_7 0x109C -#define HDMI_FC_ISCR1_6 0x109D -#define HDMI_FC_ISCR1_5 0x109E -#define HDMI_FC_ISCR1_4 0x109F -#define HDMI_FC_ISCR1_3 0x10A0 -#define HDMI_FC_ISCR1_2 0x10A1 -#define HDMI_FC_ISCR1_1 0x10A2 -#define HDMI_FC_ISCR2_15 0x10A3 -#define HDMI_FC_ISCR2_14 0x10A4 -#define HDMI_FC_ISCR2_13 0x10A5 -#define HDMI_FC_ISCR2_12 0x10A6 -#define HDMI_FC_ISCR2_11 0x10A7 -#define HDMI_FC_ISCR2_10 0x10A8 -#define HDMI_FC_ISCR2_9 0x10A9 -#define HDMI_FC_ISCR2_8 0x10AA -#define HDMI_FC_ISCR2_7 0x10AB -#define HDMI_FC_ISCR2_6 0x10AC -#define HDMI_FC_ISCR2_5 0x10AD -#define HDMI_FC_ISCR2_4 0x10AE -#define HDMI_FC_ISCR2_3 0x10AF -#define HDMI_FC_ISCR2_2 0x10B0 -#define HDMI_FC_ISCR2_1 0x10B1 -#define HDMI_FC_ISCR2_0 0x10B2 -#define HDMI_FC_DATAUTO0 0x10B3 -#define HDMI_FC_DATAUTO1 0x10B4 -#define HDMI_FC_DATAUTO2 0x10B5 -#define HDMI_FC_DATMAN 0x10B6 -#define HDMI_FC_DATAUTO3 0x10B7 -#define HDMI_FC_RDRB0 0x10B8 -#define HDMI_FC_RDRB1 0x10B9 -#define HDMI_FC_RDRB2 0x10BA -#define HDMI_FC_RDRB3 0x10BB -#define HDMI_FC_RDRB4 0x10BC -#define HDMI_FC_RDRB5 0x10BD -#define HDMI_FC_RDRB6 0x10BE -#define HDMI_FC_RDRB7 0x10BF -#define HDMI_FC_STAT0 0x10D0 -#define HDMI_FC_INT0 0x10D1 -#define HDMI_FC_MASK0 0x10D2 -#define HDMI_FC_POL0 0x10D3 -#define HDMI_FC_STAT1 0x10D4 -#define HDMI_FC_INT1 0x10D5 -#define HDMI_FC_MASK1 0x10D6 -#define HDMI_FC_POL1 0x10D7 -#define HDMI_FC_STAT2 0x10D8 -#define HDMI_FC_INT2 0x10D9 -#define HDMI_FC_MASK2 0x10DA -#define HDMI_FC_POL2 0x10DB -#define HDMI_FC_PRCONF 0x10E0 - -#define HDMI_FC_GMD_STAT 0x1100 -#define HDMI_FC_GMD_EN 0x1101 -#define HDMI_FC_GMD_UP 0x1102 -#define HDMI_FC_GMD_CONF 0x1103 -#define HDMI_FC_GMD_HB 0x1104 -#define HDMI_FC_GMD_PB0 0x1105 -#define HDMI_FC_GMD_PB1 0x1106 -#define HDMI_FC_GMD_PB2 0x1107 -#define HDMI_FC_GMD_PB3 0x1108 -#define HDMI_FC_GMD_PB4 0x1109 -#define HDMI_FC_GMD_PB5 0x110A -#define HDMI_FC_GMD_PB6 0x110B -#define HDMI_FC_GMD_PB7 0x110C -#define HDMI_FC_GMD_PB8 0x110D -#define HDMI_FC_GMD_PB9 0x110E -#define HDMI_FC_GMD_PB10 0x110F -#define HDMI_FC_GMD_PB11 0x1110 -#define HDMI_FC_GMD_PB12 0x1111 -#define HDMI_FC_GMD_PB13 0x1112 -#define HDMI_FC_GMD_PB14 0x1113 -#define HDMI_FC_GMD_PB15 0x1114 -#define HDMI_FC_GMD_PB16 0x1115 -#define HDMI_FC_GMD_PB17 0x1116 -#define HDMI_FC_GMD_PB18 0x1117 -#define HDMI_FC_GMD_PB19 0x1118 -#define HDMI_FC_GMD_PB20 0x1119 -#define HDMI_FC_GMD_PB21 0x111A -#define HDMI_FC_GMD_PB22 0x111B -#define HDMI_FC_GMD_PB23 0x111C -#define HDMI_FC_GMD_PB24 0x111D -#define HDMI_FC_GMD_PB25 0x111E -#define HDMI_FC_GMD_PB26 0x111F -#define HDMI_FC_GMD_PB27 0x1120 - -#define HDMI_FC_DBGFORCE 0x1200 -#define HDMI_FC_DBGAUD0CH0 0x1201 -#define HDMI_FC_DBGAUD1CH0 0x1202 -#define HDMI_FC_DBGAUD2CH0 0x1203 -#define HDMI_FC_DBGAUD0CH1 0x1204 -#define HDMI_FC_DBGAUD1CH1 0x1205 -#define HDMI_FC_DBGAUD2CH1 0x1206 -#define HDMI_FC_DBGAUD0CH2 0x1207 -#define HDMI_FC_DBGAUD1CH2 0x1208 -#define HDMI_FC_DBGAUD2CH2 0x1209 -#define HDMI_FC_DBGAUD0CH3 0x120A -#define HDMI_FC_DBGAUD1CH3 0x120B -#define HDMI_FC_DBGAUD2CH3 0x120C -#define HDMI_FC_DBGAUD0CH4 0x120D -#define HDMI_FC_DBGAUD1CH4 0x120E -#define HDMI_FC_DBGAUD2CH4 0x120F -#define HDMI_FC_DBGAUD0CH5 0x1210 -#define HDMI_FC_DBGAUD1CH5 0x1211 -#define HDMI_FC_DBGAUD2CH5 0x1212 -#define HDMI_FC_DBGAUD0CH6 0x1213 -#define HDMI_FC_DBGAUD1CH6 0x1214 -#define HDMI_FC_DBGAUD2CH6 0x1215 -#define HDMI_FC_DBGAUD0CH7 0x1216 -#define HDMI_FC_DBGAUD1CH7 0x1217 -#define HDMI_FC_DBGAUD2CH7 0x1218 -#define HDMI_FC_DBGTMDS0 0x1219 -#define HDMI_FC_DBGTMDS1 0x121A -#define HDMI_FC_DBGTMDS2 0x121B - -/* HDMI Source PHY Registers */ -#define HDMI_PHY_CONF0 0x3000 -#define HDMI_PHY_TST0 0x3001 -#define HDMI_PHY_TST1 0x3002 -#define HDMI_PHY_TST2 0x3003 -#define HDMI_PHY_STAT0 0x3004 -#define HDMI_PHY_INT0 0x3005 -#define HDMI_PHY_MASK0 0x3006 -#define HDMI_PHY_POL0 0x3007 - -/* HDMI Master PHY Registers */ -#define HDMI_PHY_I2CM_SLAVE_ADDR 0x3020 -#define HDMI_PHY_I2CM_ADDRESS_ADDR 0x3021 -#define HDMI_PHY_I2CM_DATAO_1_ADDR 0x3022 -#define HDMI_PHY_I2CM_DATAO_0_ADDR 0x3023 -#define HDMI_PHY_I2CM_DATAI_1_ADDR 0x3024 -#define HDMI_PHY_I2CM_DATAI_0_ADDR 0x3025 -#define HDMI_PHY_I2CM_OPERATION_ADDR 0x3026 -#define HDMI_PHY_I2CM_INT_ADDR 0x3027 -#define HDMI_PHY_I2CM_CTLINT_ADDR 0x3028 -#define HDMI_PHY_I2CM_DIV_ADDR 0x3029 -#define HDMI_PHY_I2CM_SOFTRSTZ_ADDR 0x302a -#define HDMI_PHY_I2CM_SS_SCL_HCNT_1_ADDR 0x302b -#define HDMI_PHY_I2CM_SS_SCL_HCNT_0_ADDR 0x302c -#define HDMI_PHY_I2CM_SS_SCL_LCNT_1_ADDR 0x302d -#define HDMI_PHY_I2CM_SS_SCL_LCNT_0_ADDR 0x302e -#define HDMI_PHY_I2CM_FS_SCL_HCNT_1_ADDR 0x302f -#define HDMI_PHY_I2CM_FS_SCL_HCNT_0_ADDR 0x3030 -#define HDMI_PHY_I2CM_FS_SCL_LCNT_1_ADDR 0x3031 -#define HDMI_PHY_I2CM_FS_SCL_LCNT_0_ADDR 0x3032 - -/* Audio Sampler Registers */ -#define HDMI_AUD_CONF0 0x3100 -#define HDMI_AUD_CONF1 0x3101 -#define HDMI_AUD_INT 0x3102 -#define HDMI_AUD_CONF2 0x3103 -#define HDMI_AUD_N1 0x3200 -#define HDMI_AUD_N2 0x3201 -#define HDMI_AUD_N3 0x3202 -#define HDMI_AUD_CTS1 0x3203 -#define HDMI_AUD_CTS2 0x3204 -#define HDMI_AUD_CTS3 0x3205 -#define HDMI_AUD_INPUTCLKFS 0x3206 -#define HDMI_AUD_SPDIFINT 0x3302 -#define HDMI_AUD_CONF0_HBR 0x3400 -#define HDMI_AUD_HBR_STATUS 0x3401 -#define HDMI_AUD_HBR_INT 0x3402 -#define HDMI_AUD_HBR_POL 0x3403 -#define HDMI_AUD_HBR_MASK 0x3404 - -/* - * Generic Parallel Audio Interface Registers - * Not used as GPAUD interface is not enabled in hw - */ -#define HDMI_GP_CONF0 0x3500 -#define HDMI_GP_CONF1 0x3501 -#define HDMI_GP_CONF2 0x3502 -#define HDMI_GP_STAT 0x3503 -#define HDMI_GP_INT 0x3504 -#define HDMI_GP_MASK 0x3505 -#define HDMI_GP_POL 0x3506 - -/* Audio DMA Registers */ -#define HDMI_AHB_DMA_CONF0 0x3600 -#define HDMI_AHB_DMA_START 0x3601 -#define HDMI_AHB_DMA_STOP 0x3602 -#define HDMI_AHB_DMA_THRSLD 0x3603 -#define HDMI_AHB_DMA_STRADDR0 0x3604 -#define HDMI_AHB_DMA_STRADDR1 0x3605 -#define HDMI_AHB_DMA_STRADDR2 0x3606 -#define HDMI_AHB_DMA_STRADDR3 0x3607 -#define HDMI_AHB_DMA_STPADDR0 0x3608 -#define HDMI_AHB_DMA_STPADDR1 0x3609 -#define HDMI_AHB_DMA_STPADDR2 0x360a -#define HDMI_AHB_DMA_STPADDR3 0x360b -#define HDMI_AHB_DMA_BSTADDR0 0x360c -#define HDMI_AHB_DMA_BSTADDR1 0x360d -#define HDMI_AHB_DMA_BSTADDR2 0x360e -#define HDMI_AHB_DMA_BSTADDR3 0x360f -#define HDMI_AHB_DMA_MBLENGTH0 0x3610 -#define HDMI_AHB_DMA_MBLENGTH1 0x3611 -#define HDMI_AHB_DMA_STAT 0x3612 -#define HDMI_AHB_DMA_INT 0x3613 -#define HDMI_AHB_DMA_MASK 0x3614 -#define HDMI_AHB_DMA_POL 0x3615 -#define HDMI_AHB_DMA_CONF1 0x3616 -#define HDMI_AHB_DMA_BUFFSTAT 0x3617 -#define HDMI_AHB_DMA_BUFFINT 0x3618 -#define HDMI_AHB_DMA_BUFFMASK 0x3619 -#define HDMI_AHB_DMA_BUFFPOL 0x361a - -/* Main Controller Registers */ -#define HDMI_MC_SFRDIV 0x4000 -#define HDMI_MC_CLKDIS 0x4001 -#define HDMI_MC_SWRSTZ 0x4002 -#define HDMI_MC_OPCTRL 0x4003 -#define HDMI_MC_FLOWCTRL 0x4004 -#define HDMI_MC_PHYRSTZ 0x4005 -#define HDMI_MC_LOCKONCLOCK 0x4006 -#define HDMI_MC_HEACPHY_RST 0x4007 - -/* Color Space Converter Registers */ -#define HDMI_CSC_CFG 0x4100 -#define HDMI_CSC_SCALE 0x4101 -#define HDMI_CSC_COEF_A1_MSB 0x4102 -#define HDMI_CSC_COEF_A1_LSB 0x4103 -#define HDMI_CSC_COEF_A2_MSB 0x4104 -#define HDMI_CSC_COEF_A2_LSB 0x4105 -#define HDMI_CSC_COEF_A3_MSB 0x4106 -#define HDMI_CSC_COEF_A3_LSB 0x4107 -#define HDMI_CSC_COEF_A4_MSB 0x4108 -#define HDMI_CSC_COEF_A4_LSB 0x4109 -#define HDMI_CSC_COEF_B1_MSB 0x410A -#define HDMI_CSC_COEF_B1_LSB 0x410B -#define HDMI_CSC_COEF_B2_MSB 0x410C -#define HDMI_CSC_COEF_B2_LSB 0x410D -#define HDMI_CSC_COEF_B3_MSB 0x410E -#define HDMI_CSC_COEF_B3_LSB 0x410F -#define HDMI_CSC_COEF_B4_MSB 0x4110 -#define HDMI_CSC_COEF_B4_LSB 0x4111 -#define HDMI_CSC_COEF_C1_MSB 0x4112 -#define HDMI_CSC_COEF_C1_LSB 0x4113 -#define HDMI_CSC_COEF_C2_MSB 0x4114 -#define HDMI_CSC_COEF_C2_LSB 0x4115 -#define HDMI_CSC_COEF_C3_MSB 0x4116 -#define HDMI_CSC_COEF_C3_LSB 0x4117 -#define HDMI_CSC_COEF_C4_MSB 0x4118 -#define HDMI_CSC_COEF_C4_LSB 0x4119 - -/* HDCP Encryption Engine Registers */ -#define HDMI_A_HDCPCFG0 0x5000 -#define HDMI_A_HDCPCFG1 0x5001 -#define HDMI_A_HDCPOBS0 0x5002 -#define HDMI_A_HDCPOBS1 0x5003 -#define HDMI_A_HDCPOBS2 0x5004 -#define HDMI_A_HDCPOBS3 0x5005 -#define HDMI_A_APIINTCLR 0x5006 -#define HDMI_A_APIINTSTAT 0x5007 -#define HDMI_A_APIINTMSK 0x5008 -#define HDMI_A_VIDPOLCFG 0x5009 -#define HDMI_A_OESSWCFG 0x500A -#define HDMI_A_TIMER1SETUP0 0x500B -#define HDMI_A_TIMER1SETUP1 0x500C -#define HDMI_A_TIMER2SETUP0 0x500D -#define HDMI_A_TIMER2SETUP1 0x500E -#define HDMI_A_100MSCFG 0x500F -#define HDMI_A_2SCFG0 0x5010 -#define HDMI_A_2SCFG1 0x5011 -#define HDMI_A_5SCFG0 0x5012 -#define HDMI_A_5SCFG1 0x5013 -#define HDMI_A_SRMVERLSB 0x5014 -#define HDMI_A_SRMVERMSB 0x5015 -#define HDMI_A_SRMCTRL 0x5016 -#define HDMI_A_SFRSETUP 0x5017 -#define HDMI_A_I2CHSETUP 0x5018 -#define HDMI_A_INTSETUP 0x5019 -#define HDMI_A_PRESETUP 0x501A -#define HDMI_A_SRM_BASE 0x5020 - -/* CEC Engine Registers */ -#define HDMI_CEC_CTRL 0x7D00 -#define HDMI_CEC_STAT 0x7D01 -#define HDMI_CEC_MASK 0x7D02 -#define HDMI_CEC_POLARITY 0x7D03 -#define HDMI_CEC_INT 0x7D04 -#define HDMI_CEC_ADDR_L 0x7D05 -#define HDMI_CEC_ADDR_H 0x7D06 -#define HDMI_CEC_TX_CNT 0x7D07 -#define HDMI_CEC_RX_CNT 0x7D08 -#define HDMI_CEC_TX_DATA0 0x7D10 -#define HDMI_CEC_TX_DATA1 0x7D11 -#define HDMI_CEC_TX_DATA2 0x7D12 -#define HDMI_CEC_TX_DATA3 0x7D13 -#define HDMI_CEC_TX_DATA4 0x7D14 -#define HDMI_CEC_TX_DATA5 0x7D15 -#define HDMI_CEC_TX_DATA6 0x7D16 -#define HDMI_CEC_TX_DATA7 0x7D17 -#define HDMI_CEC_TX_DATA8 0x7D18 -#define HDMI_CEC_TX_DATA9 0x7D19 -#define HDMI_CEC_TX_DATA10 0x7D1a -#define HDMI_CEC_TX_DATA11 0x7D1b -#define HDMI_CEC_TX_DATA12 0x7D1c -#define HDMI_CEC_TX_DATA13 0x7D1d -#define HDMI_CEC_TX_DATA14 0x7D1e -#define HDMI_CEC_TX_DATA15 0x7D1f -#define HDMI_CEC_RX_DATA0 0x7D20 -#define HDMI_CEC_RX_DATA1 0x7D21 -#define HDMI_CEC_RX_DATA2 0x7D22 -#define HDMI_CEC_RX_DATA3 0x7D23 -#define HDMI_CEC_RX_DATA4 0x7D24 -#define HDMI_CEC_RX_DATA5 0x7D25 -#define HDMI_CEC_RX_DATA6 0x7D26 -#define HDMI_CEC_RX_DATA7 0x7D27 -#define HDMI_CEC_RX_DATA8 0x7D28 -#define HDMI_CEC_RX_DATA9 0x7D29 -#define HDMI_CEC_RX_DATA10 0x7D2a -#define HDMI_CEC_RX_DATA11 0x7D2b -#define HDMI_CEC_RX_DATA12 0x7D2c -#define HDMI_CEC_RX_DATA13 0x7D2d -#define HDMI_CEC_RX_DATA14 0x7D2e -#define HDMI_CEC_RX_DATA15 0x7D2f -#define HDMI_CEC_LOCK 0x7D30 -#define HDMI_CEC_WKUPCTRL 0x7D31 - -/* I2C Master Registers (E-DDC) */ -#define HDMI_I2CM_SLAVE 0x7E00 -#define HDMI_I2CMESS 0x7E01 -#define HDMI_I2CM_DATAO 0x7E02 -#define HDMI_I2CM_DATAI 0x7E03 -#define HDMI_I2CM_OPERATION 0x7E04 -#define HDMI_I2CM_INT 0x7E05 -#define HDMI_I2CM_CTLINT 0x7E06 -#define HDMI_I2CM_DIV 0x7E07 -#define HDMI_I2CM_SEGADDR 0x7E08 -#define HDMI_I2CM_SOFTRSTZ 0x7E09 -#define HDMI_I2CM_SEGPTR 0x7E0A -#define HDMI_I2CM_SS_SCL_HCNT_1_ADDR 0x7E0B -#define HDMI_I2CM_SS_SCL_HCNT_0_ADDR 0x7E0C -#define HDMI_I2CM_SS_SCL_LCNT_1_ADDR 0x7E0D -#define HDMI_I2CM_SS_SCL_LCNT_0_ADDR 0x7E0E -#define HDMI_I2CM_FS_SCL_HCNT_1_ADDR 0x7E0F -#define HDMI_I2CM_FS_SCL_HCNT_0_ADDR 0x7E10 -#define HDMI_I2CM_FS_SCL_LCNT_1_ADDR 0x7E11 -#define HDMI_I2CM_FS_SCL_LCNT_0_ADDR 0x7E12 - -enum { -/* IH_FC_INT2 field values */ - HDMI_IH_FC_INT2_OVERFLOW_MASK = 0x03, - HDMI_IH_FC_INT2_LOW_PRIORITY_OVERFLOW = 0x02, - HDMI_IH_FC_INT2_HIGH_PRIORITY_OVERFLOW = 0x01, - -/* IH_FC_STAT2 field values */ - HDMI_IH_FC_STAT2_OVERFLOW_MASK = 0x03, - HDMI_IH_FC_STAT2_LOW_PRIORITY_OVERFLOW = 0x02, - HDMI_IH_FC_STAT2_HIGH_PRIORITY_OVERFLOW = 0x01, - -/* IH_PHY_STAT0 field values */ - HDMI_IH_PHY_STAT0_RX_SENSE3 = 0x20, - HDMI_IH_PHY_STAT0_RX_SENSE2 = 0x10, - HDMI_IH_PHY_STAT0_RX_SENSE1 = 0x8, - HDMI_IH_PHY_STAT0_RX_SENSE0 = 0x4, - HDMI_IH_PHY_STAT0_TX_PHY_LOCK = 0x2, - HDMI_IH_PHY_STAT0_HPD = 0x1, - -/* IH_MUTE_I2CMPHY_STAT0 field values */ - HDMI_IH_MUTE_I2CMPHY_STAT0_I2CMPHYDONE = 0x2, - HDMI_IH_MUTE_I2CMPHY_STAT0_I2CMPHYERROR = 0x1, - -/* IH_AHBDMAAUD_STAT0 field values */ - HDMI_IH_AHBDMAAUD_STAT0_ERROR = 0x20, - HDMI_IH_AHBDMAAUD_STAT0_LOST = 0x10, - HDMI_IH_AHBDMAAUD_STAT0_RETRY = 0x08, - HDMI_IH_AHBDMAAUD_STAT0_DONE = 0x04, - HDMI_IH_AHBDMAAUD_STAT0_BUFFFULL = 0x02, - HDMI_IH_AHBDMAAUD_STAT0_BUFFEMPTY = 0x01, - -/* IH_MUTE_FC_STAT2 field values */ - HDMI_IH_MUTE_FC_STAT2_OVERFLOW_MASK = 0x03, - HDMI_IH_MUTE_FC_STAT2_LOW_PRIORITY_OVERFLOW = 0x02, - HDMI_IH_MUTE_FC_STAT2_HIGH_PRIORITY_OVERFLOW = 0x01, - -/* IH_MUTE_AHBDMAAUD_STAT0 field values */ - HDMI_IH_MUTE_AHBDMAAUD_STAT0_ERROR = 0x20, - HDMI_IH_MUTE_AHBDMAAUD_STAT0_LOST = 0x10, - HDMI_IH_MUTE_AHBDMAAUD_STAT0_RETRY = 0x08, - HDMI_IH_MUTE_AHBDMAAUD_STAT0_DONE = 0x04, - HDMI_IH_MUTE_AHBDMAAUD_STAT0_BUFFFULL = 0x02, - HDMI_IH_MUTE_AHBDMAAUD_STAT0_BUFFEMPTY = 0x01, - -/* IH_MUTE field values */ - HDMI_IH_MUTE_MUTE_WAKEUP_INTERRUPT = 0x2, - HDMI_IH_MUTE_MUTE_ALL_INTERRUPT = 0x1, - -/* TX_INVID0 field values */ - HDMI_TX_INVID0_INTERNAL_DE_GENERATOR_MASK = 0x80, - HDMI_TX_INVID0_INTERNAL_DE_GENERATOR_ENABLE = 0x80, - HDMI_TX_INVID0_INTERNAL_DE_GENERATOR_DISABLE = 0x00, - HDMI_TX_INVID0_VIDEO_MAPPING_MASK = 0x1F, - HDMI_TX_INVID0_VIDEO_MAPPING_OFFSET = 0, - -/* TX_INSTUFFING field values */ - HDMI_TX_INSTUFFING_BDBDATA_STUFFING_MASK = 0x4, - HDMI_TX_INSTUFFING_BDBDATA_STUFFING_ENABLE = 0x4, - HDMI_TX_INSTUFFING_BDBDATA_STUFFING_DISABLE = 0x0, - HDMI_TX_INSTUFFING_RCRDATA_STUFFING_MASK = 0x2, - HDMI_TX_INSTUFFING_RCRDATA_STUFFING_ENABLE = 0x2, - HDMI_TX_INSTUFFING_RCRDATA_STUFFING_DISABLE = 0x0, - HDMI_TX_INSTUFFING_GYDATA_STUFFING_MASK = 0x1, - HDMI_TX_INSTUFFING_GYDATA_STUFFING_ENABLE = 0x1, - HDMI_TX_INSTUFFING_GYDATA_STUFFING_DISABLE = 0x0, - -/* VP_PR_CD field values */ - HDMI_VP_PR_CD_COLOR_DEPTH_MASK = 0xF0, - HDMI_VP_PR_CD_COLOR_DEPTH_OFFSET = 4, - HDMI_VP_PR_CD_DESIRED_PR_FACTOR_MASK = 0x0F, - HDMI_VP_PR_CD_DESIRED_PR_FACTOR_OFFSET = 0, - -/* VP_STUFF field values */ - HDMI_VP_STUFF_IDEFAULT_PHASE_MASK = 0x20, - HDMI_VP_STUFF_IDEFAULT_PHASE_OFFSET = 5, - HDMI_VP_STUFF_IFIX_PP_TO_LAST_MASK = 0x10, - HDMI_VP_STUFF_IFIX_PP_TO_LAST_OFFSET = 4, - HDMI_VP_STUFF_ICX_GOTO_P0_ST_MASK = 0x8, - HDMI_VP_STUFF_ICX_GOTO_P0_ST_OFFSET = 3, - HDMI_VP_STUFF_YCC422_STUFFING_MASK = 0x4, - HDMI_VP_STUFF_YCC422_STUFFING_STUFFING_MODE = 0x4, - HDMI_VP_STUFF_YCC422_STUFFING_DIRECT_MODE = 0x0, - HDMI_VP_STUFF_PP_STUFFING_MASK = 0x2, - HDMI_VP_STUFF_PP_STUFFING_STUFFING_MODE = 0x2, - HDMI_VP_STUFF_PP_STUFFING_DIRECT_MODE = 0x0, - HDMI_VP_STUFF_PR_STUFFING_MASK = 0x1, - HDMI_VP_STUFF_PR_STUFFING_STUFFING_MODE = 0x1, - HDMI_VP_STUFF_PR_STUFFING_DIRECT_MODE = 0x0, - -/* VP_CONF field values */ - HDMI_VP_CONF_BYPASS_EN_MASK = 0x40, - HDMI_VP_CONF_BYPASS_EN_ENABLE = 0x40, - HDMI_VP_CONF_BYPASS_EN_DISABLE = 0x00, - HDMI_VP_CONF_PP_EN_ENMASK = 0x20, - HDMI_VP_CONF_PP_EN_ENABLE = 0x20, - HDMI_VP_CONF_PP_EN_DISABLE = 0x00, - HDMI_VP_CONF_PR_EN_MASK = 0x10, - HDMI_VP_CONF_PR_EN_ENABLE = 0x10, - HDMI_VP_CONF_PR_EN_DISABLE = 0x00, - HDMI_VP_CONF_YCC422_EN_MASK = 0x8, - HDMI_VP_CONF_YCC422_EN_ENABLE = 0x8, - HDMI_VP_CONF_YCC422_EN_DISABLE = 0x0, - HDMI_VP_CONF_BYPASS_SELECT_MASK = 0x4, - HDMI_VP_CONF_BYPASS_SELECT_VID_PACKETIZER = 0x4, - HDMI_VP_CONF_BYPASS_SELECT_PIX_REPEATER = 0x0, - HDMI_VP_CONF_OUTPUT_SELECTOR_MASK = 0x3, - HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS = 0x3, - HDMI_VP_CONF_OUTPUT_SELECTOR_YCC422 = 0x1, - HDMI_VP_CONF_OUTPUT_SELECTOR_PP = 0x0, - -/* VP_REMAP field values */ - HDMI_VP_REMAP_MASK = 0x3, - HDMI_VP_REMAP_YCC422_24bit = 0x2, - HDMI_VP_REMAP_YCC422_20bit = 0x1, - HDMI_VP_REMAP_YCC422_16bit = 0x0, - -/* FC_INVIDCONF field values */ - HDMI_FC_INVIDCONF_HDCP_KEEPOUT_MASK = 0x80, - HDMI_FC_INVIDCONF_HDCP_KEEPOUT_ACTIVE = 0x80, - HDMI_FC_INVIDCONF_HDCP_KEEPOUT_INACTIVE = 0x00, - HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_MASK = 0x40, - HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_ACTIVE_HIGH = 0x40, - HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_ACTIVE_LOW = 0x00, - HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_MASK = 0x20, - HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_ACTIVE_HIGH = 0x20, - HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_ACTIVE_LOW = 0x00, - HDMI_FC_INVIDCONF_DE_IN_POLARITY_MASK = 0x10, - HDMI_FC_INVIDCONF_DE_IN_POLARITY_ACTIVE_HIGH = 0x10, - HDMI_FC_INVIDCONF_DE_IN_POLARITY_ACTIVE_LOW = 0x00, - HDMI_FC_INVIDCONF_DVI_MODEZ_MASK = 0x8, - HDMI_FC_INVIDCONF_DVI_MODEZ_HDMI_MODE = 0x8, - HDMI_FC_INVIDCONF_DVI_MODEZ_DVI_MODE = 0x0, - HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_MASK = 0x2, - HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_HIGH = 0x2, - HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_LOW = 0x0, - HDMI_FC_INVIDCONF_IN_I_P_MASK = 0x1, - HDMI_FC_INVIDCONF_IN_I_P_INTERLACED = 0x1, - HDMI_FC_INVIDCONF_IN_I_P_PROGRESSIVE = 0x0, - -/* FC_AUDICONF0 field values */ - HDMI_FC_AUDICONF0_CC_OFFSET = 4, - HDMI_FC_AUDICONF0_CC_MASK = 0x70, - HDMI_FC_AUDICONF0_CT_OFFSET = 0, - HDMI_FC_AUDICONF0_CT_MASK = 0xF, - -/* FC_AUDICONF1 field values */ - HDMI_FC_AUDICONF1_SS_OFFSET = 3, - HDMI_FC_AUDICONF1_SS_MASK = 0x18, - HDMI_FC_AUDICONF1_SF_OFFSET = 0, - HDMI_FC_AUDICONF1_SF_MASK = 0x7, - -/* FC_AUDICONF3 field values */ - HDMI_FC_AUDICONF3_LFEPBL_OFFSET = 5, - HDMI_FC_AUDICONF3_LFEPBL_MASK = 0x60, - HDMI_FC_AUDICONF3_DM_INH_OFFSET = 4, - HDMI_FC_AUDICONF3_DM_INH_MASK = 0x10, - HDMI_FC_AUDICONF3_LSV_OFFSET = 0, - HDMI_FC_AUDICONF3_LSV_MASK = 0xF, - -/* FC_AUDSCHNLS0 field values */ - HDMI_FC_AUDSCHNLS0_CGMSA_OFFSET = 4, - HDMI_FC_AUDSCHNLS0_CGMSA_MASK = 0x30, - HDMI_FC_AUDSCHNLS0_COPYRIGHT_OFFSET = 0, - HDMI_FC_AUDSCHNLS0_COPYRIGHT_MASK = 0x01, - -/* FC_AUDSCHNLS3-6 field values */ - HDMI_FC_AUDSCHNLS3_OIEC_CH0_OFFSET = 0, - HDMI_FC_AUDSCHNLS3_OIEC_CH0_MASK = 0x0f, - HDMI_FC_AUDSCHNLS3_OIEC_CH1_OFFSET = 4, - HDMI_FC_AUDSCHNLS3_OIEC_CH1_MASK = 0xf0, - HDMI_FC_AUDSCHNLS4_OIEC_CH2_OFFSET = 0, - HDMI_FC_AUDSCHNLS4_OIEC_CH2_MASK = 0x0f, - HDMI_FC_AUDSCHNLS4_OIEC_CH3_OFFSET = 4, - HDMI_FC_AUDSCHNLS4_OIEC_CH3_MASK = 0xf0, - - HDMI_FC_AUDSCHNLS5_OIEC_CH0_OFFSET = 0, - HDMI_FC_AUDSCHNLS5_OIEC_CH0_MASK = 0x0f, - HDMI_FC_AUDSCHNLS5_OIEC_CH1_OFFSET = 4, - HDMI_FC_AUDSCHNLS5_OIEC_CH1_MASK = 0xf0, - HDMI_FC_AUDSCHNLS6_OIEC_CH2_OFFSET = 0, - HDMI_FC_AUDSCHNLS6_OIEC_CH2_MASK = 0x0f, - HDMI_FC_AUDSCHNLS6_OIEC_CH3_OFFSET = 4, - HDMI_FC_AUDSCHNLS6_OIEC_CH3_MASK = 0xf0, - -/* HDMI_FC_AUDSCHNLS7 field values */ - HDMI_FC_AUDSCHNLS7_ACCURACY_OFFSET = 4, - HDMI_FC_AUDSCHNLS7_ACCURACY_MASK = 0x30, - -/* HDMI_FC_AUDSCHNLS8 field values */ - HDMI_FC_AUDSCHNLS8_ORIGSAMPFREQ_MASK = 0xf0, - HDMI_FC_AUDSCHNLS8_ORIGSAMPFREQ_OFFSET = 4, - HDMI_FC_AUDSCHNLS8_WORDLEGNTH_MASK = 0x0f, - HDMI_FC_AUDSCHNLS8_WORDLEGNTH_OFFSET = 0, - -/* FC_AUDSCONF field values */ - HDMI_FC_AUDSCONF_AUD_PACKET_SAMPFIT_MASK = 0xF0, - HDMI_FC_AUDSCONF_AUD_PACKET_SAMPFIT_OFFSET = 4, - HDMI_FC_AUDSCONF_AUD_PACKET_LAYOUT_MASK = 0x1, - HDMI_FC_AUDSCONF_AUD_PACKET_LAYOUT_OFFSET = 0, - HDMI_FC_AUDSCONF_AUD_PACKET_LAYOUT_LAYOUT1 = 0x1, - HDMI_FC_AUDSCONF_AUD_PACKET_LAYOUT_LAYOUT0 = 0x0, - -/* FC_STAT2 field values */ - HDMI_FC_STAT2_OVERFLOW_MASK = 0x03, - HDMI_FC_STAT2_LOW_PRIORITY_OVERFLOW = 0x02, - HDMI_FC_STAT2_HIGH_PRIORITY_OVERFLOW = 0x01, - -/* FC_INT2 field values */ - HDMI_FC_INT2_OVERFLOW_MASK = 0x03, - HDMI_FC_INT2_LOW_PRIORITY_OVERFLOW = 0x02, - HDMI_FC_INT2_HIGH_PRIORITY_OVERFLOW = 0x01, - -/* FC_MASK2 field values */ - HDMI_FC_MASK2_OVERFLOW_MASK = 0x03, - HDMI_FC_MASK2_LOW_PRIORITY_OVERFLOW = 0x02, - HDMI_FC_MASK2_HIGH_PRIORITY_OVERFLOW = 0x01, - -/* FC_PRCONF field values */ - HDMI_FC_PRCONF_INCOMING_PR_FACTOR_MASK = 0xF0, - HDMI_FC_PRCONF_INCOMING_PR_FACTOR_OFFSET = 4, - HDMI_FC_PRCONF_OUTPUT_PR_FACTOR_MASK = 0x0F, - HDMI_FC_PRCONF_OUTPUT_PR_FACTOR_OFFSET = 0, - -/* FC_AVICONF0-FC_AVICONF3 field values */ - HDMI_FC_AVICONF0_PIX_FMT_MASK = 0x03, - HDMI_FC_AVICONF0_PIX_FMT_RGB = 0x00, - HDMI_FC_AVICONF0_PIX_FMT_YCBCR422 = 0x01, - HDMI_FC_AVICONF0_PIX_FMT_YCBCR444 = 0x02, - HDMI_FC_AVICONF0_ACTIVE_FMT_MASK = 0x40, - HDMI_FC_AVICONF0_ACTIVE_FMT_INFO_PRESENT = 0x40, - HDMI_FC_AVICONF0_ACTIVE_FMT_NO_INFO = 0x00, - HDMI_FC_AVICONF0_BAR_DATA_MASK = 0x0C, - HDMI_FC_AVICONF0_BAR_DATA_NO_DATA = 0x00, - HDMI_FC_AVICONF0_BAR_DATA_VERT_BAR = 0x04, - HDMI_FC_AVICONF0_BAR_DATA_HORIZ_BAR = 0x08, - HDMI_FC_AVICONF0_BAR_DATA_VERT_HORIZ_BAR = 0x0C, - HDMI_FC_AVICONF0_SCAN_INFO_MASK = 0x30, - HDMI_FC_AVICONF0_SCAN_INFO_OVERSCAN = 0x10, - HDMI_FC_AVICONF0_SCAN_INFO_UNDERSCAN = 0x20, - HDMI_FC_AVICONF0_SCAN_INFO_NODATA = 0x00, - - HDMI_FC_AVICONF1_ACTIVE_ASPECT_RATIO_MASK = 0x0F, - HDMI_FC_AVICONF1_ACTIVE_ASPECT_RATIO_USE_CODED = 0x08, - HDMI_FC_AVICONF1_ACTIVE_ASPECT_RATIO_4_3 = 0x09, - HDMI_FC_AVICONF1_ACTIVE_ASPECT_RATIO_16_9 = 0x0A, - HDMI_FC_AVICONF1_ACTIVE_ASPECT_RATIO_14_9 = 0x0B, - HDMI_FC_AVICONF1_CODED_ASPECT_RATIO_MASK = 0x30, - HDMI_FC_AVICONF1_CODED_ASPECT_RATIO_NO_DATA = 0x00, - HDMI_FC_AVICONF1_CODED_ASPECT_RATIO_4_3 = 0x10, - HDMI_FC_AVICONF1_CODED_ASPECT_RATIO_16_9 = 0x20, - HDMI_FC_AVICONF1_COLORIMETRY_MASK = 0xC0, - HDMI_FC_AVICONF1_COLORIMETRY_NO_DATA = 0x00, - HDMI_FC_AVICONF1_COLORIMETRY_SMPTE = 0x40, - HDMI_FC_AVICONF1_COLORIMETRY_ITUR = 0x80, - HDMI_FC_AVICONF1_COLORIMETRY_EXTENDED_INFO = 0xC0, - - HDMI_FC_AVICONF2_SCALING_MASK = 0x03, - HDMI_FC_AVICONF2_SCALING_NONE = 0x00, - HDMI_FC_AVICONF2_SCALING_HORIZ = 0x01, - HDMI_FC_AVICONF2_SCALING_VERT = 0x02, - HDMI_FC_AVICONF2_SCALING_HORIZ_VERT = 0x03, - HDMI_FC_AVICONF2_RGB_QUANT_MASK = 0x0C, - HDMI_FC_AVICONF2_RGB_QUANT_DEFAULT = 0x00, - HDMI_FC_AVICONF2_RGB_QUANT_LIMITED_RANGE = 0x04, - HDMI_FC_AVICONF2_RGB_QUANT_FULL_RANGE = 0x08, - HDMI_FC_AVICONF2_EXT_COLORIMETRY_MASK = 0x70, - HDMI_FC_AVICONF2_EXT_COLORIMETRY_XVYCC601 = 0x00, - HDMI_FC_AVICONF2_EXT_COLORIMETRY_XVYCC709 = 0x10, - HDMI_FC_AVICONF2_EXT_COLORIMETRY_SYCC601 = 0x20, - HDMI_FC_AVICONF2_EXT_COLORIMETRY_ADOBE_YCC601 = 0x30, - HDMI_FC_AVICONF2_EXT_COLORIMETRY_ADOBE_RGB = 0x40, - HDMI_FC_AVICONF2_IT_CONTENT_MASK = 0x80, - HDMI_FC_AVICONF2_IT_CONTENT_NO_DATA = 0x00, - HDMI_FC_AVICONF2_IT_CONTENT_VALID = 0x80, - - HDMI_FC_AVICONF3_IT_CONTENT_TYPE_MASK = 0x03, - HDMI_FC_AVICONF3_IT_CONTENT_TYPE_GRAPHICS = 0x00, - HDMI_FC_AVICONF3_IT_CONTENT_TYPE_PHOTO = 0x01, - HDMI_FC_AVICONF3_IT_CONTENT_TYPE_CINEMA = 0x02, - HDMI_FC_AVICONF3_IT_CONTENT_TYPE_GAME = 0x03, - HDMI_FC_AVICONF3_QUANT_RANGE_MASK = 0x0C, - HDMI_FC_AVICONF3_QUANT_RANGE_LIMITED = 0x00, - HDMI_FC_AVICONF3_QUANT_RANGE_FULL = 0x04, - -/* FC_DBGFORCE field values */ - HDMI_FC_DBGFORCE_FORCEAUDIO = 0x10, - HDMI_FC_DBGFORCE_FORCEVIDEO = 0x1, - -/* PHY_CONF0 field values */ - HDMI_PHY_CONF0_PDZ_MASK = 0x80, - HDMI_PHY_CONF0_PDZ_OFFSET = 7, - HDMI_PHY_CONF0_ENTMDS_MASK = 0x40, - HDMI_PHY_CONF0_ENTMDS_OFFSET = 6, - HDMI_PHY_CONF0_SPARECTRL = 0x20, - HDMI_PHY_CONF0_GEN2_PDDQ_MASK = 0x10, - HDMI_PHY_CONF0_GEN2_PDDQ_OFFSET = 4, - HDMI_PHY_CONF0_GEN2_TXPWRON_MASK = 0x8, - HDMI_PHY_CONF0_GEN2_TXPWRON_OFFSET = 3, - HDMI_PHY_CONF0_GEN2_ENHPDRXSENSE_MASK = 0x4, - HDMI_PHY_CONF0_GEN2_ENHPDRXSENSE_OFFSET = 2, - HDMI_PHY_CONF0_SELDATAENPOL_MASK = 0x2, - HDMI_PHY_CONF0_SELDATAENPOL_OFFSET = 1, - HDMI_PHY_CONF0_SELDIPIF_MASK = 0x1, - HDMI_PHY_CONF0_SELDIPIF_OFFSET = 0, - -/* PHY_TST0 field values */ - HDMI_PHY_TST0_TSTCLR_MASK = 0x20, - HDMI_PHY_TST0_TSTCLR_OFFSET = 5, - HDMI_PHY_TST0_TSTEN_MASK = 0x10, - HDMI_PHY_TST0_TSTEN_OFFSET = 4, - HDMI_PHY_TST0_TSTCLK_MASK = 0x1, - HDMI_PHY_TST0_TSTCLK_OFFSET = 0, - -/* PHY_STAT0 field values */ - HDMI_PHY_RX_SENSE3 = 0x80, - HDMI_PHY_RX_SENSE2 = 0x40, - HDMI_PHY_RX_SENSE1 = 0x20, - HDMI_PHY_RX_SENSE0 = 0x10, - HDMI_PHY_HPD = 0x02, - HDMI_PHY_TX_PHY_LOCK = 0x01, - -/* PHY_I2CM_SLAVE_ADDR field values */ - HDMI_PHY_I2CM_SLAVE_ADDR_PHY_GEN2 = 0x69, - HDMI_PHY_I2CM_SLAVE_ADDR_HEAC_PHY = 0x49, - -/* PHY_I2CM_OPERATION_ADDR field values */ - HDMI_PHY_I2CM_OPERATION_ADDR_WRITE = 0x10, - HDMI_PHY_I2CM_OPERATION_ADDR_READ = 0x1, - -/* HDMI_PHY_I2CM_INT_ADDR */ - HDMI_PHY_I2CM_INT_ADDR_DONE_POL = 0x08, - HDMI_PHY_I2CM_INT_ADDR_DONE_MASK = 0x04, - -/* HDMI_PHY_I2CM_CTLINT_ADDR */ - HDMI_PHY_I2CM_CTLINT_ADDR_NAC_POL = 0x80, - HDMI_PHY_I2CM_CTLINT_ADDR_NAC_MASK = 0x40, - HDMI_PHY_I2CM_CTLINT_ADDR_ARBITRATION_POL = 0x08, - HDMI_PHY_I2CM_CTLINT_ADDR_ARBITRATION_MASK = 0x04, - -/* AUD_CTS3 field values */ - HDMI_AUD_CTS3_N_SHIFT_OFFSET = 5, - HDMI_AUD_CTS3_N_SHIFT_MASK = 0xe0, - HDMI_AUD_CTS3_N_SHIFT_1 = 0, - HDMI_AUD_CTS3_N_SHIFT_16 = 0x20, - HDMI_AUD_CTS3_N_SHIFT_32 = 0x40, - HDMI_AUD_CTS3_N_SHIFT_64 = 0x60, - HDMI_AUD_CTS3_N_SHIFT_128 = 0x80, - HDMI_AUD_CTS3_N_SHIFT_256 = 0xa0, - /* note that the CTS3 MANUAL bit has been removed - from our part. Can't set it, will read as 0. */ - HDMI_AUD_CTS3_CTS_MANUAL = 0x10, - HDMI_AUD_CTS3_AUDCTS19_16_MASK = 0x0f, - -/* AHB_DMA_CONF0 field values */ - HDMI_AHB_DMA_CONF0_SW_FIFO_RST_OFFSET = 7, - HDMI_AHB_DMA_CONF0_SW_FIFO_RST_MASK = 0x80, - HDMI_AHB_DMA_CONF0_HBR = 0x10, - HDMI_AHB_DMA_CONF0_EN_HLOCK_OFFSET = 3, - HDMI_AHB_DMA_CONF0_EN_HLOCK_MASK = 0x08, - HDMI_AHB_DMA_CONF0_INCR_TYPE_OFFSET = 1, - HDMI_AHB_DMA_CONF0_INCR_TYPE_MASK = 0x06, - HDMI_AHB_DMA_CONF0_INCR4 = 0x0, - HDMI_AHB_DMA_CONF0_INCR8 = 0x2, - HDMI_AHB_DMA_CONF0_INCR16 = 0x4, - HDMI_AHB_DMA_CONF0_BURST_MODE = 0x1, - -/* HDMI_AHB_DMA_START field values */ - HDMI_AHB_DMA_START_START_OFFSET = 0, - HDMI_AHB_DMA_START_START_MASK = 0x01, - -/* HDMI_AHB_DMA_STOP field values */ - HDMI_AHB_DMA_STOP_STOP_OFFSET = 0, - HDMI_AHB_DMA_STOP_STOP_MASK = 0x01, - -/* AHB_DMA_STAT, AHB_DMA_INT, AHB_DMA_MASK, AHB_DMA_POL field values */ - HDMI_AHB_DMA_DONE = 0x80, - HDMI_AHB_DMA_RETRY_SPLIT = 0x40, - HDMI_AHB_DMA_LOSTOWNERSHIP = 0x20, - HDMI_AHB_DMA_ERROR = 0x10, - HDMI_AHB_DMA_FIFO_THREMPTY = 0x04, - HDMI_AHB_DMA_FIFO_FULL = 0x02, - HDMI_AHB_DMA_FIFO_EMPTY = 0x01, - -/* AHB_DMA_BUFFSTAT, AHB_DMA_BUFFINT,AHB_DMA_BUFFMASK,AHB_DMA_BUFFPOL values */ - HDMI_AHB_DMA_BUFFSTAT_FULL = 0x02, - HDMI_AHB_DMA_BUFFSTAT_EMPTY = 0x01, - -/* MC_CLKDIS field values */ - HDMI_MC_CLKDIS_HDCPCLK_DISABLE = 0x40, - HDMI_MC_CLKDIS_CECCLK_DISABLE = 0x20, - HDMI_MC_CLKDIS_CSCCLK_DISABLE = 0x10, - HDMI_MC_CLKDIS_AUDCLK_DISABLE = 0x8, - HDMI_MC_CLKDIS_PREPCLK_DISABLE = 0x4, - HDMI_MC_CLKDIS_TMDSCLK_DISABLE = 0x2, - HDMI_MC_CLKDIS_PIXELCLK_DISABLE = 0x1, - -/* MC_SWRSTZ field values */ - HDMI_MC_SWRSTZ_TMDSSWRST_REQ = 0x02, - -/* MC_FLOWCTRL field values */ - HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_MASK = 0x1, - HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_CSC_IN_PATH = 0x1, - HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_CSC_BYPASS = 0x0, - -/* MC_PHYRSTZ field values */ - HDMI_MC_PHYRSTZ_ASSERT = 0x0, - HDMI_MC_PHYRSTZ_DEASSERT = 0x1, - -/* MC_HEACPHY_RST field values */ - HDMI_MC_HEACPHY_RST_ASSERT = 0x1, - HDMI_MC_HEACPHY_RST_DEASSERT = 0x0, - -/* CSC_CFG field values */ - HDMI_CSC_CFG_INTMODE_MASK = 0x30, - HDMI_CSC_CFG_INTMODE_OFFSET = 4, - HDMI_CSC_CFG_INTMODE_DISABLE = 0x00, - HDMI_CSC_CFG_INTMODE_CHROMA_INT_FORMULA1 = 0x10, - HDMI_CSC_CFG_INTMODE_CHROMA_INT_FORMULA2 = 0x20, - HDMI_CSC_CFG_DECMODE_MASK = 0x3, - HDMI_CSC_CFG_DECMODE_OFFSET = 0, - HDMI_CSC_CFG_DECMODE_DISABLE = 0x0, - HDMI_CSC_CFG_DECMODE_CHROMA_INT_FORMULA1 = 0x1, - HDMI_CSC_CFG_DECMODE_CHROMA_INT_FORMULA2 = 0x2, - HDMI_CSC_CFG_DECMODE_CHROMA_INT_FORMULA3 = 0x3, - -/* CSC_SCALE field values */ - HDMI_CSC_SCALE_CSC_COLORDE_PTH_MASK = 0xF0, - HDMI_CSC_SCALE_CSC_COLORDE_PTH_24BPP = 0x00, - HDMI_CSC_SCALE_CSC_COLORDE_PTH_30BPP = 0x50, - HDMI_CSC_SCALE_CSC_COLORDE_PTH_36BPP = 0x60, - HDMI_CSC_SCALE_CSC_COLORDE_PTH_48BPP = 0x70, - HDMI_CSC_SCALE_CSCSCALE_MASK = 0x03, - -/* A_HDCPCFG0 field values */ - HDMI_A_HDCPCFG0_ELVENA_MASK = 0x80, - HDMI_A_HDCPCFG0_ELVENA_ENABLE = 0x80, - HDMI_A_HDCPCFG0_ELVENA_DISABLE = 0x00, - HDMI_A_HDCPCFG0_I2CFASTMODE_MASK = 0x40, - HDMI_A_HDCPCFG0_I2CFASTMODE_ENABLE = 0x40, - HDMI_A_HDCPCFG0_I2CFASTMODE_DISABLE = 0x00, - HDMI_A_HDCPCFG0_BYPENCRYPTION_MASK = 0x20, - HDMI_A_HDCPCFG0_BYPENCRYPTION_ENABLE = 0x20, - HDMI_A_HDCPCFG0_BYPENCRYPTION_DISABLE = 0x00, - HDMI_A_HDCPCFG0_SYNCRICHECK_MASK = 0x10, - HDMI_A_HDCPCFG0_SYNCRICHECK_ENABLE = 0x10, - HDMI_A_HDCPCFG0_SYNCRICHECK_DISABLE = 0x00, - HDMI_A_HDCPCFG0_AVMUTE_MASK = 0x8, - HDMI_A_HDCPCFG0_AVMUTE_ENABLE = 0x8, - HDMI_A_HDCPCFG0_AVMUTE_DISABLE = 0x0, - HDMI_A_HDCPCFG0_RXDETECT_MASK = 0x4, - HDMI_A_HDCPCFG0_RXDETECT_ENABLE = 0x4, - HDMI_A_HDCPCFG0_RXDETECT_DISABLE = 0x0, - HDMI_A_HDCPCFG0_EN11FEATURE_MASK = 0x2, - HDMI_A_HDCPCFG0_EN11FEATURE_ENABLE = 0x2, - HDMI_A_HDCPCFG0_EN11FEATURE_DISABLE = 0x0, - HDMI_A_HDCPCFG0_HDMIDVI_MASK = 0x1, - HDMI_A_HDCPCFG0_HDMIDVI_HDMI = 0x1, - HDMI_A_HDCPCFG0_HDMIDVI_DVI = 0x0, - -/* A_HDCPCFG1 field values */ - HDMI_A_HDCPCFG1_DISSHA1CHECK_MASK = 0x8, - HDMI_A_HDCPCFG1_DISSHA1CHECK_DISABLE = 0x8, - HDMI_A_HDCPCFG1_DISSHA1CHECK_ENABLE = 0x0, - HDMI_A_HDCPCFG1_PH2UPSHFTENC_MASK = 0x4, - HDMI_A_HDCPCFG1_PH2UPSHFTENC_ENABLE = 0x4, - HDMI_A_HDCPCFG1_PH2UPSHFTENC_DISABLE = 0x0, - HDMI_A_HDCPCFG1_ENCRYPTIONDISABLE_MASK = 0x2, - HDMI_A_HDCPCFG1_ENCRYPTIONDISABLE_DISABLE = 0x2, - HDMI_A_HDCPCFG1_ENCRYPTIONDISABLE_ENABLE = 0x0, - HDMI_A_HDCPCFG1_SWRESET_MASK = 0x1, - HDMI_A_HDCPCFG1_SWRESET_ASSERT = 0x0, - -/* A_VIDPOLCFG field values */ - HDMI_A_VIDPOLCFG_UNENCRYPTCONF_MASK = 0x60, - HDMI_A_VIDPOLCFG_UNENCRYPTCONF_OFFSET = 5, - HDMI_A_VIDPOLCFG_DATAENPOL_MASK = 0x10, - HDMI_A_VIDPOLCFG_DATAENPOL_ACTIVE_HIGH = 0x10, - HDMI_A_VIDPOLCFG_DATAENPOL_ACTIVE_LOW = 0x0, - HDMI_A_VIDPOLCFG_VSYNCPOL_MASK = 0x8, - HDMI_A_VIDPOLCFG_VSYNCPOL_ACTIVE_HIGH = 0x8, - HDMI_A_VIDPOLCFG_VSYNCPOL_ACTIVE_LOW = 0x0, - HDMI_A_VIDPOLCFG_HSYNCPOL_MASK = 0x2, - HDMI_A_VIDPOLCFG_HSYNCPOL_ACTIVE_HIGH = 0x2, - HDMI_A_VIDPOLCFG_HSYNCPOL_ACTIVE_LOW = 0x0, -}; -#endif /* __IMX_HDMI_H__ */ diff --git a/drivers/gpu/drm/imx/imx-ldb.c b/drivers/gpu/drm/imx/imx-ldb.c index c60460043e24..1b86aac0b341 100644 --- a/drivers/gpu/drm/imx/imx-ldb.c +++ b/drivers/gpu/drm/imx/imx-ldb.c @@ -163,7 +163,7 @@ static void imx_ldb_encoder_prepare(struct drm_encoder *encoder) { struct imx_ldb_channel *imx_ldb_ch = enc_to_imx_ldb_ch(encoder); struct imx_ldb *ldb = imx_ldb_ch->ldb; - struct drm_display_mode *mode = &encoder->crtc->mode; + struct drm_display_mode *mode = &encoder->crtc->hwmode; u32 pixel_fmt; unsigned long serial_clk; unsigned long di_clk = mode->clock * 1000; @@ -241,8 +241,8 @@ static void imx_ldb_encoder_commit(struct drm_encoder *encoder) } static void imx_ldb_encoder_mode_set(struct drm_encoder *encoder, - struct drm_display_mode *mode, - struct drm_display_mode *adjusted_mode) + struct drm_display_mode *orig_mode, + struct drm_display_mode *mode) { struct imx_ldb_channel *imx_ldb_ch = enc_to_imx_ldb_ch(encoder); struct imx_ldb *ldb = imx_ldb_ch->ldb; @@ -574,6 +574,8 @@ static void imx_ldb_unbind(struct device *dev, struct device *master, channel->connector.funcs->destroy(&channel->connector); channel->encoder.funcs->destroy(&channel->encoder); + + kfree(channel->edid); } } diff --git a/drivers/gpu/drm/imx/imx-tve.c b/drivers/gpu/drm/imx/imx-tve.c index a729f4f7074c..4216e479a9be 100644 --- a/drivers/gpu/drm/imx/imx-tve.c +++ b/drivers/gpu/drm/imx/imx-tve.c @@ -191,10 +191,18 @@ static int tve_setup_vga(struct imx_tve *tve) /* set gain to (1 + 10/128) to provide 0.7V peak-to-peak amplitude */ ret = regmap_update_bits(tve->regmap, TVE_TVDAC0_CONT_REG, TVE_TVDAC_GAIN_MASK, 0x0a); + if (ret) + return ret; + ret = regmap_update_bits(tve->regmap, TVE_TVDAC1_CONT_REG, TVE_TVDAC_GAIN_MASK, 0x0a); + if (ret) + return ret; + ret = regmap_update_bits(tve->regmap, TVE_TVDAC2_CONT_REG, TVE_TVDAC_GAIN_MASK, 0x0a); + if (ret) + return ret; /* set configuration register */ mask = TVE_DATA_SOURCE_MASK | TVE_INP_VIDEO_FORM; @@ -204,16 +212,12 @@ static int tve_setup_vga(struct imx_tve *tve) mask |= TVE_TV_OUT_MODE_MASK | TVE_SYNC_CH_0_EN; val |= TVE_TV_OUT_RGB | TVE_SYNC_CH_0_EN; ret = regmap_update_bits(tve->regmap, TVE_COM_CONF_REG, mask, val); - if (ret < 0) { - dev_err(tve->dev, "failed to set configuration: %d\n", ret); + if (ret) return ret; - } /* set test mode (as documented) */ - ret = regmap_update_bits(tve->regmap, TVE_TST_MODE_REG, + return regmap_update_bits(tve->regmap, TVE_TST_MODE_REG, TVE_TVDAC_TEST_MODE_MASK, 1); - - return 0; } static enum drm_connector_status imx_tve_connector_detect( @@ -307,8 +311,8 @@ static void imx_tve_encoder_prepare(struct drm_encoder *encoder) } static void imx_tve_encoder_mode_set(struct drm_encoder *encoder, - struct drm_display_mode *mode, - struct drm_display_mode *adjusted_mode) + struct drm_display_mode *orig_mode, + struct drm_display_mode *mode) { struct imx_tve *tve = enc_to_tve(encoder); unsigned long rounded_rate; @@ -335,9 +339,11 @@ static void imx_tve_encoder_mode_set(struct drm_encoder *encoder, } if (tve->mode == TVE_MODE_VGA) - tve_setup_vga(tve); + ret = tve_setup_vga(tve); else - tve_setup_tvout(tve); + ret = tve_setup_tvout(tve); + if (ret) + dev_err(tve->dev, "failed to set configuration: %d\n", ret); } static void imx_tve_encoder_commit(struct drm_encoder *encoder) @@ -671,6 +677,8 @@ static int imx_tve_bind(struct device *dev, struct device *master, void *data) /* disable cable detection for VGA mode */ ret = regmap_write(tve->regmap, TVE_CD_CONT_REG, 0); + if (ret) + return ret; ret = imx_tve_register(drm, tve); if (ret) diff --git a/drivers/gpu/drm/imx/ipuv3-crtc.c b/drivers/gpu/drm/imx/ipuv3-crtc.c index ebee59cb96d8..98551e356e12 100644 --- a/drivers/gpu/drm/imx/ipuv3-crtc.c +++ b/drivers/gpu/drm/imx/ipuv3-crtc.c @@ -46,7 +46,6 @@ struct ipu_crtc { struct drm_framebuffer *newfb; int irq; u32 interface_pix_fmt; - unsigned long di_clkflags; int di_hsync_pin; int di_vsync_pin; }; @@ -141,47 +140,51 @@ static int ipu_crtc_mode_set(struct drm_crtc *crtc, int x, int y, struct drm_framebuffer *old_fb) { + struct drm_device *dev = crtc->dev; + struct drm_encoder *encoder; struct ipu_crtc *ipu_crtc = to_ipu_crtc(crtc); - int ret; struct ipu_di_signal_cfg sig_cfg = {}; + unsigned long encoder_types = 0; u32 out_pixel_fmt; + int ret; dev_dbg(ipu_crtc->dev, "%s: mode->hdisplay: %d\n", __func__, mode->hdisplay); dev_dbg(ipu_crtc->dev, "%s: mode->vdisplay: %d\n", __func__, mode->vdisplay); - out_pixel_fmt = ipu_crtc->interface_pix_fmt; + list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) + if (encoder->crtc == crtc) + encoder_types |= BIT(encoder->encoder_type); - if (mode->flags & DRM_MODE_FLAG_INTERLACE) - sig_cfg.interlaced = 1; - if (mode->flags & DRM_MODE_FLAG_PHSYNC) - sig_cfg.Hsync_pol = 1; - if (mode->flags & DRM_MODE_FLAG_PVSYNC) - sig_cfg.Vsync_pol = 1; + dev_dbg(ipu_crtc->dev, "%s: attached to encoder types 0x%lx\n", + __func__, encoder_types); + + /* + * If we have DAC, TVDAC or LDB, then we need the IPU DI clock + * to be the same as the LDB DI clock. + */ + if (encoder_types & (BIT(DRM_MODE_ENCODER_DAC) | + BIT(DRM_MODE_ENCODER_TVDAC) | + BIT(DRM_MODE_ENCODER_LVDS))) + sig_cfg.clkflags = IPU_DI_CLKMODE_SYNC | IPU_DI_CLKMODE_EXT; + else + sig_cfg.clkflags = 0; + + out_pixel_fmt = ipu_crtc->interface_pix_fmt; sig_cfg.enable_pol = 1; sig_cfg.clk_pol = 0; - sig_cfg.width = mode->hdisplay; - sig_cfg.height = mode->vdisplay; sig_cfg.pixel_fmt = out_pixel_fmt; - sig_cfg.h_start_width = mode->htotal - mode->hsync_end; - sig_cfg.h_sync_width = mode->hsync_end - mode->hsync_start; - sig_cfg.h_end_width = mode->hsync_start - mode->hdisplay; - - sig_cfg.v_start_width = mode->vtotal - mode->vsync_end; - sig_cfg.v_sync_width = mode->vsync_end - mode->vsync_start; - sig_cfg.v_end_width = mode->vsync_start - mode->vdisplay; - sig_cfg.pixelclock = mode->clock * 1000; - sig_cfg.clkflags = ipu_crtc->di_clkflags; - sig_cfg.v_to_h_sync = 0; - sig_cfg.hsync_pin = ipu_crtc->di_hsync_pin; sig_cfg.vsync_pin = ipu_crtc->di_vsync_pin; - ret = ipu_dc_init_sync(ipu_crtc->dc, ipu_crtc->di, sig_cfg.interlaced, - out_pixel_fmt, mode->hdisplay); + drm_display_mode_to_videomode(mode, &sig_cfg.mode); + + ret = ipu_dc_init_sync(ipu_crtc->dc, ipu_crtc->di, + mode->flags & DRM_MODE_FLAG_INTERLACE, + out_pixel_fmt, mode->hdisplay); if (ret) { dev_err(ipu_crtc->dev, "initializing display controller failed with %d\n", @@ -237,6 +240,18 @@ static bool ipu_crtc_mode_fixup(struct drm_crtc *crtc, const struct drm_display_mode *mode, struct drm_display_mode *adjusted_mode) { + struct ipu_crtc *ipu_crtc = to_ipu_crtc(crtc); + struct videomode vm; + int ret; + + drm_display_mode_to_videomode(adjusted_mode, &vm); + + ret = ipu_di_adjust_videomode(ipu_crtc->di, &vm); + if (ret) + return false; + + drm_display_mode_from_videomode(&vm, adjusted_mode); + return true; } @@ -275,7 +290,7 @@ static void ipu_disable_vblank(struct drm_crtc *crtc) ipu_crtc->newfb = NULL; } -static int ipu_set_interface_pix_fmt(struct drm_crtc *crtc, u32 encoder_type, +static int ipu_set_interface_pix_fmt(struct drm_crtc *crtc, u32 pixfmt, int hsync_pin, int vsync_pin) { struct ipu_crtc *ipu_crtc = to_ipu_crtc(crtc); @@ -284,19 +299,6 @@ static int ipu_set_interface_pix_fmt(struct drm_crtc *crtc, u32 encoder_type, ipu_crtc->di_hsync_pin = hsync_pin; ipu_crtc->di_vsync_pin = vsync_pin; - switch (encoder_type) { - case DRM_MODE_ENCODER_DAC: - case DRM_MODE_ENCODER_TVDAC: - case DRM_MODE_ENCODER_LVDS: - ipu_crtc->di_clkflags = IPU_DI_CLKMODE_SYNC | - IPU_DI_CLKMODE_EXT; - break; - case DRM_MODE_ENCODER_TMDS: - case DRM_MODE_ENCODER_NONE: - ipu_crtc->di_clkflags = 0; - break; - } - return 0; } diff --git a/drivers/gpu/drm/imx/parallel-display.c b/drivers/gpu/drm/imx/parallel-display.c index 796c3c1c170a..5e83e007080f 100644 --- a/drivers/gpu/drm/imx/parallel-display.c +++ b/drivers/gpu/drm/imx/parallel-display.c @@ -130,8 +130,8 @@ static void imx_pd_encoder_commit(struct drm_encoder *encoder) } static void imx_pd_encoder_mode_set(struct drm_encoder *encoder, - struct drm_display_mode *mode, - struct drm_display_mode *adjusted_mode) + struct drm_display_mode *orig_mode, + struct drm_display_mode *mode) { } @@ -257,6 +257,8 @@ static void imx_pd_unbind(struct device *dev, struct device *master, imxpd->encoder.funcs->destroy(&imxpd->encoder); imxpd->connector.funcs->destroy(&imxpd->connector); + + kfree(imxpd->edid); } static const struct component_ops imx_pd_ops = { @@ -272,6 +274,7 @@ static int imx_pd_probe(struct platform_device *pdev) static int imx_pd_remove(struct platform_device *pdev) { component_del(&pdev->dev, &imx_pd_ops); + return 0; } |