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path: root/drivers/gpu/drm/i915/gvt/fb_decoder.c
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Diffstat (limited to 'drivers/gpu/drm/i915/gvt/fb_decoder.c')
-rw-r--r--drivers/gpu/drm/i915/gvt/fb_decoder.c49
1 files changed, 25 insertions, 24 deletions
diff --git a/drivers/gpu/drm/i915/gvt/fb_decoder.c b/drivers/gpu/drm/i915/gvt/fb_decoder.c
index 9ec064199364..835c3fde8a20 100644
--- a/drivers/gpu/drm/i915/gvt/fb_decoder.c
+++ b/drivers/gpu/drm/i915/gvt/fb_decoder.c
@@ -37,15 +37,16 @@
#include "i915_drv.h"
#include "gvt.h"
#include "i915_pvinfo.h"
+#include "i915_reg.h"
#define PRIMARY_FORMAT_NUM 16
struct pixel_format {
- int drm_format; /* Pixel format in DRM definition */
- int bpp; /* Bits per pixel, 0 indicates invalid */
- char *desc; /* The description */
+ int drm_format; /* Pixel format in DRM definition */
+ int bpp; /* Bits per pixel, 0 indicates invalid */
+ const char *desc; /* The description */
};
-static struct pixel_format bdw_pixel_formats[] = {
+static const struct pixel_format bdw_pixel_formats[] = {
{DRM_FORMAT_C8, 8, "8-bit Indexed"},
{DRM_FORMAT_RGB565, 16, "16-bit BGRX (5:6:5 MSB-R:G:B)"},
{DRM_FORMAT_XRGB8888, 32, "32-bit BGRX (8:8:8:8 MSB-X:R:G:B)"},
@@ -58,7 +59,7 @@ static struct pixel_format bdw_pixel_formats[] = {
{0, 0, NULL},
};
-static struct pixel_format skl_pixel_formats[] = {
+static const struct pixel_format skl_pixel_formats[] = {
{DRM_FORMAT_YUYV, 16, "16-bit packed YUYV (8:8:8:8 MSB-V:Y2:U:Y1)"},
{DRM_FORMAT_UYVY, 16, "16-bit packed UYVY (8:8:8:8 MSB-Y2:V:Y1:U)"},
{DRM_FORMAT_YVYU, 16, "16-bit packed YVYU (8:8:8:8 MSB-U:Y2:V:Y1)"},
@@ -83,22 +84,22 @@ static int bdw_format_to_drm(int format)
int bdw_pixel_formats_index = 6;
switch (format) {
- case DISPPLANE_8BPP:
+ case DISP_FORMAT_8BPP:
bdw_pixel_formats_index = 0;
break;
- case DISPPLANE_BGRX565:
+ case DISP_FORMAT_BGRX565:
bdw_pixel_formats_index = 1;
break;
- case DISPPLANE_BGRX888:
+ case DISP_FORMAT_BGRX888:
bdw_pixel_formats_index = 2;
break;
- case DISPPLANE_RGBX101010:
+ case DISP_FORMAT_RGBX101010:
bdw_pixel_formats_index = 3;
break;
- case DISPPLANE_BGRX101010:
+ case DISP_FORMAT_BGRX101010:
bdw_pixel_formats_index = 4;
break;
- case DISPPLANE_RGBX888:
+ case DISP_FORMAT_RGBX888:
bdw_pixel_formats_index = 5;
break;
@@ -211,14 +212,14 @@ int intel_vgpu_decode_primary_plane(struct intel_vgpu *vgpu,
return -ENODEV;
val = vgpu_vreg_t(vgpu, DSPCNTR(pipe));
- plane->enabled = !!(val & DISPLAY_PLANE_ENABLE);
+ plane->enabled = !!(val & DISP_ENABLE);
if (!plane->enabled)
return -ENODEV;
if (GRAPHICS_VER(dev_priv) >= 9) {
plane->tiled = val & PLANE_CTL_TILED_MASK;
fmt = skl_format_to_drm(
- val & PLANE_CTL_FORMAT_MASK,
+ val & PLANE_CTL_FORMAT_MASK_SKL,
val & PLANE_CTL_ORDER_RGBX,
val & PLANE_CTL_ALPHA_MASK,
val & PLANE_CTL_YUV422_ORDER_MASK);
@@ -231,8 +232,8 @@ int intel_vgpu_decode_primary_plane(struct intel_vgpu *vgpu,
plane->bpp = skl_pixel_formats[fmt].bpp;
plane->drm_format = skl_pixel_formats[fmt].drm_format;
} else {
- plane->tiled = val & DISPPLANE_TILED;
- fmt = bdw_format_to_drm(val & DISPPLANE_PIXFORMAT_MASK);
+ plane->tiled = val & DISP_TILED;
+ fmt = bdw_format_to_drm(val & DISP_FORMAT_MASK);
plane->bpp = bdw_pixel_formats[fmt].bpp;
plane->drm_format = bdw_pixel_formats[fmt].drm_format;
}
@@ -278,14 +279,14 @@ int intel_vgpu_decode_primary_plane(struct intel_vgpu *vgpu,
#define CURSOR_FORMAT_NUM (1 << 6)
struct cursor_mode_format {
- int drm_format; /* Pixel format in DRM definition */
- u8 bpp; /* Bits per pixel; 0 indicates invalid */
- u32 width; /* In pixel */
- u32 height; /* In lines */
- char *desc; /* The description */
+ int drm_format; /* Pixel format in DRM definition */
+ u8 bpp; /* Bits per pixel; 0 indicates invalid */
+ u32 width; /* In pixel */
+ u32 height; /* In lines */
+ const char *desc; /* The description */
};
-static struct cursor_mode_format cursor_pixel_formats[] = {
+static const struct cursor_mode_format cursor_pixel_formats[] = {
{DRM_FORMAT_ARGB8888, 32, 128, 128, "128x128 32bpp ARGB"},
{DRM_FORMAT_ARGB8888, 32, 256, 256, "256x256 32bpp ARGB"},
{DRM_FORMAT_ARGB8888, 32, 64, 64, "64x64 32bpp ARGB"},
@@ -342,7 +343,7 @@ int intel_vgpu_decode_cursor_plane(struct intel_vgpu *vgpu,
return -ENODEV;
val = vgpu_vreg_t(vgpu, CURCNTR(pipe));
- mode = val & MCURSOR_MODE;
+ mode = val & MCURSOR_MODE_MASK;
plane->enabled = (mode != MCURSOR_MODE_DISABLE);
if (!plane->enabled)
return -ENODEV;
@@ -391,7 +392,7 @@ int intel_vgpu_decode_cursor_plane(struct intel_vgpu *vgpu,
#define SPRITE_FORMAT_NUM (1 << 3)
-static struct pixel_format sprite_pixel_formats[SPRITE_FORMAT_NUM] = {
+static const struct pixel_format sprite_pixel_formats[SPRITE_FORMAT_NUM] = {
[0x0] = {DRM_FORMAT_YUV422, 16, "YUV 16-bit 4:2:2 packed"},
[0x1] = {DRM_FORMAT_XRGB2101010, 32, "RGB 32-bit 2:10:10:10"},
[0x2] = {DRM_FORMAT_XRGB8888, 32, "RGB 32-bit 8:8:8:8"},
@@ -430,7 +431,7 @@ int intel_vgpu_decode_sprite_plane(struct intel_vgpu *vgpu,
yuv_order = (val & SPRITE_YUV_ORDER_MASK) >>
_SPRITE_YUV_ORDER_SHIFT;
- fmt = (val & SPRITE_PIXFORMAT_MASK) >> _SPRITE_FMT_SHIFT;
+ fmt = (val & SPRITE_FORMAT_MASK) >> _SPRITE_FMT_SHIFT;
if (!sprite_pixel_formats[fmt].bpp) {
gvt_vgpu_err("Non-supported pixel format (0x%x)\n", fmt);
return -EINVAL;