summaryrefslogtreecommitdiff
path: root/arch/mn10300/unit-asb2364/include/unit/fpga-regs.h
diff options
context:
space:
mode:
Diffstat (limited to 'arch/mn10300/unit-asb2364/include/unit/fpga-regs.h')
-rw-r--r--arch/mn10300/unit-asb2364/include/unit/fpga-regs.h24
1 files changed, 13 insertions, 11 deletions
diff --git a/arch/mn10300/unit-asb2364/include/unit/fpga-regs.h b/arch/mn10300/unit-asb2364/include/unit/fpga-regs.h
index a039a50c91db..7cf12054db65 100644
--- a/arch/mn10300/unit-asb2364/include/unit/fpga-regs.h
+++ b/arch/mn10300/unit-asb2364/include/unit/fpga-regs.h
@@ -14,17 +14,19 @@
#define ASB2364_FPGA_REG_RESET_USB __SYSREG(0xa900130c, u16)
#define ASB2364_FPGA_REG_RESET_AV __SYSREG(0xa9001310, u16)
-#define ASB2364_FPGA_REG_IRQ_LAN __SYSREG(0xa9001510, u16)
-#define ASB2364_FPGA_REG_IRQ_UART __SYSREG(0xa9001514, u16)
-#define ASB2364_FPGA_REG_IRQ_I2C __SYSREG(0xa9001518, u16)
-#define ASB2364_FPGA_REG_IRQ_USB __SYSREG(0xa900151c, u16)
-#define ASB2364_FPGA_REG_IRQ_FPGA __SYSREG(0xa9001524, u16)
-
-#define ASB2364_FPGA_REG_MASK_LAN __SYSREG(0xa9001590, u16)
-#define ASB2364_FPGA_REG_MASK_UART __SYSREG(0xa9001594, u16)
-#define ASB2364_FPGA_REG_MASK_I2C __SYSREG(0xa9001598, u16)
-#define ASB2364_FPGA_REG_MASK_USB __SYSREG(0xa900159c, u16)
-#define ASB2364_FPGA_REG_MASK_FPGA __SYSREG(0xa90015a4, u16)
+#define ASB2364_FPGA_REG_IRQ(X) __SYSREG(0xa9001590+((X)*4), u16)
+#define ASB2364_FPGA_REG_IRQ_LAN ASB2364_FPGA_REG_IRQ(0)
+#define ASB2364_FPGA_REG_IRQ_UART ASB2364_FPGA_REG_IRQ(1)
+#define ASB2364_FPGA_REG_IRQ_I2C ASB2364_FPGA_REG_IRQ(2)
+#define ASB2364_FPGA_REG_IRQ_USB ASB2364_FPGA_REG_IRQ(3)
+#define ASB2364_FPGA_REG_IRQ_FPGA ASB2364_FPGA_REG_IRQ(5)
+
+#define ASB2364_FPGA_REG_MASK(X) __SYSREG(0xa9001590+((X)*4), u16)
+#define ASB2364_FPGA_REG_MASK_LAN ASB2364_FPGA_REG_MASK(0)
+#define ASB2364_FPGA_REG_MASK_UART ASB2364_FPGA_REG_MASK(1)
+#define ASB2364_FPGA_REG_MASK_I2C ASB2364_FPGA_REG_MASK(2)
+#define ASB2364_FPGA_REG_MASK_USB ASB2364_FPGA_REG_MASK(3)
+#define ASB2364_FPGA_REG_MASK_FPGA ASB2364_FPGA_REG_MASK(5)
#define ASB2364_FPGA_REG_CPLD5_SET1 __SYSREG(0xa9002500, u16)
#define ASB2364_FPGA_REG_CPLD5_SET2 __SYSREG(0xa9002504, u16)