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Diffstat (limited to 'arch/arm64/boot/dts/renesas/r8a7796.dtsi')
-rw-r--r--arch/arm64/boot/dts/renesas/r8a7796.dtsi130
1 files changed, 123 insertions, 7 deletions
diff --git a/arch/arm64/boot/dts/renesas/r8a7796.dtsi b/arch/arm64/boot/dts/renesas/r8a7796.dtsi
index c5192d513d7d..556eb8e45499 100644
--- a/arch/arm64/boot/dts/renesas/r8a7796.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a7796.dtsi
@@ -71,6 +71,9 @@
power-domains = <&sysc R8A7796_PD_CA57_CPU0>;
next-level-cache = <&L2_CA57>;
enable-method = "psci";
+ clocks =<&cpg CPG_CORE R8A7796_CLK_Z>;
+ operating-points-v2 = <&cluster0_opp>;
+ #cooling-cells = <2>;
};
a57_1: cpu@1 {
@@ -80,6 +83,9 @@
power-domains = <&sysc R8A7796_PD_CA57_CPU1>;
next-level-cache = <&L2_CA57>;
enable-method = "psci";
+ clocks =<&cpg CPG_CORE R8A7796_CLK_Z>;
+ operating-points-v2 = <&cluster0_opp>;
+ #cooling-cells = <2>;
};
a53_0: cpu@100 {
@@ -89,6 +95,8 @@
power-domains = <&sysc R8A7796_PD_CA53_CPU0>;
next-level-cache = <&L2_CA53>;
enable-method = "psci";
+ clocks =<&cpg CPG_CORE R8A7796_CLK_Z2>;
+ operating-points-v2 = <&cluster1_opp>;
};
a53_1: cpu@101 {
@@ -98,6 +106,8 @@
power-domains = <&sysc R8A7796_PD_CA53_CPU1>;
next-level-cache = <&L2_CA53>;
enable-method = "psci";
+ clocks =<&cpg CPG_CORE R8A7796_CLK_Z2>;
+ operating-points-v2 = <&cluster1_opp>;
};
a53_2: cpu@102 {
@@ -107,6 +117,8 @@
power-domains = <&sysc R8A7796_PD_CA53_CPU2>;
next-level-cache = <&L2_CA53>;
enable-method = "psci";
+ clocks =<&cpg CPG_CORE R8A7796_CLK_Z2>;
+ operating-points-v2 = <&cluster1_opp>;
};
a53_3: cpu@103 {
@@ -116,6 +128,8 @@
power-domains = <&sysc R8A7796_PD_CA53_CPU3>;
next-level-cache = <&L2_CA53>;
enable-method = "psci";
+ clocks =<&cpg CPG_CORE R8A7796_CLK_Z2>;
+ operating-points-v2 = <&cluster1_opp>;
};
L2_CA57: cache-controller-0 {
@@ -147,6 +161,72 @@
clock-frequency = <0>;
};
+ cluster0_opp: opp_table0 {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ opp-500000000 {
+ opp-hz = /bits/ 64 <500000000>;
+ opp-microvolt = <820000>;
+ clock-latency-ns = <300000>;
+ };
+ opp-1000000000 {
+ opp-hz = /bits/ 64 <1000000000>;
+ opp-microvolt = <820000>;
+ clock-latency-ns = <300000>;
+ };
+ opp-1500000000 {
+ opp-hz = /bits/ 64 <1500000000>;
+ opp-microvolt = <820000>;
+ clock-latency-ns = <300000>;
+ };
+ opp-1600000000 {
+ opp-hz = /bits/ 64 <1600000000>;
+ opp-microvolt = <900000>;
+ clock-latency-ns = <300000>;
+ turbo-mode;
+ };
+ opp-1700000000 {
+ opp-hz = /bits/ 64 <1700000000>;
+ opp-microvolt = <900000>;
+ clock-latency-ns = <300000>;
+ turbo-mode;
+ };
+ opp-1800000000 {
+ opp-hz = /bits/ 64 <1800000000>;
+ opp-microvolt = <960000>;
+ clock-latency-ns = <300000>;
+ turbo-mode;
+ };
+ };
+
+ cluster1_opp: opp_table1 {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ opp-800000000 {
+ opp-hz = /bits/ 64 <800000000>;
+ opp-microvolt = <820000>;
+ clock-latency-ns = <300000>;
+ };
+ opp-1000000000 {
+ opp-hz = /bits/ 64 <1000000000>;
+ opp-microvolt = <820000>;
+ clock-latency-ns = <300000>;
+ };
+ opp-1200000000 {
+ opp-hz = /bits/ 64 <1200000000>;
+ opp-microvolt = <820000>;
+ clock-latency-ns = <300000>;
+ };
+ opp-1300000000 {
+ opp-hz = /bits/ 64 <1300000000>;
+ opp-microvolt = <820000>;
+ clock-latency-ns = <300000>;
+ turbo-mode;
+ };
+ };
+
/* External PCIe clock - can be overridden by the board */
pcie_bus_clk: pcie_bus {
compatible = "fixed-clock";
@@ -894,7 +974,7 @@
clocks = <&cpg CPG_MOD 812>;
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
resets = <&cpg 812>;
- phy-mode = "rgmii-txid";
+ phy-mode = "rgmii";
iommus = <&ipmmu_ds0 16>;
#address-cells = <1>;
#size-cells = <0>;
@@ -1561,9 +1641,9 @@
tsc: thermal@e6198000 {
compatible = "renesas,r8a7796-thermal";
- reg = <0 0xe6198000 0 0x68>,
- <0 0xe61a0000 0 0x5c>,
- <0 0xe61a8000 0 0x5c>;
+ reg = <0 0xe6198000 0 0x100>,
+ <0 0xe61a0000 0 0x100>,
+ <0 0xe61a8000 0 0x100>;
interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
@@ -1839,7 +1919,7 @@
vspd0: vsp@fea20000 {
compatible = "renesas,vsp2";
- reg = <0 0xfea20000 0 0x4000>;
+ reg = <0 0xfea20000 0 0x8000>;
interrupts = <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 623>;
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
@@ -1859,7 +1939,7 @@
vspd1: vsp@fea28000 {
compatible = "renesas,vsp2";
- reg = <0 0xfea28000 0 0x4000>;
+ reg = <0 0xfea28000 0 0x8000>;
interrupts = <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 622>;
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
@@ -1879,7 +1959,7 @@
vspd2: vsp@fea30000 {
compatible = "renesas,vsp2";
- reg = <0 0xfea30000 0 0x4000>;
+ reg = <0 0xfea30000 0 0x8000>;
interrupts = <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 621>;
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
@@ -1998,12 +2078,24 @@
thermal-sensors = <&tsc 0>;
trips {
+ sensor1_passive: sensor1-passive {
+ temperature = <95000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
sensor1_crit: sensor1-crit {
temperature = <120000>;
hysteresis = <2000>;
type = "critical";
};
};
+
+ cooling-maps {
+ map0 {
+ trip = <&sensor1_passive>;
+ cooling-device = <&a57_0 5 5>;
+ };
+ };
};
sensor_thermal2: sensor-thermal2 {
@@ -2012,12 +2104,24 @@
thermal-sensors = <&tsc 1>;
trips {
+ sensor2_passive: sensor2-passive {
+ temperature = <95000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
sensor2_crit: sensor2-crit {
temperature = <120000>;
hysteresis = <2000>;
type = "critical";
};
};
+
+ cooling-maps {
+ map0 {
+ trip = <&sensor2_passive>;
+ cooling-device = <&a57_0 5 5>;
+ };
+ };
};
sensor_thermal3: sensor-thermal3 {
@@ -2026,12 +2130,24 @@
thermal-sensors = <&tsc 2>;
trips {
+ sensor3_passive: sensor3-passive {
+ temperature = <95000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
sensor3_crit: sensor3-crit {
temperature = <120000>;
hysteresis = <2000>;
type = "critical";
};
};
+
+ cooling-maps {
+ map0 {
+ trip = <&sensor3_passive>;
+ cooling-device = <&a57_0 5 5>;
+ };
+ };
};
};
generated by cgit v1.2.3 (git 2.39.0) at 2024-11-26 08:18:07 +0300