diff options
Diffstat (limited to 'arch/arm64/boot/dts/freescale/s32g2.dtsi')
| -rw-r--r-- | arch/arm64/boot/dts/freescale/s32g2.dtsi | 250 |
1 files changed, 250 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/freescale/s32g2.dtsi b/arch/arm64/boot/dts/freescale/s32g2.dtsi index 7be430b78c83..09d2fbbe1d8c 100644 --- a/arch/arm64/boot/dts/freescale/s32g2.dtsi +++ b/arch/arm64/boot/dts/freescale/s32g2.dtsi @@ -114,6 +114,14 @@ #size-cells = <1>; ranges = <0 0 0 0x80000000>; + rtc0: rtc@40060000 { + compatible = "nxp,s32g2-rtc"; + reg = <0x40060000 0x1000>; + interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks 54>, <&clks 55>; + clock-names = "ipg", "source0"; + }; + pinctrl: pinctrl@4009c240 { compatible = "nxp,s32g2-siul2-pinctrl"; /* MSCR0-MSCR101 registers on siul2_0 */ @@ -317,6 +325,49 @@ }; }; + edma0: dma-controller@40144000 { + compatible = "nxp,s32g2-edma"; + reg = <0x40144000 0x24000>, + <0x4012c000 0x3000>, + <0x40130000 0x3000>; + #dma-cells = <2>; + dma-channels = <32>; + interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "tx-0-15", + "tx-16-31", + "err"; + clocks = <&clks 63>, <&clks 64>; + clock-names = "dmamux0", "dmamux1"; + }; + + can0: can@401b4000 { + compatible = "nxp,s32g2-flexcan"; + reg = <0x401b4000 0xa000>; + interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "mb-0", "state", "berr", "mb-1"; + clocks = <&clks 9>, <&clks 11>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + + can1: can@401be000 { + compatible = "nxp,s32g2-flexcan"; + reg = <0x401be000 0xa000>; + interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "mb-0", "state", "berr", "mb-1"; + clocks = <&clks 9>, <&clks 11>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + uart0: serial@401c8000 { compatible = "nxp,s32g2-linflexuart", "fsl,s32v234-linflexuart"; @@ -333,6 +384,144 @@ status = "disabled"; }; + usbmisc: usbmisc@44064200 { + #index-cells = <1>; + compatible = "nxp,s32g2-usbmisc"; + reg = <0x44064200 0x200>; + }; + + usbotg: usb@44064000 { + compatible = "nxp,s32g2-usb"; + reg = <0x44064000 0x200>; + interrupt-parent = <&gic>; + interrupts = <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>, /* OTG Core */ + <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>; /* OTG Wakeup */ + clocks = <&clks 94>, <&clks 95>; + fsl,usbmisc = <&usbmisc 0>; + ahb-burst-config = <0x3>; + tx-burst-size-dword = <0x10>; + rx-burst-size-dword = <0x10>; + phy_type = "ulpi"; + dr_mode = "host"; + maximum-speed = "high-speed"; + status = "disabled"; + }; + + spi0: spi@401d4000 { + compatible = "nxp,s32g2-dspi"; + reg = <0x401d4000 0x1000>; + interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks 26>; + clock-names = "dspi"; + spi-num-chipselects = <8>; + bus-num = <0>; + dmas = <&edma0 0 7>, <&edma0 0 8>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + spi1: spi@401d8000 { + compatible = "nxp,s32g2-dspi"; + reg = <0x401d8000 0x1000>; + interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks 26>; + clock-names = "dspi"; + spi-num-chipselects = <5>; + bus-num = <1>; + dmas = <&edma0 0 10>, <&edma0 0 11>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + spi2: spi@401dc000 { + compatible = "nxp,s32g2-dspi"; + reg = <0x401dc000 0x1000>; + interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks 26>; + clock-names = "dspi"; + spi-num-chipselects = <5>; + bus-num = <2>; + dmas = <&edma0 0 13>, <&edma0 0 14>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + i2c0: i2c@401e4000 { + compatible = "nxp,s32g2-i2c"; + reg = <0x401e4000 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks 40>; + clock-names = "ipg"; + status = "disabled"; + }; + + i2c1: i2c@401e8000 { + compatible = "nxp,s32g2-i2c"; + reg = <0x401e8000 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks 40>; + clock-names = "ipg"; + status = "disabled"; + }; + + i2c2: i2c@401ec000 { + compatible = "nxp,s32g2-i2c"; + reg = <0x401ec000 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks 40>; + clock-names = "ipg"; + status = "disabled"; + }; + + edma1: dma-controller@40244000 { + compatible = "nxp,s32g2-edma"; + reg = <0x40244000 0x24000>, + <0x4022c000 0x3000>, + <0x40230000 0x3000>; + #dma-cells = <2>; + dma-channels = <32>; + interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "tx-0-15", + "tx-16-31", + "err"; + clocks = <&clks 63>, <&clks 64>; + clock-names = "dmamux0", "dmamux1"; + }; + + can2: can@402a8000 { + compatible = "nxp,s32g2-flexcan"; + reg = <0x402a8000 0xa000>; + interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "mb-0", "state", "berr", "mb-1"; + clocks = <&clks 9>, <&clks 11>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + + can3: can@402b2000 { + compatible = "nxp,s32g2-flexcan"; + reg = <0x402b2000 0xa000>; + interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "mb-0", "state", "berr", "mb-1"; + clocks = <&clks 9>, <&clks 11>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + uart2: serial@402bc000 { compatible = "nxp,s32g2-linflexuart", "fsl,s32v234-linflexuart"; @@ -341,6 +530,67 @@ status = "disabled"; }; + spi3: spi@402c8000 { + compatible = "nxp,s32g2-dspi"; + reg = <0x402c8000 0x1000>; + interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks 26>; + clock-names = "dspi"; + spi-num-chipselects = <5>; + bus-num = <3>; + dmas = <&edma0 1 7>, <&edma0 1 8>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + spi4: spi@402cc000 { + compatible = "nxp,s32g2-dspi"; + reg = <0x402cc000 0x1000>; + interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks 26>; + clock-names = "dspi"; + spi-num-chipselects = <5>; + bus-num = <4>; + dmas = <&edma0 1 10>, <&edma0 1 11>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + spi5: spi@402d0000 { + compatible = "nxp,s32g2-dspi"; + reg = <0x402d0000 0x1000>; + interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks 26>; + clock-names = "dspi"; + spi-num-chipselects = <5>; + bus-num = <5>; + dmas = <&edma0 1 13>, <&edma0 1 14>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + i2c3: i2c@402d8000 { + compatible = "nxp,s32g2-i2c"; + reg = <0x402d8000 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks 40>; + clock-names = "ipg"; + status = "disabled"; + }; + + i2c4: i2c@402dc000 { + compatible = "nxp,s32g2-i2c"; + reg = <0x402dc000 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks 40>; + clock-names = "ipg"; + status = "disabled"; + }; + usdhc0: mmc@402f0000 { compatible = "nxp,s32g2-usdhc"; reg = <0x402f0000 0x1000>; |