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-rw-r--r--arch/arm/mach-pxa/include/mach/eseries-gpio.h63
-rw-r--r--arch/arm/mach-pxa/include/mach/irqs.h109
-rw-r--r--arch/arm/mach-pxa/include/mach/magician.h125
-rw-r--r--arch/arm/mach-pxa/include/mach/mfp.h18
-rw-r--r--arch/arm/mach-pxa/include/mach/pxa-regs.h52
-rw-r--r--arch/arm/mach-pxa/include/mach/pxa2xx-regs.h149
-rw-r--r--arch/arm/mach-pxa/include/mach/pxa3xx-regs.h134
-rw-r--r--arch/arm/mach-pxa/include/mach/regs-ost.h37
-rw-r--r--arch/arm/mach-pxa/include/mach/reset.h22
-rw-r--r--arch/arm/mach-pxa/include/mach/smemc.h72
-rw-r--r--arch/arm/mach-pxa/include/mach/tosa.h165
-rw-r--r--arch/arm/mach-pxa/include/mach/z2.h37
12 files changed, 0 insertions, 983 deletions
diff --git a/arch/arm/mach-pxa/include/mach/eseries-gpio.h b/arch/arm/mach-pxa/include/mach/eseries-gpio.h
deleted file mode 100644
index 5c645600d401..000000000000
--- a/arch/arm/mach-pxa/include/mach/eseries-gpio.h
+++ /dev/null
@@ -1,63 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-/*
- * eseries-gpio.h
- *
- * Copyright (C) Ian Molton <spyro@f2s.com>
- */
-
-/* e-series power button */
-#define GPIO_ESERIES_POWERBTN 0
-
-/* UDC GPIO definitions */
-#define GPIO_E7XX_USB_DISC 13
-#define GPIO_E7XX_USB_PULLUP 3
-
-#define GPIO_E800_USB_DISC 4
-#define GPIO_E800_USB_PULLUP 84
-
-/* e740 PCMCIA GPIO definitions */
-/* Note: PWR1 seems to be inverted */
-#define GPIO_E740_PCMCIA_CD0 8
-#define GPIO_E740_PCMCIA_CD1 44
-#define GPIO_E740_PCMCIA_RDY0 11
-#define GPIO_E740_PCMCIA_RDY1 6
-#define GPIO_E740_PCMCIA_RST0 27
-#define GPIO_E740_PCMCIA_RST1 24
-#define GPIO_E740_PCMCIA_PWR0 20
-#define GPIO_E740_PCMCIA_PWR1 23
-
-/* e750 PCMCIA GPIO definitions */
-#define GPIO_E750_PCMCIA_CD0 8
-#define GPIO_E750_PCMCIA_RDY0 12
-#define GPIO_E750_PCMCIA_RST0 27
-#define GPIO_E750_PCMCIA_PWR0 20
-
-/* e800 PCMCIA GPIO definitions */
-#define GPIO_E800_PCMCIA_RST0 69
-#define GPIO_E800_PCMCIA_RST1 72
-#define GPIO_E800_PCMCIA_PWR0 20
-#define GPIO_E800_PCMCIA_PWR1 73
-
-/* e7xx IrDA power control */
-#define GPIO_E7XX_IR_OFF 38
-
-/* e740 audio control GPIOs */
-#define GPIO_E740_WM9705_nAVDD2 16
-#define GPIO_E740_MIC_ON 40
-#define GPIO_E740_AMP_ON 41
-
-/* e750 audio control GPIOs */
-#define GPIO_E750_HP_AMP_OFF 4
-#define GPIO_E750_SPK_AMP_OFF 7
-#define GPIO_E750_HP_DETECT 37
-
-/* e800 audio control GPIOs */
-#define GPIO_E800_HP_DETECT 81
-#define GPIO_E800_HP_AMP_OFF 82
-#define GPIO_E800_SPK_AMP_ON 83
-
-/* ASIC related GPIOs */
-#define GPIO_ESERIES_TMIO_IRQ 5
-#define GPIO_ESERIES_TMIO_PCLR 19
-#define GPIO_ESERIES_TMIO_SUSPEND 45
-#define GPIO_E800_ANGELX_IRQ 8
diff --git a/arch/arm/mach-pxa/include/mach/irqs.h b/arch/arm/mach-pxa/include/mach/irqs.h
deleted file mode 100644
index 22bf536a462d..000000000000
--- a/arch/arm/mach-pxa/include/mach/irqs.h
+++ /dev/null
@@ -1,109 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-/*
- * arch/arm/mach-pxa/include/mach/irqs.h
- *
- * Author: Nicolas Pitre
- * Created: Jun 15, 2001
- * Copyright: MontaVista Software Inc.
- */
-#ifndef __ASM_MACH_IRQS_H
-#define __ASM_MACH_IRQS_H
-
-#include <asm/irq.h>
-
-#define PXA_ISA_IRQ(x) (x)
-#define PXA_IRQ(x) (NR_IRQS_LEGACY + (x))
-
-#define IRQ_SSP3 PXA_IRQ(0) /* SSP3 service request */
-#define IRQ_MSL PXA_IRQ(1) /* MSL Interface interrupt */
-#define IRQ_USBH2 PXA_IRQ(2) /* USB Host interrupt 1 (OHCI,PXA27x) */
-#define IRQ_USBH1 PXA_IRQ(3) /* USB Host interrupt 2 (non-OHCI,PXA27x) */
-#define IRQ_KEYPAD PXA_IRQ(4) /* Key pad controller */
-#define IRQ_MEMSTK PXA_IRQ(5) /* Memory Stick interrupt (PXA27x) */
-#define IRQ_ACIPC0 PXA_IRQ(5) /* AP-CP Communication (PXA930) */
-#define IRQ_PWRI2C PXA_IRQ(6) /* Power I2C interrupt */
-#define IRQ_HWUART PXA_IRQ(7) /* HWUART Transmit/Receive/Error (PXA26x) */
-#define IRQ_OST_4_11 PXA_IRQ(7) /* OS timer 4-11 matches (PXA27x) */
-#define IRQ_GPIO0 PXA_IRQ(8) /* GPIO0 Edge Detect */
-#define IRQ_GPIO1 PXA_IRQ(9) /* GPIO1 Edge Detect */
-#define IRQ_GPIO_2_x PXA_IRQ(10) /* GPIO[2-x] Edge Detect */
-#define IRQ_USB PXA_IRQ(11) /* USB Service */
-#define IRQ_PMU PXA_IRQ(12) /* Performance Monitoring Unit */
-#define IRQ_I2S PXA_IRQ(13) /* I2S Interrupt (PXA27x) */
-#define IRQ_SSP4 PXA_IRQ(13) /* SSP4 service request (PXA3xx) */
-#define IRQ_AC97 PXA_IRQ(14) /* AC97 Interrupt */
-#define IRQ_ASSP PXA_IRQ(15) /* Audio SSP Service Request (PXA25x) */
-#define IRQ_USIM PXA_IRQ(15) /* Smart Card interface interrupt (PXA27x) */
-#define IRQ_NSSP PXA_IRQ(16) /* Network SSP Service Request (PXA25x) */
-#define IRQ_SSP2 PXA_IRQ(16) /* SSP2 interrupt (PXA27x) */
-#define IRQ_LCD PXA_IRQ(17) /* LCD Controller Service Request */
-#define IRQ_I2C PXA_IRQ(18) /* I2C Service Request */
-#define IRQ_ICP PXA_IRQ(19) /* ICP Transmit/Receive/Error */
-#define IRQ_ACIPC2 PXA_IRQ(19) /* AP-CP Communication (PXA930) */
-#define IRQ_STUART PXA_IRQ(20) /* STUART Transmit/Receive/Error */
-#define IRQ_BTUART PXA_IRQ(21) /* BTUART Transmit/Receive/Error */
-#define IRQ_FFUART PXA_IRQ(22) /* FFUART Transmit/Receive/Error*/
-#define IRQ_MMC PXA_IRQ(23) /* MMC Status/Error Detection */
-#define IRQ_SSP PXA_IRQ(24) /* SSP Service Request */
-#define IRQ_DMA PXA_IRQ(25) /* DMA Channel Service Request */
-#define IRQ_OST0 PXA_IRQ(26) /* OS Timer match 0 */
-#define IRQ_OST1 PXA_IRQ(27) /* OS Timer match 1 */
-#define IRQ_OST2 PXA_IRQ(28) /* OS Timer match 2 */
-#define IRQ_OST3 PXA_IRQ(29) /* OS Timer match 3 */
-#define IRQ_RTC1Hz PXA_IRQ(30) /* RTC HZ Clock Tick */
-#define IRQ_RTCAlrm PXA_IRQ(31) /* RTC Alarm */
-
-#define IRQ_TPM PXA_IRQ(32) /* TPM interrupt */
-#define IRQ_CAMERA PXA_IRQ(33) /* Camera Interface */
-#define IRQ_CIR PXA_IRQ(34) /* Consumer IR */
-#define IRQ_COMM_WDT PXA_IRQ(35) /* Comm WDT interrupt */
-#define IRQ_TSI PXA_IRQ(36) /* Touch Screen Interface (PXA320) */
-#define IRQ_ENHROT PXA_IRQ(37) /* Enhanced Rotary (PXA930) */
-#define IRQ_USIM2 PXA_IRQ(38) /* USIM2 Controller */
-#define IRQ_GCU PXA_IRQ(39) /* Graphics Controller (PXA3xx) */
-#define IRQ_ACIPC1 PXA_IRQ(40) /* AP-CP Communication (PXA930) */
-#define IRQ_MMC2 PXA_IRQ(41) /* MMC2 Controller */
-#define IRQ_TRKBALL PXA_IRQ(43) /* Track Ball (PXA930) */
-#define IRQ_1WIRE PXA_IRQ(44) /* 1-Wire Controller */
-#define IRQ_NAND PXA_IRQ(45) /* NAND Controller */
-#define IRQ_USB2 PXA_IRQ(46) /* USB 2.0 Device Controller */
-#define IRQ_WAKEUP0 PXA_IRQ(49) /* EXT_WAKEUP0 */
-#define IRQ_WAKEUP1 PXA_IRQ(50) /* EXT_WAKEUP1 */
-#define IRQ_DMEMC PXA_IRQ(51) /* Dynamic Memory Controller */
-#define IRQ_MMC3 PXA_IRQ(55) /* MMC3 Controller (PXA310) */
-
-#define IRQ_U2O PXA_IRQ(64) /* USB OTG 2.0 Controller (PXA935) */
-#define IRQ_U2H PXA_IRQ(65) /* USB Host 2.0 Controller (PXA935) */
-#define IRQ_PXA935_MMC0 PXA_IRQ(72) /* MMC0 Controller (PXA935) */
-#define IRQ_PXA935_MMC1 PXA_IRQ(73) /* MMC1 Controller (PXA935) */
-#define IRQ_PXA935_MMC2 PXA_IRQ(74) /* MMC2 Controller (PXA935) */
-#define IRQ_U2P PXA_IRQ(93) /* USB PHY D+/D- Lines (PXA935) */
-
-#define PXA_GPIO_IRQ_BASE PXA_IRQ(96)
-#define PXA_NR_BUILTIN_GPIO (192)
-#define PXA_GPIO_TO_IRQ(x) (PXA_GPIO_IRQ_BASE + (x))
-
-/*
- * The following interrupts are for board specific purposes. Since
- * the kernel can only run on one machine at a time, we can re-use
- * these.
- * By default, no board IRQ is reserved. It should be finished in
- * custom board since sparse IRQ is already enabled.
- */
-#define IRQ_BOARD_START (PXA_GPIO_IRQ_BASE + PXA_NR_BUILTIN_GPIO)
-
-#define PXA_NR_IRQS (IRQ_BOARD_START)
-
-#ifndef __ASSEMBLY__
-struct irq_data;
-struct pt_regs;
-
-void pxa_mask_irq(struct irq_data *);
-void pxa_unmask_irq(struct irq_data *);
-void icip_handle_irq(struct pt_regs *);
-void ichp_handle_irq(struct pt_regs *);
-
-void pxa_init_irq(int irq_nr, int (*set_wake)(struct irq_data *, unsigned int));
-#endif
-
-#endif /* __ASM_MACH_IRQS_H */
diff --git a/arch/arm/mach-pxa/include/mach/magician.h b/arch/arm/mach-pxa/include/mach/magician.h
deleted file mode 100644
index 7d3af561af6f..000000000000
--- a/arch/arm/mach-pxa/include/mach/magician.h
+++ /dev/null
@@ -1,125 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-/*
- * GPIO and IRQ definitions for HTC Magician PDA phones
- *
- * Copyright (c) 2007 Philipp Zabel
- */
-
-#ifndef _MAGICIAN_H_
-#define _MAGICIAN_H_
-
-#include <linux/gpio.h>
-#include <mach/irqs.h>
-
-/*
- * PXA GPIOs
- */
-
-#define GPIO0_MAGICIAN_KEY_POWER 0
-#define GPIO9_MAGICIAN_UNKNOWN 9
-#define GPIO10_MAGICIAN_GSM_IRQ 10
-#define GPIO11_MAGICIAN_GSM_OUT1 11
-#define GPIO13_MAGICIAN_CPLD_IRQ 13
-#define GPIO14_MAGICIAN_TSC2046_CS 14
-#define GPIO18_MAGICIAN_UNKNOWN 18
-#define GPIO22_MAGICIAN_VIBRA_EN 22
-#define GPIO26_MAGICIAN_GSM_POWER 26
-#define GPIO27_MAGICIAN_USBC_PUEN 27
-#define GPIO30_MAGICIAN_BQ24022_nCHARGE_EN 30
-#define GPIO37_MAGICIAN_KEY_HANGUP 37
-#define GPIO38_MAGICIAN_KEY_CONTACTS 38
-#define GPIO40_MAGICIAN_GSM_OUT2 40
-#define GPIO48_MAGICIAN_UNKNOWN 48
-#define GPIO56_MAGICIAN_UNKNOWN 56
-#define GPIO57_MAGICIAN_CAM_RESET 57
-#define GPIO75_MAGICIAN_SAMSUNG_POWER 75
-#define GPIO83_MAGICIAN_nIR_EN 83
-#define GPIO86_MAGICIAN_GSM_RESET 86
-#define GPIO87_MAGICIAN_GSM_SELECT 87
-#define GPIO90_MAGICIAN_KEY_CALENDAR 90
-#define GPIO91_MAGICIAN_KEY_CAMERA 91
-#define GPIO93_MAGICIAN_KEY_UP 93
-#define GPIO94_MAGICIAN_KEY_DOWN 94
-#define GPIO95_MAGICIAN_KEY_LEFT 95
-#define GPIO96_MAGICIAN_KEY_RIGHT 96
-#define GPIO97_MAGICIAN_KEY_ENTER 97
-#define GPIO98_MAGICIAN_KEY_RECORD 98
-#define GPIO99_MAGICIAN_HEADPHONE_IN 99
-#define GPIO100_MAGICIAN_KEY_VOL_UP 100
-#define GPIO101_MAGICIAN_KEY_VOL_DOWN 101
-#define GPIO102_MAGICIAN_KEY_PHONE 102
-#define GPIO103_MAGICIAN_LED_KP 103
-#define GPIO104_MAGICIAN_LCD_VOFF_EN 104
-#define GPIO105_MAGICIAN_LCD_VON_EN 105
-#define GPIO106_MAGICIAN_LCD_DCDC_NRESET 106
-#define GPIO107_MAGICIAN_DS1WM_IRQ 107
-#define GPIO108_MAGICIAN_GSM_READY 108
-#define GPIO114_MAGICIAN_UNKNOWN 114
-#define GPIO115_MAGICIAN_nPEN_IRQ 115
-#define GPIO116_MAGICIAN_nCAM_EN 116
-#define GPIO119_MAGICIAN_UNKNOWN 119
-#define GPIO120_MAGICIAN_UNKNOWN 120
-
-/*
- * CPLD IRQs
- */
-
-#define IRQ_MAGICIAN_SD (IRQ_BOARD_START + 0)
-#define IRQ_MAGICIAN_EP (IRQ_BOARD_START + 1)
-#define IRQ_MAGICIAN_BT (IRQ_BOARD_START + 2)
-#define IRQ_MAGICIAN_VBUS (IRQ_BOARD_START + 3)
-
-#define MAGICIAN_NR_IRQS (IRQ_BOARD_START + 8)
-
-/*
- * CPLD EGPIOs
- */
-
-#define MAGICIAN_EGPIO_BASE PXA_NR_BUILTIN_GPIO
-#define MAGICIAN_EGPIO(reg,bit) \
- (MAGICIAN_EGPIO_BASE + 8*reg + bit)
-
-/* output */
-
-#define EGPIO_MAGICIAN_TOPPOLY_POWER MAGICIAN_EGPIO(0, 2)
-#define EGPIO_MAGICIAN_LED_POWER MAGICIAN_EGPIO(0, 5)
-#define EGPIO_MAGICIAN_GSM_RESET MAGICIAN_EGPIO(0, 6)
-#define EGPIO_MAGICIAN_LCD_POWER MAGICIAN_EGPIO(0, 7)
-#define EGPIO_MAGICIAN_SPK_POWER MAGICIAN_EGPIO(1, 0)
-#define EGPIO_MAGICIAN_EP_POWER MAGICIAN_EGPIO(1, 1)
-#define EGPIO_MAGICIAN_IN_SEL0 MAGICIAN_EGPIO(1, 2)
-#define EGPIO_MAGICIAN_IN_SEL1 MAGICIAN_EGPIO(1, 3)
-#define EGPIO_MAGICIAN_MIC_POWER MAGICIAN_EGPIO(1, 4)
-#define EGPIO_MAGICIAN_CODEC_RESET MAGICIAN_EGPIO(1, 5)
-#define EGPIO_MAGICIAN_CODEC_POWER MAGICIAN_EGPIO(1, 6)
-#define EGPIO_MAGICIAN_BL_POWER MAGICIAN_EGPIO(1, 7)
-#define EGPIO_MAGICIAN_SD_POWER MAGICIAN_EGPIO(2, 0)
-#define EGPIO_MAGICIAN_CARKIT_MIC MAGICIAN_EGPIO(2, 1)
-#define EGPIO_MAGICIAN_IR_RX_SHUTDOWN MAGICIAN_EGPIO(2, 2)
-#define EGPIO_MAGICIAN_FLASH_VPP MAGICIAN_EGPIO(2, 3)
-#define EGPIO_MAGICIAN_BL_POWER2 MAGICIAN_EGPIO(2, 4)
-#define EGPIO_MAGICIAN_BQ24022_ISET2 MAGICIAN_EGPIO(2, 5)
-#define EGPIO_MAGICIAN_NICD_CHARGE MAGICIAN_EGPIO(2, 6)
-#define EGPIO_MAGICIAN_GSM_POWER MAGICIAN_EGPIO(2, 7)
-
-/* input */
-
-/* USB or AC charger type */
-#define EGPIO_MAGICIAN_CABLE_TYPE MAGICIAN_EGPIO(4, 0)
-/*
- * Vbus is detected
- * FIXME behaves like (6,3), may differ for host/device
- */
-#define EGPIO_MAGICIAN_CABLE_VBUS MAGICIAN_EGPIO(4, 1)
-
-#define EGPIO_MAGICIAN_BOARD_ID0 MAGICIAN_EGPIO(5, 0)
-#define EGPIO_MAGICIAN_BOARD_ID1 MAGICIAN_EGPIO(5, 1)
-#define EGPIO_MAGICIAN_BOARD_ID2 MAGICIAN_EGPIO(5, 2)
-#define EGPIO_MAGICIAN_LCD_SELECT MAGICIAN_EGPIO(5, 3)
-#define EGPIO_MAGICIAN_nSD_READONLY MAGICIAN_EGPIO(5, 4)
-
-#define EGPIO_MAGICIAN_EP_INSERT MAGICIAN_EGPIO(6, 1)
-/* FIXME behaves like (4,1), may differ for host/device */
-#define EGPIO_MAGICIAN_CABLE_INSERTED MAGICIAN_EGPIO(6, 3)
-
-#endif /* _MAGICIAN_H_ */
diff --git a/arch/arm/mach-pxa/include/mach/mfp.h b/arch/arm/mach-pxa/include/mach/mfp.h
deleted file mode 100644
index 7e0879bd4102..000000000000
--- a/arch/arm/mach-pxa/include/mach/mfp.h
+++ /dev/null
@@ -1,18 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-/*
- * arch/arm/mach-pxa/include/mach/mfp.h
- *
- * Multi-Function Pin Definitions
- *
- * Copyright (C) 2007 Marvell International Ltd.
- *
- * 2007-8-21: eric miao <eric.miao@marvell.com>
- * initial version
- */
-
-#ifndef __ASM_ARCH_MFP_H
-#define __ASM_ARCH_MFP_H
-
-#include <linux/soc/pxa/mfp.h>
-
-#endif /* __ASM_ARCH_MFP_H */
diff --git a/arch/arm/mach-pxa/include/mach/pxa-regs.h b/arch/arm/mach-pxa/include/mach/pxa-regs.h
deleted file mode 100644
index ba5120c06b8a..000000000000
--- a/arch/arm/mach-pxa/include/mach/pxa-regs.h
+++ /dev/null
@@ -1,52 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Author: Nicolas Pitre
- * Created: Jun 15, 2001
- * Copyright: MontaVista Software Inc.
- */
-#ifndef __ASM_MACH_PXA_REGS_H
-#define __ASM_MACH_PXA_REGS_H
-
-/*
- * Workarounds for at least 2 errata so far require this.
- * The mapping is set in mach-pxa/generic.c.
- */
-#define UNCACHED_PHYS_0 0xfe000000
-#define UNCACHED_PHYS_0_SIZE 0x00100000
-
-/*
- * Intel PXA2xx internal register mapping:
- *
- * 0x40000000 - 0x41ffffff <--> 0xf2000000 - 0xf3ffffff
- * 0x44000000 - 0x45ffffff <--> 0xf4000000 - 0xf5ffffff
- * 0x48000000 - 0x49ffffff <--> 0xf6000000 - 0xf7ffffff
- * 0x4c000000 - 0x4dffffff <--> 0xf8000000 - 0xf9ffffff
- * 0x50000000 - 0x51ffffff <--> 0xfa000000 - 0xfbffffff
- * 0x54000000 - 0x55ffffff <--> 0xfc000000 - 0xfdffffff
- * 0x58000000 - 0x59ffffff <--> 0xfe000000 - 0xffffffff
- *
- * Note that not all PXA2xx chips implement all those addresses, and the
- * kernel only maps the minimum needed range of this mapping.
- */
-#define io_v2p(x) (0x3c000000 + ((x) & 0x01ffffff) + (((x) & 0x0e000000) << 1))
-#define io_p2v(x) IOMEM(0xf2000000 + ((x) & 0x01ffffff) + (((x) & 0x1c000000) >> 1))
-
-#ifndef __ASSEMBLY__
-# define __REG(x) (*((volatile u32 __iomem *)io_p2v(x)))
-
-/* With indexed regs we don't want to feed the index through io_p2v()
- especially if it is a variable, otherwise horrible code will result. */
-# define __REG2(x,y) \
- (*(volatile u32 __iomem*)((u32)&__REG(x) + (y)))
-
-# define __PREG(x) (io_v2p((u32)&(x)))
-
-#else
-
-# define __REG(x) io_p2v(x)
-# define __PREG(x) io_v2p(x)
-
-#endif
-
-
-#endif
diff --git a/arch/arm/mach-pxa/include/mach/pxa2xx-regs.h b/arch/arm/mach-pxa/include/mach/pxa2xx-regs.h
deleted file mode 100644
index 0b7eaf6b5813..000000000000
--- a/arch/arm/mach-pxa/include/mach/pxa2xx-regs.h
+++ /dev/null
@@ -1,149 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-/*
- * arch/arm/mach-pxa/include/mach/pxa2xx-regs.h
- *
- * Taken from pxa-regs.h by Russell King
- *
- * Author: Nicolas Pitre
- * Copyright: MontaVista Software Inc.
- */
-
-#ifndef __PXA2XX_REGS_H
-#define __PXA2XX_REGS_H
-
-#include "pxa-regs.h"
-
-/*
- * Power Manager
- */
-
-#define PMCR __REG(0x40F00000) /* Power Manager Control Register */
-#define PSSR __REG(0x40F00004) /* Power Manager Sleep Status Register */
-#define PSPR __REG(0x40F00008) /* Power Manager Scratch Pad Register */
-#define PWER __REG(0x40F0000C) /* Power Manager Wake-up Enable Register */
-#define PRER __REG(0x40F00010) /* Power Manager GPIO Rising-Edge Detect Enable Register */
-#define PFER __REG(0x40F00014) /* Power Manager GPIO Falling-Edge Detect Enable Register */
-#define PEDR __REG(0x40F00018) /* Power Manager GPIO Edge Detect Status Register */
-#define PCFR __REG(0x40F0001C) /* Power Manager General Configuration Register */
-#define PGSR0 __REG(0x40F00020) /* Power Manager GPIO Sleep State Register for GP[31-0] */
-#define PGSR1 __REG(0x40F00024) /* Power Manager GPIO Sleep State Register for GP[63-32] */
-#define PGSR2 __REG(0x40F00028) /* Power Manager GPIO Sleep State Register for GP[84-64] */
-#define PGSR3 __REG(0x40F0002C) /* Power Manager GPIO Sleep State Register for GP[118-96] */
-#define RCSR __REG(0x40F00030) /* Reset Controller Status Register */
-
-#define PSLR __REG(0x40F00034) /* Power Manager Sleep Config Register */
-#define PSTR __REG(0x40F00038) /* Power Manager Standby Config Register */
-#define PSNR __REG(0x40F0003C) /* Power Manager Sense Config Register */
-#define PVCR __REG(0x40F00040) /* Power Manager VoltageControl Register */
-#define PKWR __REG(0x40F00050) /* Power Manager KB Wake-up Enable Reg */
-#define PKSR __REG(0x40F00054) /* Power Manager KB Level-Detect Register */
-#define PCMD(x) __REG2(0x40F00080, (x)<<2)
-#define PCMD0 __REG(0x40F00080 + 0 * 4)
-#define PCMD1 __REG(0x40F00080 + 1 * 4)
-#define PCMD2 __REG(0x40F00080 + 2 * 4)
-#define PCMD3 __REG(0x40F00080 + 3 * 4)
-#define PCMD4 __REG(0x40F00080 + 4 * 4)
-#define PCMD5 __REG(0x40F00080 + 5 * 4)
-#define PCMD6 __REG(0x40F00080 + 6 * 4)
-#define PCMD7 __REG(0x40F00080 + 7 * 4)
-#define PCMD8 __REG(0x40F00080 + 8 * 4)
-#define PCMD9 __REG(0x40F00080 + 9 * 4)
-#define PCMD10 __REG(0x40F00080 + 10 * 4)
-#define PCMD11 __REG(0x40F00080 + 11 * 4)
-#define PCMD12 __REG(0x40F00080 + 12 * 4)
-#define PCMD13 __REG(0x40F00080 + 13 * 4)
-#define PCMD14 __REG(0x40F00080 + 14 * 4)
-#define PCMD15 __REG(0x40F00080 + 15 * 4)
-#define PCMD16 __REG(0x40F00080 + 16 * 4)
-#define PCMD17 __REG(0x40F00080 + 17 * 4)
-#define PCMD18 __REG(0x40F00080 + 18 * 4)
-#define PCMD19 __REG(0x40F00080 + 19 * 4)
-#define PCMD20 __REG(0x40F00080 + 20 * 4)
-#define PCMD21 __REG(0x40F00080 + 21 * 4)
-#define PCMD22 __REG(0x40F00080 + 22 * 4)
-#define PCMD23 __REG(0x40F00080 + 23 * 4)
-#define PCMD24 __REG(0x40F00080 + 24 * 4)
-#define PCMD25 __REG(0x40F00080 + 25 * 4)
-#define PCMD26 __REG(0x40F00080 + 26 * 4)
-#define PCMD27 __REG(0x40F00080 + 27 * 4)
-#define PCMD28 __REG(0x40F00080 + 28 * 4)
-#define PCMD29 __REG(0x40F00080 + 29 * 4)
-#define PCMD30 __REG(0x40F00080 + 30 * 4)
-#define PCMD31 __REG(0x40F00080 + 31 * 4)
-
-#define PCMD_MBC (1<<12)
-#define PCMD_DCE (1<<11)
-#define PCMD_LC (1<<10)
-/* FIXME: PCMD_SQC need be checked. */
-#define PCMD_SQC (3<<8) /* currently only bit 8 is changeable,
- bit 9 should be 0 all day. */
-#define PVCR_VCSA (0x1<<14)
-#define PVCR_CommandDelay (0xf80)
-#define PCFR_PI2C_EN (0x1 << 6)
-
-#define PSSR_OTGPH (1 << 6) /* OTG Peripheral control Hold */
-#define PSSR_RDH (1 << 5) /* Read Disable Hold */
-#define PSSR_PH (1 << 4) /* Peripheral Control Hold */
-#define PSSR_STS (1 << 3) /* Standby Mode Status */
-#define PSSR_VFS (1 << 2) /* VDD Fault Status */
-#define PSSR_BFS (1 << 1) /* Battery Fault Status */
-#define PSSR_SSS (1 << 0) /* Software Sleep Status */
-
-#define PSLR_SL_ROD (1 << 20) /* Sleep-Mode/Depp-Sleep Mode nRESET_OUT Disable */
-
-#define PCFR_RO (1 << 15) /* RDH Override */
-#define PCFR_PO (1 << 14) /* PH Override */
-#define PCFR_GPROD (1 << 12) /* GPIO nRESET_OUT Disable */
-#define PCFR_L1_EN (1 << 11) /* Sleep Mode L1 converter Enable */
-#define PCFR_FVC (1 << 10) /* Frequency/Voltage Change */
-#define PCFR_DC_EN (1 << 7) /* Sleep/deep-sleep DC-DC Converter Enable */
-#define PCFR_PI2CEN (1 << 6) /* Enable PI2C controller */
-#define PCFR_GPR_EN (1 << 4) /* nRESET_GPIO Pin Enable */
-#define PCFR_DS (1 << 3) /* Deep Sleep Mode */
-#define PCFR_FS (1 << 2) /* Float Static Chip Selects */
-#define PCFR_FP (1 << 1) /* Float PCMCIA controls */
-#define PCFR_OPDE (1 << 0) /* 3.6864 MHz oscillator power-down enable */
-
-#define RCSR_GPR (1 << 3) /* GPIO Reset */
-#define RCSR_SMR (1 << 2) /* Sleep Mode */
-#define RCSR_WDR (1 << 1) /* Watchdog Reset */
-#define RCSR_HWR (1 << 0) /* Hardware Reset */
-
-#define PWER_GPIO(Nb) (1 << Nb) /* GPIO [0..15] wake-up enable */
-#define PWER_GPIO0 PWER_GPIO (0) /* GPIO [0] wake-up enable */
-#define PWER_GPIO1 PWER_GPIO (1) /* GPIO [1] wake-up enable */
-#define PWER_GPIO2 PWER_GPIO (2) /* GPIO [2] wake-up enable */
-#define PWER_GPIO3 PWER_GPIO (3) /* GPIO [3] wake-up enable */
-#define PWER_GPIO4 PWER_GPIO (4) /* GPIO [4] wake-up enable */
-#define PWER_GPIO5 PWER_GPIO (5) /* GPIO [5] wake-up enable */
-#define PWER_GPIO6 PWER_GPIO (6) /* GPIO [6] wake-up enable */
-#define PWER_GPIO7 PWER_GPIO (7) /* GPIO [7] wake-up enable */
-#define PWER_GPIO8 PWER_GPIO (8) /* GPIO [8] wake-up enable */
-#define PWER_GPIO9 PWER_GPIO (9) /* GPIO [9] wake-up enable */
-#define PWER_GPIO10 PWER_GPIO (10) /* GPIO [10] wake-up enable */
-#define PWER_GPIO11 PWER_GPIO (11) /* GPIO [11] wake-up enable */
-#define PWER_GPIO12 PWER_GPIO (12) /* GPIO [12] wake-up enable */
-#define PWER_GPIO13 PWER_GPIO (13) /* GPIO [13] wake-up enable */
-#define PWER_GPIO14 PWER_GPIO (14) /* GPIO [14] wake-up enable */
-#define PWER_GPIO15 PWER_GPIO (15) /* GPIO [15] wake-up enable */
-#define PWER_RTC 0x80000000 /* RTC alarm wake-up enable */
-
-/*
- * PXA2xx specific Core clock definitions
- */
-#define CCCR io_p2v(0x41300000) /* Core Clock Configuration Register */
-#define CCSR io_p2v(0x4130000C) /* Core Clock Status Register */
-#define CKEN io_p2v(0x41300004) /* Clock Enable Register */
-#define OSCC io_p2v(0x41300008) /* Oscillator Configuration Register */
-
-#define OSCC_OON (1 << 1) /* 32.768kHz OON (write-once only bit) */
-#define OSCC_OOK (1 << 0) /* 32.768kHz OOK (read-only bit) */
-
-/* PWRMODE register M field values */
-
-#define PWRMODE_IDLE 0x1
-#define PWRMODE_STANDBY 0x2
-#define PWRMODE_SLEEP 0x3
-#define PWRMODE_DEEPSLEEP 0x7
-
-#endif
diff --git a/arch/arm/mach-pxa/include/mach/pxa3xx-regs.h b/arch/arm/mach-pxa/include/mach/pxa3xx-regs.h
deleted file mode 100644
index 4b11cf81a9e6..000000000000
--- a/arch/arm/mach-pxa/include/mach/pxa3xx-regs.h
+++ /dev/null
@@ -1,134 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-/*
- * arch/arm/mach-pxa/include/mach/pxa3xx-regs.h
- *
- * PXA3xx specific register definitions
- *
- * Copyright (C) 2007 Marvell International Ltd.
- */
-
-#ifndef __ASM_ARCH_PXA3XX_REGS_H
-#define __ASM_ARCH_PXA3XX_REGS_H
-
-#include "pxa-regs.h"
-
-/*
- * Oscillator Configuration Register (OSCC)
- */
-#define OSCC io_p2v(0x41350000) /* Oscillator Configuration Register */
-
-#define OSCC_PEN (1 << 11) /* 13MHz POUT */
-
-
-/*
- * Service Power Management Unit (MPMU)
- */
-#define PMCR __REG(0x40F50000) /* Power Manager Control Register */
-#define PSR __REG(0x40F50004) /* Power Manager S2 Status Register */
-#define PSPR __REG(0x40F50008) /* Power Manager Scratch Pad Register */
-#define PCFR __REG(0x40F5000C) /* Power Manager General Configuration Register */
-#define PWER __REG(0x40F50010) /* Power Manager Wake-up Enable Register */
-#define PWSR __REG(0x40F50014) /* Power Manager Wake-up Status Register */
-#define PECR __REG(0x40F50018) /* Power Manager EXT_WAKEUP[1:0] Control Register */
-#define DCDCSR __REG(0x40F50080) /* DC-DC Controller Status Register */
-#define PVCR __REG(0x40F50100) /* Power Manager Voltage Change Control Register */
-#define PCMD(x) __REG(0x40F50110 + ((x) << 2))
-
-/*
- * Slave Power Management Unit
- */
-#define ASCR __REG(0x40f40000) /* Application Subsystem Power Status/Configuration */
-#define ARSR __REG(0x40f40004) /* Application Subsystem Reset Status */
-#define AD3ER __REG(0x40f40008) /* Application Subsystem Wake-Up from D3 Enable */
-#define AD3SR __REG(0x40f4000c) /* Application Subsystem Wake-Up from D3 Status */
-#define AD2D0ER __REG(0x40f40010) /* Application Subsystem Wake-Up from D2 to D0 Enable */
-#define AD2D0SR __REG(0x40f40014) /* Application Subsystem Wake-Up from D2 to D0 Status */
-#define AD2D1ER __REG(0x40f40018) /* Application Subsystem Wake-Up from D2 to D1 Enable */
-#define AD2D1SR __REG(0x40f4001c) /* Application Subsystem Wake-Up from D2 to D1 Status */
-#define AD1D0ER __REG(0x40f40020) /* Application Subsystem Wake-Up from D1 to D0 Enable */
-#define AD1D0SR __REG(0x40f40024) /* Application Subsystem Wake-Up from D1 to D0 Status */
-#define AGENP __REG(0x40f4002c) /* Application Subsystem General Purpose */
-#define AD3R __REG(0x40f40030) /* Application Subsystem D3 Configuration */
-#define AD2R __REG(0x40f40034) /* Application Subsystem D2 Configuration */
-#define AD1R __REG(0x40f40038) /* Application Subsystem D1 Configuration */
-
-/*
- * Application Subsystem Configuration bits.
- */
-#define ASCR_RDH (1 << 31)
-#define ASCR_D1S (1 << 2)
-#define ASCR_D2S (1 << 1)
-#define ASCR_D3S (1 << 0)
-
-/*
- * Application Reset Status bits.
- */
-#define ARSR_GPR (1 << 3)
-#define ARSR_LPMR (1 << 2)
-#define ARSR_WDT (1 << 1)
-#define ARSR_HWR (1 << 0)
-
-/*
- * Application Subsystem Wake-Up bits.
- */
-#define ADXER_WRTC (1 << 31) /* RTC */
-#define ADXER_WOST (1 << 30) /* OS Timer */
-#define ADXER_WTSI (1 << 29) /* Touchscreen */
-#define ADXER_WUSBH (1 << 28) /* USB host */
-#define ADXER_WUSB2 (1 << 26) /* USB client 2.0 */
-#define ADXER_WMSL0 (1 << 24) /* MSL port 0*/
-#define ADXER_WDMUX3 (1 << 23) /* USB EDMUX3 */
-#define ADXER_WDMUX2 (1 << 22) /* USB EDMUX2 */
-#define ADXER_WKP (1 << 21) /* Keypad */
-#define ADXER_WUSIM1 (1 << 20) /* USIM Port 1 */
-#define ADXER_WUSIM0 (1 << 19) /* USIM Port 0 */
-#define ADXER_WOTG (1 << 16) /* USBOTG input */
-#define ADXER_MFP_WFLASH (1 << 15) /* MFP: Data flash busy */
-#define ADXER_MFP_GEN12 (1 << 14) /* MFP: MMC3/GPIO/OST inputs */
-#define ADXER_MFP_WMMC2 (1 << 13) /* MFP: MMC2 */
-#define ADXER_MFP_WMMC1 (1 << 12) /* MFP: MMC1 */
-#define ADXER_MFP_WI2C (1 << 11) /* MFP: I2C */
-#define ADXER_MFP_WSSP4 (1 << 10) /* MFP: SSP4 */
-#define ADXER_MFP_WSSP3 (1 << 9) /* MFP: SSP3 */
-#define ADXER_MFP_WMAXTRIX (1 << 8) /* MFP: matrix keypad */
-#define ADXER_MFP_WUART3 (1 << 7) /* MFP: UART3 */
-#define ADXER_MFP_WUART2 (1 << 6) /* MFP: UART2 */
-#define ADXER_MFP_WUART1 (1 << 5) /* MFP: UART1 */
-#define ADXER_MFP_WSSP2 (1 << 4) /* MFP: SSP2 */
-#define ADXER_MFP_WSSP1 (1 << 3) /* MFP: SSP1 */
-#define ADXER_MFP_WAC97 (1 << 2) /* MFP: AC97 */
-#define ADXER_WEXTWAKE1 (1 << 1) /* External Wake 1 */
-#define ADXER_WEXTWAKE0 (1 << 0) /* External Wake 0 */
-
-/*
- * AD3R/AD2R/AD1R bits. R2-R5 are only defined for PXA320.
- */
-#define ADXR_L2 (1 << 8)
-#define ADXR_R5 (1 << 5)
-#define ADXR_R4 (1 << 4)
-#define ADXR_R3 (1 << 3)
-#define ADXR_R2 (1 << 2)
-#define ADXR_R1 (1 << 1)
-#define ADXR_R0 (1 << 0)
-
-/*
- * Values for PWRMODE CP15 register
- */
-#define PXA3xx_PM_S3D4C4 0x07 /* aka deep sleep */
-#define PXA3xx_PM_S2D3C4 0x06 /* aka sleep */
-#define PXA3xx_PM_S0D2C2 0x03 /* aka standby */
-#define PXA3xx_PM_S0D1C2 0x02 /* aka LCD refresh */
-#define PXA3xx_PM_S0D0C1 0x01
-
-/*
- * Application Subsystem Clock
- */
-#define ACCR __REG(0x41340000) /* Application Subsystem Clock Configuration Register */
-#define ACSR __REG(0x41340004) /* Application Subsystem Clock Status Register */
-#define AICSR __REG(0x41340008) /* Application Subsystem Interrupt Control/Status Register */
-#define CKENA __REG(0x4134000C) /* A Clock Enable Register */
-#define CKENB __REG(0x41340010) /* B Clock Enable Register */
-#define CKENC __REG(0x41340024) /* C Clock Enable Register */
-#define AC97_DIV __REG(0x41340014) /* AC97 clock divisor value register */
-
-#endif /* __ASM_ARCH_PXA3XX_REGS_H */
diff --git a/arch/arm/mach-pxa/include/mach/regs-ost.h b/arch/arm/mach-pxa/include/mach/regs-ost.h
deleted file mode 100644
index c8001cfc8d6b..000000000000
--- a/arch/arm/mach-pxa/include/mach/regs-ost.h
+++ /dev/null
@@ -1,37 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __ASM_MACH_REGS_OST_H
-#define __ASM_MACH_REGS_OST_H
-
-#include "pxa-regs.h"
-
-/*
- * OS Timer & Match Registers
- */
-#define OST_PHYS 0x40A00000
-#define OST_LEN 0x00000020
-
-#define OSMR0 io_p2v(0x40A00000) /* */
-#define OSMR1 io_p2v(0x40A00004) /* */
-#define OSMR2 io_p2v(0x40A00008) /* */
-#define OSMR3 io_p2v(0x40A0000C) /* */
-#define OSMR4 io_p2v(0x40A00080) /* */
-#define OSCR io_p2v(0x40A00010) /* OS Timer Counter Register */
-#define OSCR4 io_p2v(0x40A00040) /* OS Timer Counter Register */
-#define OMCR4 io_p2v(0x40A000C0) /* */
-#define OSSR io_p2v(0x40A00014) /* OS Timer Status Register */
-#define OWER io_p2v(0x40A00018) /* OS Timer Watchdog Enable Register */
-#define OIER io_p2v(0x40A0001C) /* OS Timer Interrupt Enable Register */
-
-#define OSSR_M3 (1 << 3) /* Match status channel 3 */
-#define OSSR_M2 (1 << 2) /* Match status channel 2 */
-#define OSSR_M1 (1 << 1) /* Match status channel 1 */
-#define OSSR_M0 (1 << 0) /* Match status channel 0 */
-
-#define OWER_WME (1 << 0) /* Watchdog Match Enable */
-
-#define OIER_E3 (1 << 3) /* Interrupt enable channel 3 */
-#define OIER_E2 (1 << 2) /* Interrupt enable channel 2 */
-#define OIER_E1 (1 << 1) /* Interrupt enable channel 1 */
-#define OIER_E0 (1 << 0) /* Interrupt enable channel 0 */
-
-#endif /* __ASM_MACH_REGS_OST_H */
diff --git a/arch/arm/mach-pxa/include/mach/reset.h b/arch/arm/mach-pxa/include/mach/reset.h
deleted file mode 100644
index 963dd190bc13..000000000000
--- a/arch/arm/mach-pxa/include/mach/reset.h
+++ /dev/null
@@ -1,22 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __ASM_ARCH_RESET_H
-#define __ASM_ARCH_RESET_H
-
-#define RESET_STATUS_HARDWARE (1 << 0) /* Hardware Reset */
-#define RESET_STATUS_WATCHDOG (1 << 1) /* Watchdog Reset */
-#define RESET_STATUS_LOWPOWER (1 << 2) /* Low Power/Sleep Exit */
-#define RESET_STATUS_GPIO (1 << 3) /* GPIO Reset */
-#define RESET_STATUS_ALL (0xf)
-
-extern void clear_reset_status(unsigned int mask);
-extern void pxa_register_wdt(unsigned int reset_status);
-
-/**
- * init_gpio_reset() - register GPIO as reset generator
- * @gpio: gpio nr
- * @output: set gpio as output instead of input during normal work
- * @level: output level
- */
-extern int init_gpio_reset(int gpio, int output, int level);
-
-#endif /* __ASM_ARCH_RESET_H */
diff --git a/arch/arm/mach-pxa/include/mach/smemc.h b/arch/arm/mach-pxa/include/mach/smemc.h
deleted file mode 100644
index 9b2453a7ab23..000000000000
--- a/arch/arm/mach-pxa/include/mach/smemc.h
+++ /dev/null
@@ -1,72 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-/*
- * Static memory controller register definitions for PXA CPUs
- *
- * Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
- */
-
-#ifndef __SMEMC_REGS_H
-#define __SMEMC_REGS_H
-
-#define PXA2XX_SMEMC_BASE 0x48000000
-#define PXA3XX_SMEMC_BASE 0x4a000000
-#define SMEMC_VIRT IOMEM(0xf6000000)
-
-#define MDCNFG (SMEMC_VIRT + 0x00) /* SDRAM Configuration Register 0 */
-#define MDREFR (SMEMC_VIRT + 0x04) /* SDRAM Refresh Control Register */
-#define MSC0 (SMEMC_VIRT + 0x08) /* Static Memory Control Register 0 */
-#define MSC1 (SMEMC_VIRT + 0x0C) /* Static Memory Control Register 1 */
-#define MSC2 (SMEMC_VIRT + 0x10) /* Static Memory Control Register 2 */
-#define MECR (SMEMC_VIRT + 0x14) /* Expansion Memory (PCMCIA/Compact Flash) Bus Configuration */
-#define SXLCR (SMEMC_VIRT + 0x18) /* LCR value to be written to SDRAM-Timing Synchronous Flash */
-#define SXCNFG (SMEMC_VIRT + 0x1C) /* Synchronous Static Memory Control Register */
-#define SXMRS (SMEMC_VIRT + 0x24) /* MRS value to be written to Synchronous Flash or SMROM */
-#define MCMEM0 (SMEMC_VIRT + 0x28) /* Card interface Common Memory Space Socket 0 Timing */
-#define MCMEM1 (SMEMC_VIRT + 0x2C) /* Card interface Common Memory Space Socket 1 Timing */
-#define MCATT0 (SMEMC_VIRT + 0x30) /* Card interface Attribute Space Socket 0 Timing Configuration */
-#define MCATT1 (SMEMC_VIRT + 0x34) /* Card interface Attribute Space Socket 1 Timing Configuration */
-#define MCIO0 (SMEMC_VIRT + 0x38) /* Card interface I/O Space Socket 0 Timing Configuration */
-#define MCIO1 (SMEMC_VIRT + 0x3C) /* Card interface I/O Space Socket 1 Timing Configuration */
-#define MDMRS (SMEMC_VIRT + 0x40) /* MRS value to be written to SDRAM */
-#define BOOT_DEF (SMEMC_VIRT + 0x44) /* Read-Only Boot-Time Register. Contains BOOT_SEL and PKG_SEL */
-#define MEMCLKCFG (SMEMC_VIRT + 0x68) /* Clock Configuration */
-#define CSADRCFG0 (SMEMC_VIRT + 0x80) /* Address Configuration Register for CS0 */
-#define CSADRCFG1 (SMEMC_VIRT + 0x84) /* Address Configuration Register for CS1 */
-#define CSADRCFG2 (SMEMC_VIRT + 0x88) /* Address Configuration Register for CS2 */
-#define CSADRCFG3 (SMEMC_VIRT + 0x8C) /* Address Configuration Register for CS3 */
-#define CSMSADRCFG (SMEMC_VIRT + 0xA0) /* Chip Select Configuration Register */
-
-/*
- * More handy macros for PCMCIA
- *
- * Arg is socket number
- */
-#define MCMEM(s) (SMEMC_VIRT + 0x28 + ((s)<<2)) /* Card interface Common Memory Space Socket s Timing */
-#define MCATT(s) (SMEMC_VIRT + 0x30 + ((s)<<2)) /* Card interface Attribute Space Socket s Timing Configuration */
-#define MCIO(s) (SMEMC_VIRT + 0x38 + ((s)<<2)) /* Card interface I/O Space Socket s Timing Configuration */
-
-/* MECR register defines */
-#define MECR_NOS (1 << 0) /* Number Of Sockets: 0 -> 1 sock, 1 -> 2 sock */
-#define MECR_CIT (1 << 1) /* Card Is There: 0 -> no card, 1 -> card inserted */
-
-#define MDCNFG_DE0 (1 << 0) /* SDRAM Bank 0 Enable */
-#define MDCNFG_DE1 (1 << 1) /* SDRAM Bank 1 Enable */
-#define MDCNFG_DE2 (1 << 16) /* SDRAM Bank 2 Enable */
-#define MDCNFG_DE3 (1 << 17) /* SDRAM Bank 3 Enable */
-
-#define MDREFR_K0DB4 (1 << 29) /* SDCLK0 Divide by 4 Control/Status */
-#define MDREFR_K2FREE (1 << 25) /* SDRAM Free-Running Control */
-#define MDREFR_K1FREE (1 << 24) /* SDRAM Free-Running Control */
-#define MDREFR_K0FREE (1 << 23) /* SDRAM Free-Running Control */
-#define MDREFR_SLFRSH (1 << 22) /* SDRAM Self-Refresh Control/Status */
-#define MDREFR_APD (1 << 20) /* SDRAM/SSRAM Auto-Power-Down Enable */
-#define MDREFR_K2DB2 (1 << 19) /* SDCLK2 Divide by 2 Control/Status */
-#define MDREFR_K2RUN (1 << 18) /* SDCLK2 Run Control/Status */
-#define MDREFR_K1DB2 (1 << 17) /* SDCLK1 Divide by 2 Control/Status */
-#define MDREFR_K1RUN (1 << 16) /* SDCLK1 Run Control/Status */
-#define MDREFR_E1PIN (1 << 15) /* SDCKE1 Level Control/Status */
-#define MDREFR_K0DB2 (1 << 14) /* SDCLK0 Divide by 2 Control/Status */
-#define MDREFR_K0RUN (1 << 13) /* SDCLK0 Run Control/Status */
-#define MDREFR_E0PIN (1 << 12) /* SDCKE0 Level Control/Status */
-
-#endif
diff --git a/arch/arm/mach-pxa/include/mach/tosa.h b/arch/arm/mach-pxa/include/mach/tosa.h
deleted file mode 100644
index 3b3efa0a0e22..000000000000
--- a/arch/arm/mach-pxa/include/mach/tosa.h
+++ /dev/null
@@ -1,165 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-/*
- * Hardware specific definitions for Sharp SL-C6000x series of PDAs
- *
- * Copyright (c) 2005 Dirk Opfer
- *
- * Based on Sharp's 2.4 kernel patches
- */
-#ifndef _ASM_ARCH_TOSA_H_
-#define _ASM_ARCH_TOSA_H_ 1
-
-#include "irqs.h" /* PXA_NR_BUILTIN_GPIO */
-
-/* TOSA Chip selects */
-#define TOSA_LCDC_PHYS PXA_CS4_PHYS
-/* Internel Scoop */
-#define TOSA_CF_PHYS (PXA_CS2_PHYS + 0x00800000)
-/* Jacket Scoop */
-#define TOSA_SCOOP_PHYS (PXA_CS5_PHYS + 0x00800000)
-
-#define TOSA_NR_IRQS (IRQ_BOARD_START + TC6393XB_NR_IRQS)
-/*
- * SCOOP2 internal GPIOs
- */
-#define TOSA_SCOOP_GPIO_BASE PXA_NR_BUILTIN_GPIO
-#define TOSA_SCOOP_PXA_VCORE1 SCOOP_GPCR_PA11
-#define TOSA_GPIO_TC6393XB_REST_IN (TOSA_SCOOP_GPIO_BASE + 1)
-#define TOSA_GPIO_IR_POWERDWN (TOSA_SCOOP_GPIO_BASE + 2)
-#define TOSA_GPIO_SD_WP (TOSA_SCOOP_GPIO_BASE + 3)
-#define TOSA_GPIO_PWR_ON (TOSA_SCOOP_GPIO_BASE + 4)
-#define TOSA_SCOOP_AUD_PWR_ON SCOOP_GPCR_PA16
-#define TOSA_GPIO_BT_RESET (TOSA_SCOOP_GPIO_BASE + 6)
-#define TOSA_GPIO_BT_PWR_EN (TOSA_SCOOP_GPIO_BASE + 7)
-#define TOSA_SCOOP_AC_IN_OL SCOOP_GPCR_PA19
-
-/* GPIO Direction 1 : output mode / 0:input mode */
-#define TOSA_SCOOP_IO_DIR (TOSA_SCOOP_PXA_VCORE1 | \
- TOSA_SCOOP_AUD_PWR_ON)
-
-/*
- * SCOOP2 jacket GPIOs
- */
-#define TOSA_SCOOP_JC_GPIO_BASE (PXA_NR_BUILTIN_GPIO + 12)
-#define TOSA_GPIO_BT_LED (TOSA_SCOOP_JC_GPIO_BASE + 0)
-#define TOSA_GPIO_NOTE_LED (TOSA_SCOOP_JC_GPIO_BASE + 1)
-#define TOSA_GPIO_CHRG_ERR_LED (TOSA_SCOOP_JC_GPIO_BASE + 2)
-#define TOSA_GPIO_USB_PULLUP (TOSA_SCOOP_JC_GPIO_BASE + 3)
-#define TOSA_GPIO_TC6393XB_SUSPEND (TOSA_SCOOP_JC_GPIO_BASE + 4)
-#define TOSA_GPIO_TC6393XB_L3V_ON (TOSA_SCOOP_JC_GPIO_BASE + 5)
-#define TOSA_SCOOP_JC_WLAN_DETECT SCOOP_GPCR_PA17
-#define TOSA_GPIO_WLAN_LED (TOSA_SCOOP_JC_GPIO_BASE + 7)
-#define TOSA_SCOOP_JC_CARD_LIMIT_SEL SCOOP_GPCR_PA19
-
-/* GPIO Direction 1 : output mode / 0:input mode */
-#define TOSA_SCOOP_JC_IO_DIR (TOSA_SCOOP_JC_CARD_LIMIT_SEL)
-
-/*
- * PXA GPIOs
- */
-#define TOSA_GPIO_POWERON (0)
-#define TOSA_GPIO_RESET (1)
-#define TOSA_GPIO_AC_IN (2)
-#define TOSA_GPIO_RECORD_BTN (3)
-#define TOSA_GPIO_SYNC (4) /* Cradle SYNC Button */
-#define TOSA_GPIO_USB_IN (5)
-#define TOSA_GPIO_JACKET_DETECT (7)
-#define TOSA_GPIO_nSD_DETECT (9)
-#define TOSA_GPIO_nSD_INT (10)
-#define TOSA_GPIO_TC6393XB_CLK (11)
-#define TOSA_GPIO_BAT1_CRG (12)
-#define TOSA_GPIO_CF_CD (13)
-#define TOSA_GPIO_BAT0_CRG (14)
-#define TOSA_GPIO_TC6393XB_INT (15)
-#define TOSA_GPIO_BAT0_LOW (17)
-#define TOSA_GPIO_TC6393XB_RDY (18)
-#define TOSA_GPIO_ON_RESET (19)
-#define TOSA_GPIO_EAR_IN (20)
-#define TOSA_GPIO_CF_IRQ (21) /* CF slot0 Ready */
-#define TOSA_GPIO_ON_KEY (22)
-#define TOSA_GPIO_VGA_LINE (27)
-#define TOSA_GPIO_TP_INT (32) /* Touch Panel pen down interrupt */
-#define TOSA_GPIO_JC_CF_IRQ (36) /* CF slot1 Ready */
-#define TOSA_GPIO_BAT_LOCKED (38) /* Battery locked */
-#define TOSA_GPIO_IRDA_TX (47)
-#define TOSA_GPIO_TG_SPI_SCLK (81)
-#define TOSA_GPIO_TG_SPI_CS (82)
-#define TOSA_GPIO_TG_SPI_MOSI (83)
-#define TOSA_GPIO_BAT1_LOW (84)
-
-#define TOSA_GPIO_HP_IN GPIO_EAR_IN
-
-#define TOSA_GPIO_MAIN_BAT_LOW GPIO_BAT0_LOW
-
-#define TOSA_KEY_STROBE_NUM (11)
-#define TOSA_KEY_SENSE_NUM (7)
-
-#define TOSA_GPIO_HIGH_STROBE_BIT (0xfc000000)
-#define TOSA_GPIO_LOW_STROBE_BIT (0x0000001f)
-#define TOSA_GPIO_ALL_SENSE_BIT (0x00000fe0)
-#define TOSA_GPIO_ALL_SENSE_RSHIFT (5)
-#define TOSA_GPIO_STROBE_BIT(a) GPIO_bit(58+(a))
-#define TOSA_GPIO_SENSE_BIT(a) GPIO_bit(69+(a))
-#define TOSA_GAFR_HIGH_STROBE_BIT (0xfff00000)
-#define TOSA_GAFR_LOW_STROBE_BIT (0x000003ff)
-#define TOSA_GAFR_ALL_SENSE_BIT (0x00fffc00)
-#define TOSA_GPIO_KEY_SENSE(a) (69+(a))
-#define TOSA_GPIO_KEY_STROBE(a) (58+(a))
-
-/*
- * Interrupts
- */
-#define TOSA_IRQ_GPIO_WAKEUP PXA_GPIO_TO_IRQ(TOSA_GPIO_WAKEUP)
-#define TOSA_IRQ_GPIO_AC_IN PXA_GPIO_TO_IRQ(TOSA_GPIO_AC_IN)
-#define TOSA_IRQ_GPIO_RECORD_BTN PXA_GPIO_TO_IRQ(TOSA_GPIO_RECORD_BTN)
-#define TOSA_IRQ_GPIO_SYNC PXA_GPIO_TO_IRQ(TOSA_GPIO_SYNC)
-#define TOSA_IRQ_GPIO_USB_IN PXA_GPIO_TO_IRQ(TOSA_GPIO_USB_IN)
-#define TOSA_IRQ_GPIO_JACKET_DETECT PXA_GPIO_TO_IRQ(TOSA_GPIO_JACKET_DETECT)
-#define TOSA_IRQ_GPIO_nSD_INT PXA_GPIO_TO_IRQ(TOSA_GPIO_nSD_INT)
-#define TOSA_IRQ_GPIO_nSD_DETECT PXA_GPIO_TO_IRQ(TOSA_GPIO_nSD_DETECT)
-#define TOSA_IRQ_GPIO_BAT1_CRG PXA_GPIO_TO_IRQ(TOSA_GPIO_BAT1_CRG)
-#define TOSA_IRQ_GPIO_CF_CD PXA_GPIO_TO_IRQ(TOSA_GPIO_CF_CD)
-#define TOSA_IRQ_GPIO_BAT0_CRG PXA_GPIO_TO_IRQ(TOSA_GPIO_BAT0_CRG)
-#define TOSA_IRQ_GPIO_TC6393XB_INT PXA_GPIO_TO_IRQ(TOSA_GPIO_TC6393XB_INT)
-#define TOSA_IRQ_GPIO_BAT0_LOW PXA_GPIO_TO_IRQ(TOSA_GPIO_BAT0_LOW)
-#define TOSA_IRQ_GPIO_EAR_IN PXA_GPIO_TO_IRQ(TOSA_GPIO_EAR_IN)
-#define TOSA_IRQ_GPIO_CF_IRQ PXA_GPIO_TO_IRQ(TOSA_GPIO_CF_IRQ)
-#define TOSA_IRQ_GPIO_ON_KEY PXA_GPIO_TO_IRQ(TOSA_GPIO_ON_KEY)
-#define TOSA_IRQ_GPIO_VGA_LINE PXA_GPIO_TO_IRQ(TOSA_GPIO_VGA_LINE)
-#define TOSA_IRQ_GPIO_TP_INT PXA_GPIO_TO_IRQ(TOSA_GPIO_TP_INT)
-#define TOSA_IRQ_GPIO_JC_CF_IRQ PXA_GPIO_TO_IRQ(TOSA_GPIO_JC_CF_IRQ)
-#define TOSA_IRQ_GPIO_BAT_LOCKED PXA_GPIO_TO_IRQ(TOSA_GPIO_BAT_LOCKED)
-#define TOSA_IRQ_GPIO_BAT1_LOW PXA_GPIO_TO_IRQ(TOSA_GPIO_BAT1_LOW)
-#define TOSA_IRQ_GPIO_KEY_SENSE(a) PXA_GPIO_TO_IRQ(69+(a))
-
-#define TOSA_IRQ_GPIO_MAIN_BAT_LOW PXA_GPIO_TO_IRQ(TOSA_GPIO_MAIN_BAT_LOW)
-
-#define TOSA_KEY_SYNC KEY_102ND /* ??? */
-
-#ifndef CONFIG_TOSA_USE_EXT_KEYCODES
-#define TOSA_KEY_RECORD KEY_YEN
-#define TOSA_KEY_ADDRESSBOOK KEY_KATAKANA
-#define TOSA_KEY_CANCEL KEY_ESC
-#define TOSA_KEY_CENTER KEY_HIRAGANA
-#define TOSA_KEY_OK KEY_HENKAN
-#define TOSA_KEY_CALENDAR KEY_KATAKANAHIRAGANA
-#define TOSA_KEY_HOMEPAGE KEY_HANGEUL
-#define TOSA_KEY_LIGHT KEY_MUHENKAN
-#define TOSA_KEY_MENU KEY_HANJA
-#define TOSA_KEY_FN KEY_RIGHTALT
-#define TOSA_KEY_MAIL KEY_ZENKAKUHANKAKU
-#else
-#define TOSA_KEY_RECORD KEY_RECORD
-#define TOSA_KEY_ADDRESSBOOK KEY_ADDRESSBOOK
-#define TOSA_KEY_CANCEL KEY_CANCEL
-#define TOSA_KEY_CENTER KEY_SELECT /* ??? */
-#define TOSA_KEY_OK KEY_OK
-#define TOSA_KEY_CALENDAR KEY_CALENDAR
-#define TOSA_KEY_HOMEPAGE KEY_HOMEPAGE
-#define TOSA_KEY_LIGHT KEY_KBDILLUMTOGGLE
-#define TOSA_KEY_MENU KEY_MENU
-#define TOSA_KEY_FN KEY_FN
-#define TOSA_KEY_MAIL KEY_MAIL
-#endif
-
-#endif /* _ASM_ARCH_TOSA_H_ */
diff --git a/arch/arm/mach-pxa/include/mach/z2.h b/arch/arm/mach-pxa/include/mach/z2.h
deleted file mode 100644
index a78b2e28b1db..000000000000
--- a/arch/arm/mach-pxa/include/mach/z2.h
+++ /dev/null
@@ -1,37 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-/*
- * arch/arm/mach-pxa/include/mach/z2.h
- *
- * Author: Ken McGuire
- * Created: Feb 6, 2009
- */
-
-#ifndef ASM_ARCH_ZIPIT2_H
-#define ASM_ARCH_ZIPIT2_H
-
-/* LEDs */
-#define GPIO10_ZIPITZ2_LED_WIFI 10
-#define GPIO85_ZIPITZ2_LED_CHARGED 85
-#define GPIO83_ZIPITZ2_LED_CHARGING 83
-
-/* SD/MMC */
-#define GPIO96_ZIPITZ2_SD_DETECT 96
-
-/* GPIO Buttons */
-#define GPIO1_ZIPITZ2_POWER_BUTTON 1
-#define GPIO98_ZIPITZ2_LID_BUTTON 98
-
-/* Libertas GSPI8686 WiFi */
-#define GPIO14_ZIPITZ2_WIFI_POWER 14
-#define GPIO24_ZIPITZ2_WIFI_CS 24
-#define GPIO36_ZIPITZ2_WIFI_IRQ 36
-
-/* LCD */
-#define GPIO19_ZIPITZ2_LCD_RESET 19
-#define GPIO88_ZIPITZ2_LCD_CS 88
-
-/* MISC GPIOs */
-#define GPIO0_ZIPITZ2_AC_DETECT 0
-#define GPIO37_ZIPITZ2_HEADSET_DETECT 37
-
-#endif
generated by cgit v1.2.3 (git 2.39.0) at 2024-11-28 08:31:25 +0300