diff options
Diffstat (limited to 'arch/arm/mach-mmp/mmp2.c')
| -rw-r--r-- | arch/arm/mach-mmp/mmp2.c | 123 |
1 files changed, 123 insertions, 0 deletions
diff --git a/arch/arm/mach-mmp/mmp2.c b/arch/arm/mach-mmp/mmp2.c new file mode 100644 index 000000000000..72eb9daeea99 --- /dev/null +++ b/arch/arm/mach-mmp/mmp2.c @@ -0,0 +1,123 @@ +/* + * linux/arch/arm/mach-mmp/mmp2.c + * + * code name MMP2 + * + * Copyright (C) 2009 Marvell International Ltd. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include <linux/module.h> +#include <linux/kernel.h> +#include <linux/init.h> +#include <linux/io.h> + +#include <mach/addr-map.h> +#include <mach/regs-apbc.h> +#include <mach/regs-apmu.h> +#include <mach/cputype.h> +#include <mach/irqs.h> +#include <mach/mfp.h> +#include <mach/gpio.h> +#include <mach/devices.h> + +#include "common.h" +#include "clock.h" + +#define MFPR_VIRT_BASE (APB_VIRT_BASE + 0x1e000) + +#define APMASK(i) (GPIO_REGS_VIRT + BANK_OFF(i) + 0x9c) + +static struct mfp_addr_map mmp2_addr_map[] __initdata = { + MFP_ADDR(PMIC_INT, 0x2c4), + + MFP_ADDR_END, +}; + +void mmp2_clear_pmic_int(void) +{ + unsigned long mfpr_pmic, data; + + mfpr_pmic = APB_VIRT_BASE + 0x1e000 + 0x2c4; + data = __raw_readl(mfpr_pmic); + __raw_writel(data | (1 << 6), mfpr_pmic); + __raw_writel(data, mfpr_pmic); +} + +static void __init mmp2_init_gpio(void) +{ + int i; + + /* enable GPIO clock */ + __raw_writel(APBC_APBCLK | APBC_FNCLK, APBC_MMP2_GPIO); + + /* unmask GPIO edge detection for all 6 banks -- APMASKx */ + for (i = 0; i < 6; i++) + __raw_writel(0xffffffff, APMASK(i)); + + pxa_init_gpio(IRQ_MMP2_GPIO, 0, 167, NULL); +} + +void __init mmp2_init_irq(void) +{ + mmp2_init_icu(); + mmp2_init_gpio(); +} + +/* APB peripheral clocks */ +static APBC_CLK(uart1, MMP2_UART1, 1, 26000000); +static APBC_CLK(uart2, MMP2_UART2, 1, 26000000); +static APBC_CLK(uart3, MMP2_UART3, 1, 26000000); +static APBC_CLK(uart4, MMP2_UART4, 1, 26000000); +static APBC_CLK(twsi1, MMP2_TWSI1, 0, 26000000); +static APBC_CLK(twsi2, MMP2_TWSI2, 0, 26000000); +static APBC_CLK(twsi3, MMP2_TWSI3, 0, 26000000); +static APBC_CLK(twsi4, MMP2_TWSI4, 0, 26000000); +static APBC_CLK(twsi5, MMP2_TWSI5, 0, 26000000); +static APBC_CLK(twsi6, MMP2_TWSI6, 0, 26000000); +static APBC_CLK(rtc, MMP2_RTC, 0, 32768); + +static APMU_CLK(nand, NAND, 0xbf, 100000000); + +static struct clk_lookup mmp2_clkregs[] = { + INIT_CLKREG(&clk_uart1, "pxa2xx-uart.0", NULL), + INIT_CLKREG(&clk_uart2, "pxa2xx-uart.1", NULL), + INIT_CLKREG(&clk_uart3, "pxa2xx-uart.2", NULL), + INIT_CLKREG(&clk_uart4, "pxa2xx-uart.3", NULL), + INIT_CLKREG(&clk_twsi1, "pxa2xx-i2c.0", NULL), + INIT_CLKREG(&clk_twsi2, "pxa2xx-i2c.1", NULL), + INIT_CLKREG(&clk_twsi3, "pxa2xx-i2c.2", NULL), + INIT_CLKREG(&clk_twsi4, "pxa2xx-i2c.3", NULL), + INIT_CLKREG(&clk_twsi5, "pxa2xx-i2c.4", NULL), + INIT_CLKREG(&clk_twsi6, "pxa2xx-i2c.5", NULL), + INIT_CLKREG(&clk_nand, "pxa3xx-nand", NULL), +}; + +static int __init mmp2_init(void) +{ + if (cpu_is_mmp2()) { + mfp_init_base(MFPR_VIRT_BASE); + mfp_init_addr(mmp2_addr_map); + clks_register(ARRAY_AND_SIZE(mmp2_clkregs)); + } + + return 0; +} +postcore_initcall(mmp2_init); + +/* on-chip devices */ +MMP2_DEVICE(uart1, "pxa2xx-uart", 0, UART1, 0xd4030000, 0x30, 4, 5); +MMP2_DEVICE(uart2, "pxa2xx-uart", 1, UART2, 0xd4017000, 0x30, 20, 21); +MMP2_DEVICE(uart3, "pxa2xx-uart", 2, UART3, 0xd4018000, 0x30, 22, 23); +MMP2_DEVICE(uart4, "pxa2xx-uart", 3, UART4, 0xd4016000, 0x30, 18, 19); +MMP2_DEVICE(twsi1, "pxa2xx-i2c", 0, TWSI1, 0xd4011000, 0x70); +MMP2_DEVICE(twsi2, "pxa2xx-i2c", 1, TWSI2, 0xd4031000, 0x70); +MMP2_DEVICE(twsi3, "pxa2xx-i2c", 2, TWSI3, 0xd4032000, 0x70); +MMP2_DEVICE(twsi4, "pxa2xx-i2c", 3, TWSI4, 0xd4033000, 0x70); +MMP2_DEVICE(twsi5, "pxa2xx-i2c", 4, TWSI5, 0xd4033800, 0x70); +MMP2_DEVICE(twsi6, "pxa2xx-i2c", 5, TWSI6, 0xd4034000, 0x70); +MMP2_DEVICE(nand, "pxa3xx-nand", -1, NAND, 0xd4283000, 0x100, 28, 29); + |