diff options
Diffstat (limited to 'arch/arm/boot/dts/intel')
7 files changed, 135 insertions, 17 deletions
diff --git a/arch/arm/boot/dts/intel/ixp/intel-ixp42x-netgear-wg302v1.dts b/arch/arm/boot/dts/intel/ixp/intel-ixp42x-netgear-wg302v1.dts index 19d56e9aec9d..a351a97d257e 100644 --- a/arch/arm/boot/dts/intel/ixp/intel-ixp42x-netgear-wg302v1.dts +++ b/arch/arm/boot/dts/intel/ixp/intel-ixp42x-netgear-wg302v1.dts @@ -8,6 +8,7 @@ #include "intel-ixp42x.dtsi" #include <dt-bindings/input/input.h> +#include <dt-bindings/leds/common.h> / { model = "Netgear WG302 v1"; @@ -32,6 +33,35 @@ serial0 = &uart1; }; + leds { + compatible = "gpio-leds"; + test_led: led-test { + color = <LED_COLOR_ID_AMBER>; + function = "test"; + gpios = <&gpio0 4 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + wlan_led: led-wlan { + color = <LED_COLOR_ID_GREEN>; + function = LED_FUNCTION_WLAN; + gpios = <&gpio0 5 GPIO_ACTIVE_LOW>; + default-state = "off"; + linux,default-trigger = "phy0tx"; + }; + }; + + gpio_keys { + /* RESET is on GPIO13 which can't fire interrupts */ + compatible = "gpio-keys-polled"; + poll-interval = <100>; + + button-reset { + linux,code = <KEY_RESTART>; + label = "reset"; + gpios = <&gpio0 13 GPIO_ACTIVE_LOW>; + }; + }; + soc { bus@c4000000 { flash@0,0 { @@ -57,7 +87,7 @@ status = "okay"; /* - * Taken from WG302 v2 PCI boardfile (wg302v2-pci.c) + * Taken from WG302 v1 PCI boardfile (wg302v1-pci.c) * We have slots (IDSEL) 1 and 2 with one assigned IRQ * each handling all IRQs. */ @@ -70,10 +100,10 @@ <0x0800 0 0 3 &gpio0 8 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 1 is irq 8 */ <0x0800 0 0 4 &gpio0 8 IRQ_TYPE_LEVEL_LOW>, /* INT D on slot 1 is irq 8 */ /* IDSEL 2 */ - <0x1000 0 0 1 &gpio0 9 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 2 is irq 9 */ - <0x1000 0 0 2 &gpio0 9 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 2 is irq 9 */ - <0x1000 0 0 3 &gpio0 9 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 2 is irq 9 */ - <0x1000 0 0 4 &gpio0 9 IRQ_TYPE_LEVEL_LOW>; /* INT D on slot 2 is irq 9 */ + <0x1000 0 0 1 &gpio0 10 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 2 is irq 10 */ + <0x1000 0 0 2 &gpio0 10 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 2 is irq 10 */ + <0x1000 0 0 3 &gpio0 10 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 2 is irq 10 */ + <0x1000 0 0 4 &gpio0 10 IRQ_TYPE_LEVEL_LOW>; /* INT D on slot 2 is irq 10 */ }; ethernet@c8009000 { diff --git a/arch/arm/boot/dts/intel/ixp/intel-ixp4xx.dtsi b/arch/arm/boot/dts/intel/ixp/intel-ixp4xx.dtsi index 51a716c59669..0adeccabd4fe 100644 --- a/arch/arm/boot/dts/intel/ixp/intel-ixp4xx.dtsi +++ b/arch/arm/boot/dts/intel/ixp/intel-ixp4xx.dtsi @@ -193,10 +193,10 @@ compatible = "intel,ixp4xx-ethernet"; reg = <0xc800c000 0x1000>; status = "disabled"; - intel,npe = <0>; /* Dummy values that depend on firmware */ queue-rx = <&qmgr 0>; queue-txready = <&qmgr 0>; + intel,npe-handle = <&npe 0>; }; }; }; diff --git a/arch/arm/boot/dts/intel/socfpga/Makefile b/arch/arm/boot/dts/intel/socfpga/Makefile index c467828aeb4b..7f69a0355ea5 100644 --- a/arch/arm/boot/dts/intel/socfpga/Makefile +++ b/arch/arm/boot/dts/intel/socfpga/Makefile @@ -10,6 +10,7 @@ dtb-$(CONFIG_ARCH_INTEL_SOCFPGA) += \ socfpga_cyclone5_mcvevk.dtb \ socfpga_cyclone5_socdk.dtb \ socfpga_cyclone5_de0_nano_soc.dtb \ + socfpga_cyclone5_de10nano.dtb \ socfpga_cyclone5_sockit.dtb \ socfpga_cyclone5_socrates.dtb \ socfpga_cyclone5_sodia.dtb \ diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga_arria10.dtsi b/arch/arm/boot/dts/intel/socfpga/socfpga_arria10.dtsi index 6b6e77596ffa..b108265e9bde 100644 --- a/arch/arm/boot/dts/intel/socfpga/socfpga_arria10.dtsi +++ b/arch/arm/boot/dts/intel/socfpga/socfpga_arria10.dtsi @@ -440,7 +440,7 @@ clocks = <&l4_mp_clk>, <&peri_emac_ptp_clk>; clock-names = "stmmaceth", "ptp_ref"; resets = <&rst EMAC0_RESET>, <&rst EMAC0_OCP_RESET>; - reset-names = "stmmaceth", "ahb"; + reset-names = "stmmaceth", "stmmaceth-ocp"; snps,axi-config = <&socfpga_axi_setup>; status = "disabled"; }; @@ -460,7 +460,7 @@ clocks = <&l4_mp_clk>, <&peri_emac_ptp_clk>; clock-names = "stmmaceth", "ptp_ref"; resets = <&rst EMAC1_RESET>, <&rst EMAC1_OCP_RESET>; - reset-names = "stmmaceth", "ahb"; + reset-names = "stmmaceth", "stmmaceth-ocp"; snps,axi-config = <&socfpga_axi_setup>; status = "disabled"; }; @@ -480,7 +480,7 @@ clocks = <&l4_mp_clk>, <&peri_emac_ptp_clk>; clock-names = "stmmaceth", "ptp_ref"; resets = <&rst EMAC2_RESET>, <&rst EMAC2_OCP_RESET>; - reset-names = "stmmaceth", "ahb"; + reset-names = "stmmaceth", "stmmaceth-ocp"; snps,axi-config = <&socfpga_axi_setup>; status = "disabled"; }; diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_de10nano.dts b/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_de10nano.dts new file mode 100644 index 000000000000..ec25106caacf --- /dev/null +++ b/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_de10nano.dts @@ -0,0 +1,95 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2017, Intel Corporation + * + * based on socfpga_cyclone5_de0_nano_soc.dts + */ +/dts-v1/; + +#include "socfpga_cyclone5.dtsi" +#include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/gpio/gpio.h> + +/ { + model = "Terasic DE10-Nano"; + compatible = "terasic,de10-nano", "altr,socfpga-cyclone5", "altr,socfpga"; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory@0 { + /* 1 GiB */ + device_type = "memory"; + reg = <0x0 0x40000000>; + }; + + soc { + fpga: bus@ff200000 { + compatible = "simple-bus"; + reg = <0xff200000 0x00200000>; + ranges = <0x00000000 0xff200000 0x00200000>; + #address-cells = <1>; + #size-cells = <1>; + + /* + * Here the devices will appear if an FPGA image is + * loaded. Their description is expected to be added + * using a device tree overlay that matches the image. + */ + }; + }; +}; + +&gmac1 { + /* Uses a KSZ9031RNX phy */ + phy-mode = "rgmii-id"; + rxd0-skew-ps = <420>; + rxd1-skew-ps = <420>; + rxd2-skew-ps = <420>; + rxd3-skew-ps = <420>; + txen-skew-ps = <0>; + rxdv-skew-ps = <420>; + status = "okay"; +}; + +&gpio0 { + status = "okay"; +}; + +&gpio1 { + status = "okay"; +}; + +&gpio2 { + status = "okay"; +}; + +&i2c0 { + clock-frequency = <100000>; + status = "okay"; + + accelerometer@53 { + compatible = "adi,adxl345"; + reg = <0x53>; + /* HPS_GSENSOR_INT is routed to UART0_RX/CAN0_RX/SPIM0_SS1/HPS_GPIO61 */ + interrupt-parent = <&portc>; + interrupts = <3 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "INT1"; + }; +}; + +&mmc0 { + /* micro SD card socket J11 */ + status = "okay"; +}; + +&uart0 { + /* + * Accessible via USB (FT232R) on Mini-USB plug J4 + * RX = TRACE_D0/SPIS0_CLK/UART0_RX/HPS_GPIO49 + * TX = TRACE_D1/SPIS0_MOSI/UART0_TX/HPS_GPIO50 + * no handshaking lines + */ + clock-frequency = <100000000>; +}; diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mcvevk.dts b/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mcvevk.dts index ceaec29770c6..c1e1264bcb09 100644 --- a/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mcvevk.dts +++ b/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mcvevk.dts @@ -50,8 +50,6 @@ stmpe1: stmpe811@41 { compatible = "st,stmpe811"; - #address-cells = <1>; - #size-cells = <0>; reg = <0x41>; id = <0>; blocks = <0x5>; diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_socdk.dts b/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_socdk.dts index d37a982e8571..97622febc44e 100644 --- a/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_socdk.dts +++ b/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_socdk.dts @@ -151,12 +151,6 @@ &spi0 { status = "okay"; - - spidev@0 { - compatible = "rohm,dh2228fv"; - reg = <0>; - spi-max-frequency = <1000000>; - }; }; &usb1 { |