diff options
Diffstat (limited to 'Documentation')
13 files changed, 439 insertions, 221 deletions
diff --git a/Documentation/PCI/msi-howto.rst b/Documentation/PCI/msi-howto.rst index 667ebe2156b4..844c1d3c395d 100644 --- a/Documentation/PCI/msi-howto.rst +++ b/Documentation/PCI/msi-howto.rst @@ -113,8 +113,11 @@ vectors, use the following function:: int pci_irq_vector(struct pci_dev *dev, unsigned int nr); -Any allocated resources should be freed before removing the device using -the following function:: +If the driver enables the device using pcim_enable_device(), the driver +shouldn't call pci_free_irq_vectors() because pcim_enable_device() +activates automatic management for IRQ vectors. Otherwise, the driver should +free any allocated IRQ vectors before removing the device using the following +function:: void pci_free_irq_vectors(struct pci_dev *dev); diff --git a/Documentation/devicetree/bindings/pci/andestech,qilai-pcie.yaml b/Documentation/devicetree/bindings/pci/andestech,qilai-pcie.yaml new file mode 100644 index 000000000000..97ba97fdc5a9 --- /dev/null +++ b/Documentation/devicetree/bindings/pci/andestech,qilai-pcie.yaml @@ -0,0 +1,89 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pci/andestech,qilai-pcie.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Andes QiLai PCIe host controller + +description: + Andes QiLai PCIe host controller is based on the Synopsys DesignWare + PCI core. + +maintainers: + - Randolph Lin <randolph@andestech.com> + +allOf: + - $ref: /schemas/pci/snps,dw-pcie.yaml# + +properties: + compatible: + const: andestech,qilai-pcie + + reg: + items: + - description: Data Bus Interface (DBI) registers. + - description: APB registers. + - description: PCIe configuration space region. + + reg-names: + items: + - const: dbi + - const: apb + - const: config + + dma-coherent: true + + ranges: + maxItems: 2 + + interrupts: + maxItems: 1 + + interrupt-names: + items: + - const: msi + +required: + - reg + - reg-names + - interrupts + - interrupt-names + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/irq.h> + + soc { + #address-cells = <2>; + #size-cells = <2>; + + pcie@80000000 { + compatible = "andestech,qilai-pcie"; + device_type = "pci"; + reg = <0x0 0x80000000 0x0 0x20000000>, + <0x0 0x04000000 0x0 0x00001000>, + <0x0 0x00000000 0x0 0x00010000>; + reg-names = "dbi", "apb", "config"; + dma-coherent; + + linux,pci-domain = <0>; + #address-cells = <3>; + #size-cells = <2>; + ranges = <0x02000000 0x00 0x10000000 0x00 0x10000000 0x00 0xf0000000>, + <0x43000000 0x01 0x00000000 0x01 0x00000000 0x02 0x00000000>; + + #interrupt-cells = <1>; + interrupts = <0xf>; + interrupt-names = "msi"; + interrupt-parent = <&plic0>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 1 &plic0 0xf IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 2 &plic0 0xf IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 3 &plic0 0xf IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 4 &plic0 0xf IRQ_TYPE_LEVEL_HIGH>; + }; + }; +... diff --git a/Documentation/devicetree/bindings/pci/baikal,bt1-pcie.yaml b/Documentation/devicetree/bindings/pci/baikal,bt1-pcie.yaml deleted file mode 100644 index 8eaa07ae9774..000000000000 --- a/Documentation/devicetree/bindings/pci/baikal,bt1-pcie.yaml +++ /dev/null @@ -1,168 +0,0 @@ -# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) -%YAML 1.2 ---- -$id: http://devicetree.org/schemas/pci/baikal,bt1-pcie.yaml# -$schema: http://devicetree.org/meta-schemas/core.yaml# - -title: Baikal-T1 PCIe Root Port Controller - -maintainers: - - Serge Semin <fancer.lancer@gmail.com> - -description: - Embedded into Baikal-T1 SoC Root Complex controller with a single port - activated. It's based on the DWC RC PCIe v4.60a IP-core, which is configured - to have just a single Root Port function and is capable of establishing the - link up to Gen.3 speed on x4 lanes. It doesn't have embedded clock and reset - control module, so the proper interface initialization is supposed to be - performed by software. There four in- and four outbound iATU regions - which can be used to emit all required TLP types on the PCIe bus. - -allOf: - - $ref: /schemas/pci/snps,dw-pcie.yaml# - -properties: - compatible: - const: baikal,bt1-pcie - - reg: - description: - DBI, DBI2 and at least 4KB outbound iATU-capable region for the - peripheral devices CFG-space access. - maxItems: 3 - - reg-names: - items: - - const: dbi - - const: dbi2 - - const: config - - interrupts: - description: - MSI, AER, PME, Hot-plug, Link Bandwidth Management, Link Equalization - request and eight Read/Write eDMA IRQ lines are available. - maxItems: 14 - - interrupt-names: - items: - - const: dma0 - - const: dma1 - - const: dma2 - - const: dma3 - - const: dma4 - - const: dma5 - - const: dma6 - - const: dma7 - - const: msi - - const: aer - - const: pme - - const: hp - - const: bw_mg - - const: l_eq - - clocks: - description: - DBI (attached to the APB bus), AXI-bus master and slave interfaces - are fed up by the dedicated application clocks. A common reference - clock signal is supposed to be attached to the corresponding Ref-pad - of the SoC. It will be redistributed amongst the controller core - sub-modules (pipe, core, aux, etc). - maxItems: 4 - - clock-names: - items: - - const: dbi - - const: mstr - - const: slv - - const: ref - - resets: - description: - A comprehensive controller reset logic is supposed to be implemented - by software, so almost all the possible application and core reset - signals are exposed via the system CCU module. - maxItems: 9 - - reset-names: - items: - - const: mstr - - const: slv - - const: pwr - - const: hot - - const: phy - - const: core - - const: pipe - - const: sticky - - const: non-sticky - - baikal,bt1-syscon: - $ref: /schemas/types.yaml#/definitions/phandle - description: - Phandle to the Baikal-T1 System Controller DT node. It's required to - access some additional PM, Reset-related and LTSSM signals. - - num-lanes: - maximum: 4 - - max-link-speed: - maximum: 3 - -required: - - compatible - - reg - - reg-names - - interrupts - - interrupt-names - -unevaluatedProperties: false - -examples: - - | - #include <dt-bindings/interrupt-controller/mips-gic.h> - #include <dt-bindings/gpio/gpio.h> - - pcie@1f052000 { - compatible = "baikal,bt1-pcie"; - device_type = "pci"; - reg = <0x1f052000 0x1000>, <0x1f053000 0x1000>, <0x1bdbf000 0x1000>; - reg-names = "dbi", "dbi2", "config"; - #address-cells = <3>; - #size-cells = <2>; - ranges = <0x81000000 0 0x00000000 0x1bdb0000 0 0x00008000>, - <0x82000000 0 0x20000000 0x08000000 0 0x13db0000>; - bus-range = <0x0 0xff>; - - interrupts = <GIC_SHARED 80 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SHARED 81 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SHARED 82 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SHARED 83 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SHARED 84 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SHARED 85 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SHARED 86 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SHARED 87 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SHARED 88 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SHARED 89 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SHARED 90 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SHARED 91 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SHARED 92 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SHARED 93 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "dma0", "dma1", "dma2", "dma3", - "dma4", "dma5", "dma6", "dma7", - "msi", "aer", "pme", "hp", "bw_mg", - "l_eq"; - - clocks = <&ccu_sys 1>, <&ccu_axi 6>, <&ccu_axi 7>, <&clk_pcie>; - clock-names = "dbi", "mstr", "slv", "ref"; - - resets = <&ccu_axi 6>, <&ccu_axi 7>, <&ccu_sys 7>, <&ccu_sys 10>, - <&ccu_sys 4>, <&ccu_sys 6>, <&ccu_sys 5>, <&ccu_sys 8>, - <&ccu_sys 9>; - reset-names = "mstr", "slv", "pwr", "hot", "phy", "core", "pipe", - "sticky", "non-sticky"; - - reset-gpios = <&port0 0 GPIO_ACTIVE_LOW>; - - num-lanes = <4>; - max-link-speed = <3>; - }; -... diff --git a/Documentation/devicetree/bindings/pci/cix,sky1-pcie-host.yaml b/Documentation/devicetree/bindings/pci/cix,sky1-pcie-host.yaml index b910a42e0843..d55d165f1e94 100644 --- a/Documentation/devicetree/bindings/pci/cix,sky1-pcie-host.yaml +++ b/Documentation/devicetree/bindings/pci/cix,sky1-pcie-host.yaml @@ -38,6 +38,9 @@ properties: ranges: maxItems: 3 + power-domains: + maxItems: 1 + required: - compatible - ranges diff --git a/Documentation/devicetree/bindings/pci/eswin,pcie.yaml b/Documentation/devicetree/bindings/pci/eswin,pcie.yaml new file mode 100644 index 000000000000..057e1f363dde --- /dev/null +++ b/Documentation/devicetree/bindings/pci/eswin,pcie.yaml @@ -0,0 +1,166 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pci/eswin,pcie.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: ESWIN PCIe Root Complex + +maintainers: + - Yu Ning <ningyu@eswincomputing.com> + - Senchuan Zhang <zhangsenchuan@eswincomputing.com> + - Yanghui Ou <ouyanghui@eswincomputing.com> + +description: + ESWIN SoCs PCIe Root Complex is based on the Synopsys DesignWare PCIe IP. + +properties: + compatible: + const: eswin,eic7700-pcie + + reg: + maxItems: 3 + + reg-names: + items: + - const: dbi + - const: config + - const: elbi + + ranges: + maxItems: 3 + + '#interrupt-cells': + const: 1 + + interrupt-names: + items: + - const: msi + - const: inta + - const: intb + - const: intc + - const: intd + + interrupt-map: + maxItems: 4 + + interrupt-map-mask: + items: + - const: 0 + - const: 0 + - const: 0 + - const: 7 + + clocks: + maxItems: 4 + + clock-names: + items: + - const: mstr + - const: dbi + - const: phy_reg + - const: aux + + resets: + maxItems: 2 + + reset-names: + items: + - const: dbi + - const: pwr + +patternProperties: + "^pcie@": + type: object + $ref: /schemas/pci/pci-pci-bridge.yaml# + + properties: + reg: + maxItems: 1 + + num-lanes: + maximum: 4 + + resets: + maxItems: 1 + + reset-names: + items: + - const: perst + + required: + - reg + - ranges + - num-lanes + - resets + - reset-names + + unevaluatedProperties: false + +required: + - compatible + - reg + - ranges + - interrupts + - interrupt-names + - interrupt-map-mask + - interrupt-map + - '#interrupt-cells' + - clocks + - clock-names + - resets + - reset-names + +allOf: + - $ref: /schemas/pci/snps,dw-pcie.yaml# + +unevaluatedProperties: false + +examples: + - | + soc { + #address-cells = <2>; + #size-cells = <2>; + + pcie@54000000 { + compatible = "eswin,eic7700-pcie"; + reg = <0x0 0x54000000 0x0 0x4000000>, + <0x0 0x40000000 0x0 0x800000>, + <0x0 0x50000000 0x0 0x100000>; + reg-names = "dbi", "config", "elbi"; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + ranges = <0x01000000 0x0 0x40800000 0x0 0x40800000 0x0 0x800000>, + <0x02000000 0x0 0x41000000 0x0 0x41000000 0x0 0xf000000>, + <0x43000000 0x80 0x00000000 0x80 0x00000000 0x2 0x00000000>; + bus-range = <0x00 0xff>; + clocks = <&clock 144>, + <&clock 145>, + <&clock 146>, + <&clock 147>; + clock-names = "mstr", "dbi", "phy_reg", "aux"; + resets = <&reset 97>, + <&reset 98>; + reset-names = "dbi", "pwr"; + interrupts = <220>, <179>, <180>, <181>, <182>, <183>, <184>, <185>, <186>; + interrupt-names = "msi", "inta", "intb", "intc", "intd"; + interrupt-parent = <&plic>; + interrupt-map-mask = <0x0 0x0 0x0 0x7>; + interrupt-map = <0x0 0x0 0x0 0x1 &plic 179>, + <0x0 0x0 0x0 0x2 &plic 180>, + <0x0 0x0 0x0 0x3 &plic 181>, + <0x0 0x0 0x0 0x4 &plic 182>; + device_type = "pci"; + pcie@0 { + reg = <0x0 0x0 0x0 0x0 0x0>; + #address-cells = <3>; + #size-cells = <2>; + ranges; + device_type = "pci"; + num-lanes = <4>; + resets = <&reset 99>; + reset-names = "perst"; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie-common.yaml b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie-common.yaml index cddbe21f99f2..0488c942092d 100644 --- a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie-common.yaml +++ b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie-common.yaml @@ -17,11 +17,11 @@ description: properties: clocks: minItems: 3 - maxItems: 5 + maxItems: 6 clock-names: minItems: 3 - maxItems: 5 + maxItems: 6 num-lanes: const: 1 diff --git a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie-ep.yaml b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie-ep.yaml index 0b3526de1d62..e4e30da0acb0 100644 --- a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie-ep.yaml +++ b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie-ep.yaml @@ -18,12 +18,18 @@ description: |+ properties: compatible: - enum: - - fsl,imx8mm-pcie-ep - - fsl,imx8mq-pcie-ep - - fsl,imx8mp-pcie-ep - - fsl,imx8q-pcie-ep - - fsl,imx95-pcie-ep + oneOf: + - enum: + - fsl,imx8mm-pcie-ep + - fsl,imx8mp-pcie-ep + - fsl,imx8mq-pcie-ep + - fsl,imx8q-pcie-ep + - fsl,imx95-pcie-ep + - items: + - enum: + - fsl,imx94-pcie-ep + - fsl,imx943-pcie-ep + - const: fsl,imx95-pcie-ep clocks: minItems: 3 diff --git a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml index 12a01f7a5744..9d1349855b42 100644 --- a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml +++ b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml @@ -21,16 +21,22 @@ description: |+ properties: compatible: - enum: - - fsl,imx6q-pcie - - fsl,imx6sx-pcie - - fsl,imx6qp-pcie - - fsl,imx7d-pcie - - fsl,imx8mq-pcie - - fsl,imx8mm-pcie - - fsl,imx8mp-pcie - - fsl,imx95-pcie - - fsl,imx8q-pcie + oneOf: + - enum: + - fsl,imx6q-pcie + - fsl,imx6qp-pcie + - fsl,imx6sx-pcie + - fsl,imx7d-pcie + - fsl,imx8mm-pcie + - fsl,imx8mp-pcie + - fsl,imx8mq-pcie + - fsl,imx8q-pcie + - fsl,imx95-pcie + - items: + - enum: + - fsl,imx94-pcie + - fsl,imx943-pcie + - const: fsl,imx95-pcie clocks: minItems: 3 @@ -40,7 +46,8 @@ properties: - description: PCIe PHY clock. - description: Additional required clock entry for imx6sx-pcie, imx6sx-pcie-ep, imx8mq-pcie, imx8mq-pcie-ep. - - description: PCIe reference clock. + - description: PCIe internal reference clock. + - description: PCIe additional external reference clock. clock-names: minItems: 3 diff --git a/Documentation/devicetree/bindings/pci/nvidia,tegra194-pcie-ep.yaml b/Documentation/devicetree/bindings/pci/nvidia,tegra194-pcie-ep.yaml index 6d6052a2748f..7805757f2e2d 100644 --- a/Documentation/devicetree/bindings/pci/nvidia,tegra194-pcie-ep.yaml +++ b/Documentation/devicetree/bindings/pci/nvidia,tegra194-pcie-ep.yaml @@ -55,12 +55,16 @@ properties: - const: intr clocks: + minItems: 1 items: - - description: module clock + - description: core clock + - description: monitor clock clock-names: + minItems: 1 items: - const: core + - const: core_m resets: items: diff --git a/Documentation/devicetree/bindings/pci/nvidia,tegra194-pcie.yaml b/Documentation/devicetree/bindings/pci/nvidia,tegra194-pcie.yaml index fe81d52c7277..41041ae7e0a4 100644 --- a/Documentation/devicetree/bindings/pci/nvidia,tegra194-pcie.yaml +++ b/Documentation/devicetree/bindings/pci/nvidia,tegra194-pcie.yaml @@ -58,12 +58,16 @@ properties: - const: msi clocks: + minItems: 1 items: - - description: module clock + - description: core clock + - description: monitor clock clock-names: + minItems: 1 items: - const: core + - const: core_m resets: items: diff --git a/Documentation/devicetree/bindings/pci/renesas,r9a08g045-pcie.yaml b/Documentation/devicetree/bindings/pci/renesas,r9a08g045-pcie.yaml index d668782546a2..a67108c48feb 100644 --- a/Documentation/devicetree/bindings/pci/renesas,r9a08g045-pcie.yaml +++ b/Documentation/devicetree/bindings/pci/renesas,r9a08g045-pcie.yaml @@ -10,17 +10,21 @@ maintainers: - Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> description: - Renesas RZ/G3S PCIe host controller complies with PCIe Base Specification - 4.0 and supports up to 5 GT/s (Gen2). + Renesas RZ/G3{E,S} PCIe host controllers comply with PCIe + Base Specification 4.0 and support up to 5 GT/s (Gen2) for RZ/G3S and + up to 8 GT/s (Gen3) for RZ/G3E. properties: compatible: - const: renesas,r9a08g045-pcie # RZ/G3S + enum: + - renesas,r9a08g045-pcie # RZ/G3S + - renesas,r9a09g047-pcie # RZ/G3E reg: maxItems: 1 interrupts: + minItems: 16 items: - description: System error interrupt - description: System error on correctable error interrupt @@ -38,39 +42,55 @@ properties: - description: PCIe event interrupt - description: Message interrupt - description: All interrupts + - description: Link equalization request interrupt + - description: Turn off event interrupt + - description: PMU power off interrupt + - description: D3 event function 0 interrupt + - description: D3 event function 1 interrupt + - description: Configuration PMCSR write clear function 0 interrupt + - description: Configuration PMCSR write clear function 1 interrupt interrupt-names: + minItems: 16 items: - - description: serr - - description: ser_cor - - description: serr_nonfatal - - description: serr_fatal - - description: axi_err - - description: inta - - description: intb - - description: intc - - description: intd - - description: msi - - description: link_bandwidth - - description: pm_pme - - description: dma - - description: pcie_evt - - description: msg - - description: all + - const: serr + - const: serr_cor + - const: serr_nonfatal + - const: serr_fatal + - const: axi_err + - const: inta + - const: intb + - const: intc + - const: intd + - const: msi + - const: link_bandwidth + - const: pm_pme + - const: dma + - const: pcie_evt + - const: msg + - const: all + - const: link_equalization_request + - const: turn_off_event + - const: pmu_poweroff + - const: d3_event_f0 + - const: d3_event_f1 + - const: cfg_pmcsr_writeclear_f0 + - const: cfg_pmcsr_writeclear_f1 interrupt-controller: true clocks: items: - description: System clock - - description: PM control clock + - description: PM control clock or clock for L1 substate handling clock-names: items: - - description: aclk - - description: pm + - const: aclk + - enum: [pm, pmu] resets: + minItems: 1 items: - description: AXI2PCIe Bridge reset - description: Data link layer/transaction layer reset @@ -81,14 +101,15 @@ properties: - description: Configuration register reset reset-names: + minItems: 1 items: - - description: aresetn - - description: rst_b - - description: rst_gp_b - - description: rst_ps_b - - description: rst_rsm_b - - description: rst_cfg_b - - description: rst_load_b + - const: aresetn + - const: rst_b + - const: rst_gp_b + - const: rst_ps_b + - const: rst_rsm_b + - const: rst_cfg_b + - const: rst_load_b power-domains: maxItems: 1 @@ -128,7 +149,9 @@ patternProperties: const: 0x1912 device-id: - const: 0x0033 + enum: + - 0x0033 + - 0x0039 clocks: items: @@ -167,6 +190,44 @@ required: allOf: - $ref: /schemas/pci/pci-host-bridge.yaml# + - if: + properties: + compatible: + contains: + const: renesas,r9a08g045-pcie + then: + properties: + interrupts: + maxItems: 16 + interrupt-names: + maxItems: 16 + clock-names: + items: + - const: aclk + - const: pm + resets: + minItems: 7 + reset-names: + minItems: 7 + - if: + properties: + compatible: + contains: + const: renesas,r9a09g047-pcie + then: + properties: + interrupts: + minItems: 23 + interrupt-names: + minItems: 23 + clock-names: + items: + - const: aclk + - const: pmu + resets: + maxItems: 1 + reset-names: + maxItems: 1 unevaluatedProperties: false diff --git a/Documentation/trace/events-pci-controller.rst b/Documentation/trace/events-pci-controller.rst new file mode 100644 index 000000000000..cb9f71592973 --- /dev/null +++ b/Documentation/trace/events-pci-controller.rst @@ -0,0 +1,42 @@ +.. SPDX-License-Identifier: GPL-2.0 + +====================================== +Subsystem Trace Points: PCI Controller +====================================== + +Overview +======== +The PCI controller tracing system provides tracepoints to monitor controller +level information for debugging purpose. The events normally show up here: + + /sys/kernel/tracing/events/pci_controller + +Cf. include/trace/events/pci_controller.h for the events definitions. + +Available Tracepoints +===================== + +pcie_ltssm_state_transition +--------------------------- + +Monitors PCIe LTSSM state transition including state and rate information +:: + + pcie_ltssm_state_transition "dev: %s state: %s rate: %s\n" + +**Parameters**: + +* ``dev`` - PCIe controller instance +* ``state`` - PCIe LTSSM state +* ``rate`` - PCIe date rate + +**Example Usage**: + +.. code-block:: shell + + # Enable the tracepoint + echo 1 > /sys/kernel/debug/tracing/events/pci_controller/pcie_ltssm_state_transition/enable + + # Monitor events (the following output is generated when a device is linking) + cat /sys/kernel/debug/tracing/trace_pipe + kworker/0:0-9 [000] ..... 5.600221: pcie_ltssm_state_transition: dev: a40000000.pcie state: RCVRY_EQ2 rate: 8.0 GT/s diff --git a/Documentation/trace/index.rst b/Documentation/trace/index.rst index 338bc4d7cfab..5715a32866ab 100644 --- a/Documentation/trace/index.rst +++ b/Documentation/trace/index.rst @@ -55,6 +55,7 @@ applications. events-nmi events-msr events-pci + events-pci-controller boottime-trace histogram histogram-design |