diff options
Diffstat (limited to 'Documentation/devicetree/bindings/net')
29 files changed, 1043 insertions, 257 deletions
diff --git a/Documentation/devicetree/bindings/net/airoha,en7581-eth.yaml b/Documentation/devicetree/bindings/net/airoha,en7581-eth.yaml index 6d22131ac2f9..fbe2ddcdd909 100644 --- a/Documentation/devicetree/bindings/net/airoha,en7581-eth.yaml +++ b/Documentation/devicetree/bindings/net/airoha,en7581-eth.yaml @@ -17,6 +17,7 @@ properties: compatible: enum: - airoha,en7581-eth + - airoha,an7583-eth reg: items: @@ -44,6 +45,7 @@ properties: - description: PDMA irq resets: + minItems: 7 maxItems: 8 reset-names: @@ -54,8 +56,9 @@ properties: - const: xsi-mac - const: hsi0-mac - const: hsi1-mac - - const: hsi-mac + - enum: [ hsi-mac, xfp-mac ] - const: xfp-mac + minItems: 7 memory-region: items: @@ -81,6 +84,36 @@ properties: interface to implement hardware flow offloading programming Packet Processor Engine (PPE) flow table. +allOf: + - $ref: ethernet-controller.yaml# + - if: + properties: + compatible: + contains: + enum: + - airoha,en7581-eth + then: + properties: + resets: + minItems: 8 + + reset-names: + minItems: 8 + + - if: + properties: + compatible: + contains: + enum: + - airoha,an7583-eth + then: + properties: + resets: + maxItems: 7 + + reset-names: + maxItems: 7 + patternProperties: "^ethernet@[1-4]$": type: object diff --git a/Documentation/devicetree/bindings/net/airoha,en7581-npu.yaml b/Documentation/devicetree/bindings/net/airoha,en7581-npu.yaml index c7644e6586d3..59c57f58116b 100644 --- a/Documentation/devicetree/bindings/net/airoha,en7581-npu.yaml +++ b/Documentation/devicetree/bindings/net/airoha,en7581-npu.yaml @@ -18,6 +18,7 @@ properties: compatible: enum: - airoha,en7581-npu + - airoha,an7583-npu reg: maxItems: 1 diff --git a/Documentation/devicetree/bindings/net/amd,xgbe-seattle-v1a.yaml b/Documentation/devicetree/bindings/net/amd,xgbe-seattle-v1a.yaml new file mode 100644 index 000000000000..006add8b6410 --- /dev/null +++ b/Documentation/devicetree/bindings/net/amd,xgbe-seattle-v1a.yaml @@ -0,0 +1,147 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/net/amd,xgbe-seattle-v1a.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: AMD XGBE Seattle v1a + +maintainers: + - Shyam Sundar S K <Shyam-sundar.S-k@amd.com> + +allOf: + - $ref: /schemas/net/ethernet-controller.yaml# + +properties: + compatible: + const: amd,xgbe-seattle-v1a + + reg: + items: + - description: MAC registers + - description: PCS registers + - description: SerDes Rx/Tx registers + - description: SerDes integration registers (1/2) + - description: SerDes integration registers (2/2) + + interrupts: + description: Device interrupts. The first entry is the general device + interrupt. If amd,per-channel-interrupt is specified, each DMA channel + interrupt must be specified. The last entry is the PCS auto-negotiation + interrupt. + minItems: 2 + maxItems: 6 + + clocks: + items: + - description: DMA clock for the device + - description: PTP clock for the device + + clock-names: + items: + - const: dma_clk + - const: ptp_clk + + iommus: + maxItems: 1 + + phy-mode: true + + dma-coherent: true + + amd,per-channel-interrupt: + description: Indicates that Rx and Tx complete will generate a unique + interrupt for each DMA channel. + type: boolean + + amd,speed-set: + description: > + Speed capabilities of the device. + 0 = 1GbE and 10GbE + 1 = 2.5GbE and 10GbE + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [0, 1] + + amd,serdes-blwc: + description: Baseline wandering correction enablement for each speed. + $ref: /schemas/types.yaml#/definitions/uint32-array + minItems: 3 + maxItems: 3 + items: + enum: [0, 1] + + amd,serdes-cdr-rate: + description: CDR rate speed selection for each speed. + $ref: /schemas/types.yaml#/definitions/uint32-array + items: + - description: CDR rate for 1GbE + - description: CDR rate for 2.5GbE + - description: CDR rate for 10GbE + + amd,serdes-pq-skew: + description: PQ data sampling skew for each speed. + $ref: /schemas/types.yaml#/definitions/uint32-array + items: + - description: PQ skew for 1GbE + - description: PQ skew for 2.5GbE + - description: PQ skew for 10GbE + + amd,serdes-tx-amp: + description: TX amplitude boost for each speed. + $ref: /schemas/types.yaml#/definitions/uint32-array + items: + - description: TX amplitude for 1GbE + - description: TX amplitude for 2.5GbE + - description: TX amplitude for 10GbE + + amd,serdes-dfe-tap-config: + description: DFE taps available to run for each speed. + $ref: /schemas/types.yaml#/definitions/uint32-array + items: + - description: DFE taps available for 1GbE + - description: DFE taps available for 2.5GbE + - description: DFE taps available for 10GbE + + amd,serdes-dfe-tap-enable: + description: DFE taps to enable for each speed. + $ref: /schemas/types.yaml#/definitions/uint32-array + items: + - description: DFE taps to enable for 1GbE + - description: DFE taps to enable for 2.5GbE + - description: DFE taps to enable for 10GbE + +required: + - compatible + - reg + - interrupts + - clocks + - clock-names + - phy-mode + +unevaluatedProperties: false + +examples: + - | + ethernet@e0700000 { + compatible = "amd,xgbe-seattle-v1a"; + reg = <0xe0700000 0x80000>, + <0xe0780000 0x80000>, + <0xe1240800 0x00400>, + <0xe1250000 0x00060>, + <0xe1250080 0x00004>; + interrupts = <0 325 4>, + <0 326 1>, <0 327 1>, <0 328 1>, <0 329 1>, + <0 323 4>; + amd,per-channel-interrupt; + clocks = <&xgbe_dma_clk>, <&xgbe_ptp_clk>; + clock-names = "dma_clk", "ptp_clk"; + phy-mode = "xgmii"; + mac-address = [ 02 a1 a2 a3 a4 a5 ]; + amd,speed-set = <0>; + amd,serdes-blwc = <1>, <1>, <0>; + amd,serdes-cdr-rate = <2>, <2>, <7>; + amd,serdes-pq-skew = <10>, <10>, <30>; + amd,serdes-tx-amp = <15>, <15>, <10>; + amd,serdes-dfe-tap-config = <3>, <3>, <1>; + amd,serdes-dfe-tap-enable = <0>, <0>, <127>; + }; diff --git a/Documentation/devicetree/bindings/net/amd-xgbe.txt b/Documentation/devicetree/bindings/net/amd-xgbe.txt deleted file mode 100644 index 9c27dfcd1133..000000000000 --- a/Documentation/devicetree/bindings/net/amd-xgbe.txt +++ /dev/null @@ -1,76 +0,0 @@ -* AMD 10GbE driver (amd-xgbe) - -Required properties: -- compatible: Should be "amd,xgbe-seattle-v1a" -- reg: Address and length of the register sets for the device - - MAC registers - - PCS registers - - SerDes Rx/Tx registers - - SerDes integration registers (1/2) - - SerDes integration registers (2/2) -- interrupts: Should contain the amd-xgbe interrupt(s). The first interrupt - listed is required and is the general device interrupt. If the optional - amd,per-channel-interrupt property is specified, then one additional - interrupt for each DMA channel supported by the device should be specified. - The last interrupt listed should be the PCS auto-negotiation interrupt. -- clocks: - - DMA clock for the amd-xgbe device (used for calculating the - correct Rx interrupt watchdog timer value on a DMA channel - for coalescing) - - PTP clock for the amd-xgbe device -- clock-names: Should be the names of the clocks - - "dma_clk" for the DMA clock - - "ptp_clk" for the PTP clock -- phy-mode: See ethernet.txt file in the same directory - -Optional properties: -- dma-coherent: Present if dma operations are coherent -- amd,per-channel-interrupt: Indicates that Rx and Tx complete will generate - a unique interrupt for each DMA channel - this requires an additional - interrupt be configured for each DMA channel -- amd,speed-set: Speed capabilities of the device - 0 - 1GbE and 10GbE (default) - 1 - 2.5GbE and 10GbE - -The MAC address will be determined using the optional properties defined in -ethernet.txt. - -The following optional properties are represented by an array with each -value corresponding to a particular speed. The first array value represents -the setting for the 1GbE speed, the second value for the 2.5GbE speed and -the third value for the 10GbE speed. All three values are required if the -property is used. -- amd,serdes-blwc: Baseline wandering correction enablement - 0 - Off - 1 - On -- amd,serdes-cdr-rate: CDR rate speed selection -- amd,serdes-pq-skew: PQ (data sampling) skew -- amd,serdes-tx-amp: TX amplitude boost -- amd,serdes-dfe-tap-config: DFE taps available to run -- amd,serdes-dfe-tap-enable: DFE taps to enable - -Example: - xgbe@e0700000 { - compatible = "amd,xgbe-seattle-v1a"; - reg = <0 0xe0700000 0 0x80000>, - <0 0xe0780000 0 0x80000>, - <0 0xe1240800 0 0x00400>, - <0 0xe1250000 0 0x00060>, - <0 0xe1250080 0 0x00004>; - interrupt-parent = <&gic>; - interrupts = <0 325 4>, - <0 326 1>, <0 327 1>, <0 328 1>, <0 329 1>, - <0 323 4>; - amd,per-channel-interrupt; - clocks = <&xgbe_dma_clk>, <&xgbe_ptp_clk>; - clock-names = "dma_clk", "ptp_clk"; - phy-mode = "xgmii"; - mac-address = [ 02 a1 a2 a3 a4 a5 ]; - amd,speed-set = <0>; - amd,serdes-blwc = <1>, <1>, <0>; - amd,serdes-cdr-rate = <2>, <2>, <7>; - amd,serdes-pq-skew = <10>, <10>, <30>; - amd,serdes-tx-amp = <15>, <15>, <10>; - amd,serdes-dfe-tap-config = <3>, <3>, <1>; - amd,serdes-dfe-tap-enable = <0>, <0>, <127>; - }; diff --git a/Documentation/devicetree/bindings/net/aspeed,ast2600-mdio.yaml b/Documentation/devicetree/bindings/net/aspeed,ast2600-mdio.yaml index d6ef468495c5..a105dc07ed12 100644 --- a/Documentation/devicetree/bindings/net/aspeed,ast2600-mdio.yaml +++ b/Documentation/devicetree/bindings/net/aspeed,ast2600-mdio.yaml @@ -19,7 +19,12 @@ allOf: properties: compatible: - const: aspeed,ast2600-mdio + oneOf: + - const: aspeed,ast2600-mdio + - items: + - enum: + - aspeed,ast2700-mdio + - const: aspeed,ast2600-mdio reg: maxItems: 1 diff --git a/Documentation/devicetree/bindings/net/bluetooth/marvell,sd8897-bt.yaml b/Documentation/devicetree/bindings/net/bluetooth/marvell,sd8897-bt.yaml new file mode 100644 index 000000000000..a307c64cfa4d --- /dev/null +++ b/Documentation/devicetree/bindings/net/bluetooth/marvell,sd8897-bt.yaml @@ -0,0 +1,79 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/net/bluetooth/marvell,sd8897-bt.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Marvell 8897/8997 (sd8897/sd8997) bluetooth devices (SDIO) + +maintainers: + - Ariel D'Alessandro <ariel.dalessandro@collabora.com> + +allOf: + - $ref: /schemas/net/bluetooth/bluetooth-controller.yaml# + +properties: + compatible: + enum: + - marvell,sd8897-bt + - marvell,sd8997-bt + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + marvell,cal-data: + $ref: /schemas/types.yaml#/definitions/uint8-array + description: + Calibration data downloaded to the device during initialization. + maxItems: 28 + + marvell,wakeup-pin: + $ref: /schemas/types.yaml#/definitions/uint16 + description: + Wakeup pin number of the bluetooth chip. Used by firmware to wakeup host + system. + + marvell,wakeup-gap-ms: + $ref: /schemas/types.yaml#/definitions/uint16 + description: + Wakeup latency of the host platform. Required by the chip sleep feature. + +required: + - compatible + - reg + - interrupts + +additionalProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/irq.h> + + mmc { + vmmc-supply = <&wlan_en_reg>; + bus-width = <4>; + cap-power-off-card; + keep-power-in-suspend; + + #address-cells = <1>; + #size-cells = <0>; + + bluetooth@2 { + compatible = "marvell,sd8897-bt"; + reg = <2>; + interrupt-parent = <&pio>; + interrupts = <119 IRQ_TYPE_LEVEL_LOW>; + + marvell,cal-data = /bits/ 8 < + 0x37 0x01 0x1c 0x00 0xff 0xff 0xff 0xff 0x01 0x7f 0x04 0x02 + 0x00 0x00 0xba 0xce 0xc0 0xc6 0x2d 0x00 0x00 0x00 0x00 0x00 + 0x00 0x00 0xf0 0x00>; + marvell,wakeup-pin = /bits/ 16 <0x0d>; + marvell,wakeup-gap-ms = /bits/ 16 <0x64>; + }; + }; + +... diff --git a/Documentation/devicetree/bindings/net/btusb.txt b/Documentation/devicetree/bindings/net/btusb.txt index f546b1f7dd6d..a68022a57c51 100644 --- a/Documentation/devicetree/bindings/net/btusb.txt +++ b/Documentation/devicetree/bindings/net/btusb.txt @@ -14,7 +14,7 @@ Required properties: Also, vendors that use btusb may have device additional properties, e.g: -Documentation/devicetree/bindings/net/marvell-bt-8xxx.txt +Documentation/devicetree/bindings/net/bluetooth/marvell,sd8897-bt.yaml Optional properties: diff --git a/Documentation/devicetree/bindings/net/can/bosch,m_can.yaml b/Documentation/devicetree/bindings/net/can/bosch,m_can.yaml index 61ef60d8f1c7..2c9d37975bed 100644 --- a/Documentation/devicetree/bindings/net/can/bosch,m_can.yaml +++ b/Documentation/devicetree/bindings/net/can/bosch,m_can.yaml @@ -109,6 +109,26 @@ properties: maximum: 32 minItems: 1 + pinctrl-0: + description: Default pinctrl state + + pinctrl-1: + description: Can be "sleep" or "wakeup" pinctrl state + + pinctrl-2: + description: Can be "sleep" or "wakeup" pinctrl state + + pinctrl-names: + description: + When present should contain at least "default" describing the default pin + states. Other states are "sleep" which describes the pinstate when + sleeping and "wakeup" describing the pins if wakeup is enabled. + minItems: 1 + items: + - const: default + - enum: [ sleep, wakeup ] + - const: wakeup + power-domains: description: Power domain provider node and an args specifier containing @@ -125,6 +145,11 @@ properties: minItems: 1 maxItems: 2 + wakeup-source: + $ref: /schemas/types.yaml#/definitions/phandle-array + description: + List of phandles to system idle states in which mcan can wakeup the system. + required: - compatible - reg diff --git a/Documentation/devicetree/bindings/net/can/microchip,mcp251xfd.yaml b/Documentation/devicetree/bindings/net/can/microchip,mcp251xfd.yaml index c155c9c6db39..2d13638ebc6a 100644 --- a/Documentation/devicetree/bindings/net/can/microchip,mcp251xfd.yaml +++ b/Documentation/devicetree/bindings/net/can/microchip,mcp251xfd.yaml @@ -49,6 +49,11 @@ properties: Must be half or less of "clocks" frequency. maximum: 20000000 + gpio-controller: true + + "#gpio-cells": + const: 2 + required: - compatible - reg diff --git a/Documentation/devicetree/bindings/net/can/microchip,mpfs-can.yaml b/Documentation/devicetree/bindings/net/can/microchip,mpfs-can.yaml index 1219c5cb601f..519a11fbe972 100644 --- a/Documentation/devicetree/bindings/net/can/microchip,mpfs-can.yaml +++ b/Documentation/devicetree/bindings/net/can/microchip,mpfs-can.yaml @@ -32,11 +32,15 @@ properties: - description: AHB peripheral clock - description: CAN bus clock + resets: + maxItems: 1 + required: - compatible - reg - interrupts - clocks + - resets additionalProperties: false @@ -46,6 +50,7 @@ examples: compatible = "microchip,mpfs-can"; reg = <0x2010c000 0x1000>; clocks = <&clkcfg 17>, <&clkcfg 37>; + resets = <&clkcfg 17>; interrupt-parent = <&plic>; interrupts = <56>; }; diff --git a/Documentation/devicetree/bindings/net/cdns,macb.yaml b/Documentation/devicetree/bindings/net/cdns,macb.yaml index 1029786a855c..cb14c35ba996 100644 --- a/Documentation/devicetree/bindings/net/cdns,macb.yaml +++ b/Documentation/devicetree/bindings/net/cdns,macb.yaml @@ -38,7 +38,10 @@ properties: - cdns,sam9x60-macb # Microchip sam9x60 SoC - microchip,mpfs-macb # Microchip PolarFire SoC - const: cdns,macb # Generic - + - items: + - const: microchip,pic64gx-macb # Microchip PIC64GX SoC + - const: microchip,mpfs-macb # Microchip PolarFire SoC + - const: cdns,macb # Generic - items: - enum: - atmel,sama5d3-macb # 10/100Mbit IP on Atmel sama5d3 SoCs @@ -47,18 +50,19 @@ properties: - const: cdns,macb # Generic - enum: - - atmel,sama5d29-gem # GEM XL IP (10/100) on Atmel sama5d29 SoCs - atmel,sama5d2-gem # GEM IP (10/100) on Atmel sama5d2 SoCs + - atmel,sama5d29-gem # GEM XL IP (10/100) on Atmel sama5d29 SoCs - atmel,sama5d3-gem # Gigabit IP on Atmel sama5d3 SoCs - atmel,sama5d4-gem # GEM IP (10/100) on Atmel sama5d4 SoCs + - cdns,emac # Generic + - cdns,gem # Generic + - cdns,macb # Generic - cdns,np4-macb # NP4 SoC devices - microchip,sama7g5-emac # Microchip SAMA7G5 ethernet interface - microchip,sama7g5-gem # Microchip SAMA7G5 gigabit ethernet interface + - mobileye,eyeq5-gem # Mobileye EyeQ5 SoCs - raspberrypi,rp1-gem # Raspberry Pi RP1 gigabit ethernet interface - sifive,fu540-c000-gem # SiFive FU540-C000 SoC - - cdns,emac # Generic - - cdns,gem # Generic - - cdns,macb # Generic - items: - enum: @@ -183,6 +187,15 @@ allOf: reg: maxItems: 1 + - if: + properties: + compatible: + contains: + const: mobileye,eyeq5-gem + then: + required: + - phys + unevaluatedProperties: false examples: diff --git a/Documentation/devicetree/bindings/net/dsa/lantiq,gswip.yaml b/Documentation/devicetree/bindings/net/dsa/lantiq,gswip.yaml index f3154b19af78..205b683849a5 100644 --- a/Documentation/devicetree/bindings/net/dsa/lantiq,gswip.yaml +++ b/Documentation/devicetree/bindings/net/dsa/lantiq,gswip.yaml @@ -4,10 +4,14 @@ $id: http://devicetree.org/schemas/net/dsa/lantiq,gswip.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Lantiq GSWIP Ethernet switches +title: Lantiq GSWIP and MaxLinear GSW1xx Ethernet switches -allOf: - - $ref: dsa.yaml#/$defs/ethernet-ports +description: + Lantiq GSWIP and MaxLinear GSW1xx switches share the same hardware IP. + Lantiq switches are embedded in SoCs and accessed via memory-mapped I/O, + while MaxLinear switches are standalone ICs connected via MDIO. + +$ref: dsa.yaml# maintainers: - Hauke Mehrtens <hauke@hauke-m.de> @@ -18,9 +22,14 @@ properties: - lantiq,xrx200-gswip - lantiq,xrx300-gswip - lantiq,xrx330-gswip + - maxlinear,gsw120 + - maxlinear,gsw125 + - maxlinear,gsw140 + - maxlinear,gsw141 + - maxlinear,gsw145 reg: - minItems: 3 + minItems: 1 maxItems: 3 reg-names: @@ -37,9 +46,6 @@ properties: compatible: const: lantiq,xrx200-mdio - required: - - compatible - gphy-fw: type: object properties: @@ -91,10 +97,63 @@ properties: additionalProperties: false +patternProperties: + "^(ethernet-)?ports$": + type: object + patternProperties: + "^(ethernet-)?port@[0-6]$": + $ref: dsa-port.yaml# + unevaluatedProperties: false + + properties: + maxlinear,rmii-refclk-out: + type: boolean + description: + Configure the RMII reference clock to be a clock output + rather than an input. Only applicable for RMII mode. + tx-internal-delay-ps: + enum: [0, 500, 1000, 1500, 2000, 2500, 3000, 3500] + description: + RGMII TX Clock Delay defined in pico seconds. + The delay lines adjust the MII clock vs. data timing. + If this property is not present the delay is determined by + the interface mode. + rx-internal-delay-ps: + enum: [0, 500, 1000, 1500, 2000, 2500, 3000, 3500] + description: + RGMII RX Clock Delay defined in pico seconds. + The delay lines adjust the MII clock vs. data timing. + If this property is not present the delay is determined by + the interface mode. + required: - compatible - reg +allOf: + - if: + properties: + compatible: + contains: + enum: + - lantiq,xrx200-gswip + - lantiq,xrx300-gswip + - lantiq,xrx330-gswip + then: + properties: + reg: + minItems: 3 + maxItems: 3 + mdio: + required: + - compatible + else: + properties: + reg: + maxItems: 1 + reg-names: false + gphy-fw: false + unevaluatedProperties: false examples: @@ -113,8 +172,10 @@ examples: port@0 { reg = <0>; label = "lan3"; - phy-mode = "rgmii"; + phy-mode = "rgmii-id"; phy-handle = <&phy0>; + tx-internal-delay-ps = <2000>; + rx-internal-delay-ps = <2000>; }; port@1 { @@ -200,3 +261,90 @@ examples: }; }; }; + + - | + #include <dt-bindings/leds/common.h> + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + switch@1f { + compatible = "maxlinear,gsw125"; + reg = <0x1f>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + label = "lan0"; + phy-handle = <&switchphy0>; + phy-mode = "internal"; + }; + + port@1 { + reg = <1>; + label = "lan1"; + phy-handle = <&switchphy1>; + phy-mode = "internal"; + }; + + port@4 { + reg = <4>; + label = "wan"; + phy-mode = "1000base-x"; + managed = "in-band-status"; + }; + + port@5 { + reg = <5>; + phy-mode = "rgmii-id"; + tx-internal-delay-ps = <2000>; + rx-internal-delay-ps = <2000>; + ethernet = <ð0>; + + fixed-link { + speed = <1000>; + full-duplex; + }; + }; + }; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + switchphy0: switchphy@0 { + reg = <0>; + + leds { + #address-cells = <1>; + #size-cells = <0>; + + led@0 { + reg = <0>; + color = <LED_COLOR_ID_GREEN>; + function = LED_FUNCTION_LAN; + }; + }; + }; + + switchphy1: switchphy@1 { + reg = <1>; + + leds { + #address-cells = <1>; + #size-cells = <0>; + + led@0 { + reg = <0>; + color = <LED_COLOR_ID_GREEN>; + function = LED_FUNCTION_LAN; + }; + }; + }; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/net/dsa/motorcomm,yt921x.yaml b/Documentation/devicetree/bindings/net/dsa/motorcomm,yt921x.yaml new file mode 100644 index 000000000000..33a6552e46fc --- /dev/null +++ b/Documentation/devicetree/bindings/net/dsa/motorcomm,yt921x.yaml @@ -0,0 +1,167 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/net/dsa/motorcomm,yt921x.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Motorcomm YT921x Ethernet switch family + +maintainers: + - David Yang <mmyangfl@gmail.com> + +description: | + The Motorcomm YT921x series is a family of Ethernet switches with up to 8 + internal GbE PHYs and up to 2 GMACs, including: + + - YT9215S / YT9215RB / YT9215SC: 5 GbE PHYs (Port 0-4) + 2 GMACs (Port 8-9) + - YT9213NB: 2 GbE PHYs (Port 1/3) + 1 GMAC (Port 9) + - YT9214NB: 2 GbE PHYs (Port 1/3) + 2 GMACs (Port 8-9) + - YT9218N: 8 GbE PHYs (Port 0-7) + - YT9218MB: 8 GbE PHYs (Port 0-7) + 2 GMACs (Port 8-9) + + Any port can be used as the CPU port. + +properties: + compatible: + const: motorcomm,yt9215 + + reg: + enum: [0x0, 0x1d] + + reset-gpios: + maxItems: 1 + + mdio: + $ref: /schemas/net/mdio.yaml# + unevaluatedProperties: false + description: + Internal MDIO bus for the internal GbE PHYs. PHY 0-7 are used for Port + 0-7 respectively. + + mdio-external: + $ref: /schemas/net/mdio.yaml# + unevaluatedProperties: false + description: + External MDIO bus to access external components. External PHYs for GMACs + (Port 8-9) are expected to be connected to the external MDIO bus in + vendor's reference design, but that is not a hard limitation from the + chip. + +required: + - compatible + - reg + +allOf: + - $ref: dsa.yaml#/$defs/ethernet-ports + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/gpio/gpio.h> + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + switch@1d { + compatible = "motorcomm,yt9215"; + /* default 0x1d, alternate 0x0 */ + reg = <0x1d>; + reset-gpios = <&tlmm 39 GPIO_ACTIVE_LOW>; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + sw_phy0: phy@0 { + reg = <0x0>; + }; + + sw_phy1: phy@1 { + reg = <0x1>; + }; + + sw_phy2: phy@2 { + reg = <0x2>; + }; + + sw_phy3: phy@3 { + reg = <0x3>; + }; + + sw_phy4: phy@4 { + reg = <0x4>; + }; + }; + + mdio-external { + #address-cells = <1>; + #size-cells = <0>; + + phy1: phy@b { + reg = <0xb>; + }; + }; + + ethernet-ports { + #address-cells = <1>; + #size-cells = <0>; + + ethernet-port@0 { + reg = <0>; + label = "lan1"; + phy-mode = "internal"; + phy-handle = <&sw_phy0>; + }; + + ethernet-port@1 { + reg = <1>; + label = "lan2"; + phy-mode = "internal"; + phy-handle = <&sw_phy1>; + }; + + ethernet-port@2 { + reg = <2>; + label = "lan3"; + phy-mode = "internal"; + phy-handle = <&sw_phy2>; + }; + + ethernet-port@3 { + reg = <3>; + label = "lan4"; + phy-mode = "internal"; + phy-handle = <&sw_phy3>; + }; + + ethernet-port@4 { + reg = <4>; + label = "lan5"; + phy-mode = "internal"; + phy-handle = <&sw_phy4>; + }; + + /* CPU port */ + ethernet-port@8 { + reg = <8>; + phy-mode = "2500base-x"; + ethernet = <ð0>; + + fixed-link { + speed = <2500>; + full-duplex; + }; + }; + + /* if external phy is connected to a MAC */ + ethernet-port@9 { + reg = <9>; + label = "wan"; + phy-mode = "rgmii-id"; + phy-handle = <&phy1>; + }; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/net/dsa/nxp,sja1105.yaml b/Documentation/devicetree/bindings/net/dsa/nxp,sja1105.yaml index e9dd914b0734..607b7fe8d28e 100644 --- a/Documentation/devicetree/bindings/net/dsa/nxp,sja1105.yaml +++ b/Documentation/devicetree/bindings/net/dsa/nxp,sja1105.yaml @@ -41,6 +41,9 @@ properties: therefore discouraged. maxItems: 1 + clocks: + maxItems: 1 + spi-cpha: true spi-cpol: true diff --git a/Documentation/devicetree/bindings/net/eswin,eic7700-eth.yaml b/Documentation/devicetree/bindings/net/eswin,eic7700-eth.yaml new file mode 100644 index 000000000000..91e8cd1db67b --- /dev/null +++ b/Documentation/devicetree/bindings/net/eswin,eic7700-eth.yaml @@ -0,0 +1,129 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/net/eswin,eic7700-eth.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Eswin EIC7700 SOC Eth Controller + +maintainers: + - Shuang Liang <liangshuang@eswincomputing.com> + - Zhi Li <lizhi2@eswincomputing.com> + - Shangjuan Wei <weishangjuan@eswincomputing.com> + +description: + Platform glue layer implementation for STMMAC Ethernet driver. + +select: + properties: + compatible: + contains: + enum: + - eswin,eic7700-qos-eth + required: + - compatible + +allOf: + - $ref: snps,dwmac.yaml# + +properties: + compatible: + items: + - const: eswin,eic7700-qos-eth + - const: snps,dwmac-5.20 + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + interrupt-names: + const: macirq + + clocks: + items: + - description: AXI clock + - description: Configuration clock + - description: GMAC main clock + - description: Tx clock + + clock-names: + items: + - const: axi + - const: cfg + - const: stmmaceth + - const: tx + + resets: + maxItems: 1 + + reset-names: + items: + - const: stmmaceth + + rx-internal-delay-ps: + enum: [0, 200, 600, 1200, 1600, 1800, 2000, 2200, 2400] + + tx-internal-delay-ps: + enum: [0, 200, 600, 1200, 1600, 1800, 2000, 2200, 2400] + + eswin,hsp-sp-csr: + description: + HSP CSR is to control and get status of different high-speed peripherals + (such as Ethernet, USB, SATA, etc.) via register, which can tune + board-level's parameters of PHY, etc. + $ref: /schemas/types.yaml#/definitions/phandle-array + items: + - items: + - description: Phandle to HSP(High-Speed Peripheral) device + - description: Offset of phy control register for internal + or external clock selection + - description: Offset of AXI clock controller Low-Power request + register + - description: Offset of register controlling TX/RX clock delay + +required: + - compatible + - reg + - clocks + - clock-names + - interrupts + - interrupt-names + - phy-mode + - resets + - reset-names + - rx-internal-delay-ps + - tx-internal-delay-ps + - eswin,hsp-sp-csr + +unevaluatedProperties: false + +examples: + - | + ethernet@50400000 { + compatible = "eswin,eic7700-qos-eth", "snps,dwmac-5.20"; + reg = <0x50400000 0x10000>; + clocks = <&d0_clock 186>, <&d0_clock 171>, <&d0_clock 40>, + <&d0_clock 193>; + clock-names = "axi", "cfg", "stmmaceth", "tx"; + interrupt-parent = <&plic>; + interrupts = <61>; + interrupt-names = "macirq"; + phy-mode = "rgmii-id"; + phy-handle = <&phy0>; + resets = <&reset 95>; + reset-names = "stmmaceth"; + rx-internal-delay-ps = <200>; + tx-internal-delay-ps = <200>; + eswin,hsp-sp-csr = <&hsp_sp_csr 0x100 0x108 0x118>; + snps,axi-config = <&stmmac_axi_setup>; + snps,aal; + snps,fixed-burst; + snps,tso; + stmmac_axi_setup: stmmac-axi-config { + snps,blen = <0 0 0 0 16 8 4>; + snps,rd_osr_lmt = <2>; + snps,wr_osr_lmt = <2>; + }; + }; diff --git a/Documentation/devicetree/bindings/net/ethernet-phy.yaml b/Documentation/devicetree/bindings/net/ethernet-phy.yaml index 2ec2d9fda7e3..bb4c49fc5fd8 100644 --- a/Documentation/devicetree/bindings/net/ethernet-phy.yaml +++ b/Documentation/devicetree/bindings/net/ethernet-phy.yaml @@ -35,9 +35,13 @@ properties: description: PHYs that implement IEEE802.3 clause 45 - pattern: "^ethernet-phy-id[a-f0-9]{4}\\.[a-f0-9]{4}$" description: - If the PHY reports an incorrect ID (or none at all) then the - compatible list may contain an entry with the correct PHY ID - in the above form. + PHYs contain identification registers. These will be read to + identify the PHY. If the PHY reports an incorrect ID, or the + PHY requires a specific initialization sequence (like a + particular order of clocks, resets, power supplies), in + order to be able to read the ID registers, then the + compatible list must contain an entry with the correct PHY + ID in the above form. The first group of digits is the 16 bit Phy Identifier 1 register, this is the chip vendor OUI bits 3:18. The second group of digits is the Phy Identifier 2 register, diff --git a/Documentation/devicetree/bindings/net/fsl,enetc.yaml b/Documentation/devicetree/bindings/net/fsl,enetc.yaml index ca70f0050171..aac20ab72ace 100644 --- a/Documentation/devicetree/bindings/net/fsl,enetc.yaml +++ b/Documentation/devicetree/bindings/net/fsl,enetc.yaml @@ -27,6 +27,7 @@ properties: - const: fsl,enetc - enum: - pci1131,e101 + - pci1131,e110 reg: maxItems: 1 diff --git a/Documentation/devicetree/bindings/net/marvell-bt-8xxx.txt b/Documentation/devicetree/bindings/net/marvell-bt-8xxx.txt deleted file mode 100644 index 957e5e5c2927..000000000000 --- a/Documentation/devicetree/bindings/net/marvell-bt-8xxx.txt +++ /dev/null @@ -1,83 +0,0 @@ -Marvell 8897/8997 (sd8897/sd8997) bluetooth devices (SDIO or USB based) ------- -The 8997 devices supports multiple interfaces. When used on SDIO interfaces, -the btmrvl driver is used and when used on USB interface, the btusb driver is -used. - -Required properties: - - - compatible : should be one of the following: - * "marvell,sd8897-bt" (for SDIO) - * "marvell,sd8997-bt" (for SDIO) - * "usb1286,204e" (for USB) - -Optional properties: - - - marvell,cal-data: Calibration data downloaded to the device during - initialization. This is an array of 28 values(u8). - This is only applicable to SDIO devices. - - - marvell,wakeup-pin: It represents wakeup pin number of the bluetooth chip. - firmware will use the pin to wakeup host system (u16). - - marvell,wakeup-gap-ms: wakeup gap represents wakeup latency of the host - platform. The value will be configured to firmware. This - is needed to work chip's sleep feature as expected (u16). - - interrupt-names: Used only for USB based devices (See below) - - interrupts : specifies the interrupt pin number to the cpu. For SDIO, the - driver will use the first interrupt specified in the interrupt - array. For USB based devices, the driver will use the interrupt - named "wakeup" from the interrupt-names and interrupt arrays. - The driver will request an irq based on this interrupt number. - During system suspend, the irq will be enabled so that the - bluetooth chip can wakeup host platform under certain - conditions. During system resume, the irq will be disabled - to make sure unnecessary interrupt is not received. - -Example: - -IRQ pin 119 is used as system wakeup source interrupt. -wakeup pin 13 and gap 100ms are configured so that firmware can wakeup host -using this device side pin and wakeup latency. - -Example for SDIO device follows (calibration data is also available in -below example). - -&mmc3 { - vmmc-supply = <&wlan_en_reg>; - bus-width = <4>; - cap-power-off-card; - keep-power-in-suspend; - - #address-cells = <1>; - #size-cells = <0>; - btmrvl: bluetooth@2 { - compatible = "marvell,sd8897-bt"; - reg = <2>; - interrupt-parent = <&pio>; - interrupts = <119 IRQ_TYPE_LEVEL_LOW>; - - marvell,cal-data = /bits/ 8 < - 0x37 0x01 0x1c 0x00 0xff 0xff 0xff 0xff 0x01 0x7f 0x04 0x02 - 0x00 0x00 0xba 0xce 0xc0 0xc6 0x2d 0x00 0x00 0x00 0x00 0x00 - 0x00 0x00 0xf0 0x00>; - marvell,wakeup-pin = /bits/ 16 <0x0d>; - marvell,wakeup-gap-ms = /bits/ 16 <0x64>; - }; -}; - -Example for USB device: - -&usb_host1_ohci { - #address-cells = <1>; - #size-cells = <0>; - - mvl_bt1: bt@1 { - compatible = "usb1286,204e"; - reg = <1>; - interrupt-parent = <&gpio0>; - interrupt-names = "wakeup"; - interrupts = <119 IRQ_TYPE_LEVEL_LOW>; - marvell,wakeup-pin = /bits/ 16 <0x0d>; - marvell,wakeup-gap-ms = /bits/ 16 <0x64>; - }; -}; diff --git a/Documentation/devicetree/bindings/net/mediatek,net.yaml b/Documentation/devicetree/bindings/net/mediatek,net.yaml index b45f67f92e80..cc346946291a 100644 --- a/Documentation/devicetree/bindings/net/mediatek,net.yaml +++ b/Documentation/devicetree/bindings/net/mediatek,net.yaml @@ -112,7 +112,7 @@ properties: mediatek,wed: $ref: /schemas/types.yaml#/definitions/phandle-array - minItems: 2 + minItems: 1 maxItems: 2 items: maxItems: 1 @@ -249,6 +249,9 @@ allOf: minItems: 1 maxItems: 1 + mediatek,wed: + minItems: 2 + mediatek,wed-pcie: false else: properties: @@ -338,12 +341,13 @@ allOf: - const: netsys0 - const: netsys1 - mediatek,infracfg: false - mediatek,sgmiisys: minItems: 2 maxItems: 2 + mediatek,wed: + maxItems: 1 + - if: properties: compatible: @@ -385,6 +389,9 @@ allOf: minItems: 2 maxItems: 2 + mediatek,wed: + minItems: 2 + - if: properties: compatible: @@ -429,6 +436,19 @@ allOf: - const: xgp2 - const: xgp3 + mediatek,wed: + minItems: 2 + + - if: + properties: + compatible: + contains: + const: ralink,rt5350-eth + then: + properties: + mediatek,wed: + minItems: 2 + patternProperties: "^mac@[0-2]$": type: object diff --git a/Documentation/devicetree/bindings/net/microchip,sparx5-switch.yaml b/Documentation/devicetree/bindings/net/microchip,sparx5-switch.yaml index 5caa3779660d..5491d0775ede 100644 --- a/Documentation/devicetree/bindings/net/microchip,sparx5-switch.yaml +++ b/Documentation/devicetree/bindings/net/microchip,sparx5-switch.yaml @@ -180,9 +180,9 @@ allOf: then: properties: reg: - minItems: 2 + maxItems: 2 reg-names: - minItems: 2 + maxItems: 2 else: properties: reg: diff --git a/Documentation/devicetree/bindings/net/mscc-phy-vsc8531.txt b/Documentation/devicetree/bindings/net/mscc-phy-vsc8531.txt deleted file mode 100644 index 0a3647fe331b..000000000000 --- a/Documentation/devicetree/bindings/net/mscc-phy-vsc8531.txt +++ /dev/null @@ -1,73 +0,0 @@ -* Microsemi - vsc8531 Giga bit ethernet phy - -Optional properties: -- vsc8531,vddmac : The vddmac in mV. Allowed values is listed - in the first row of Table 1 (below). - This property is only used in combination - with the 'edge-slowdown' property. - Default value is 3300. -- vsc8531,edge-slowdown : % the edge should be slowed down relative to - the fastest possible edge time. - Edge rate sets the drive strength of the MAC - interface output signals. Changing the - drive strength will affect the edge rate of - the output signal. The goal of this setting - is to help reduce electrical emission (EMI) - by being able to reprogram drive strength - and in effect slow down the edge rate if - desired. - To adjust the edge-slowdown, the 'vddmac' - must be specified. Table 1 lists the - supported edge-slowdown values for a given - 'vddmac'. - Default value is 0%. - Ref: Table:1 - Edge rate change (below). -- vsc8531,led-[N]-mode : LED mode. Specify how the LED[N] should behave. - N depends on the number of LEDs supported by a - PHY. - Allowed values are defined in - "include/dt-bindings/net/mscc-phy-vsc8531.h". - Default values are VSC8531_LINK_1000_ACTIVITY (1), - VSC8531_LINK_100_ACTIVITY (2), - VSC8531_LINK_ACTIVITY (0) and - VSC8531_DUPLEX_COLLISION (8). -- load-save-gpios : GPIO used for the load/save operation of the PTP - hardware clock (PHC). - - -Table: 1 - Edge rate change -----------------------------------------------------------------| -| Edge Rate Change (VDDMAC) | -| | -| 3300 mV 2500 mV 1800 mV 1500 mV | -|---------------------------------------------------------------| -| 0% 0% 0% 0% | -| (Fastest) (recommended) (recommended) | -|---------------------------------------------------------------| -| 2% 3% 5% 6% | -|---------------------------------------------------------------| -| 4% 6% 9% 14% | -|---------------------------------------------------------------| -| 7% 10% 16% 21% | -|(recommended) (recommended) | -|---------------------------------------------------------------| -| 10% 14% 23% 29% | -|---------------------------------------------------------------| -| 17% 23% 35% 42% | -|---------------------------------------------------------------| -| 29% 37% 52% 58% | -|---------------------------------------------------------------| -| 53% 63% 76% 77% | -| (slowest) | -|---------------------------------------------------------------| - -Example: - - vsc8531_0: ethernet-phy@0 { - compatible = "ethernet-phy-id0007.0570"; - vsc8531,vddmac = <3300>; - vsc8531,edge-slowdown = <7>; - vsc8531,led-0-mode = <VSC8531_LINK_1000_ACTIVITY>; - vsc8531,led-1-mode = <VSC8531_LINK_100_ACTIVITY>; - load-save-gpios = <&gpio 10 GPIO_ACTIVE_HIGH>; - }; diff --git a/Documentation/devicetree/bindings/net/mscc-phy-vsc8531.yaml b/Documentation/devicetree/bindings/net/mscc-phy-vsc8531.yaml new file mode 100644 index 000000000000..0afbd0ff126f --- /dev/null +++ b/Documentation/devicetree/bindings/net/mscc-phy-vsc8531.yaml @@ -0,0 +1,131 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/net/mscc-phy-vsc8531.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Microsemi VSC8531 Gigabit Ethernet PHY + +maintainers: + - Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> + +description: + The VSC8531 is a Gigabit Ethernet PHY with configurable MAC interface + drive strength and LED modes. + +allOf: + - $ref: ethernet-phy.yaml# + +select: + properties: + compatible: + contains: + enum: + - ethernet-phy-id0007.0570 # VSC8531 + - ethernet-phy-id0007.0772 # VSC8541 + required: + - compatible + +properties: + compatible: + items: + - enum: + - ethernet-phy-id0007.0570 # VSC8531 + - ethernet-phy-id0007.0772 # VSC8541 + - const: ethernet-phy-ieee802.3-c22 + + vsc8531,vddmac: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + The VDDMAC voltage in millivolts. This property is used in combination + with the edge-slowdown property to control the drive strength of the + MAC interface output signals. + enum: [3300, 2500, 1800, 1500] + default: 3300 + + vsc8531,edge-slowdown: + $ref: /schemas/types.yaml#/definitions/uint32 + description: > + Percentage by which the edge rate should be slowed down relative to + the fastest possible edge time. This setting helps reduce electromagnetic + interference (EMI) by adjusting the drive strength of the MAC interface + output signals. Valid values depend on the vddmac voltage setting + according to the edge rate change table in the datasheet. + + - When vsc8531,vddmac = 3300 mV: allowed values are 0, 2, 4, 7, 10, 17, 29, and 53. + (Recommended: 7) + - When vsc8531,vddmac = 2500 mV: allowed values are 0, 3, 6, 10, 14, 23, 37, and 63. + (Recommended: 10) + - When vsc8531,vddmac = 1800 mV: allowed values are 0, 5, 9, 16, 23, 35, 52, and 76. + (Recommended: 0) + - When vsc8531,vddmac = 1500 mV: allowed values are 0, 6, 14, 21, 29, 42, 58, and 77. + (Recommended: 0) + enum: [0, 2, 3, 4, 5, 6, 7, 9, 10, 14, 16, 17, 21, 23, 29, 35, 37, 42, 52, 53, 58, 63, 76, 77] + default: 0 + + vsc8531,led-0-mode: + $ref: /schemas/types.yaml#/definitions/uint32 + description: LED[0] behavior mode. See include/dt-bindings/net/mscc-phy-vsc8531.h + for available modes. + minimum: 0 + maximum: 15 + default: 1 + + vsc8531,led-1-mode: + $ref: /schemas/types.yaml#/definitions/uint32 + description: LED[1] behavior mode. See include/dt-bindings/net/mscc-phy-vsc8531.h + for available modes. + minimum: 0 + maximum: 15 + default: 2 + + vsc8531,led-2-mode: + $ref: /schemas/types.yaml#/definitions/uint32 + description: LED[2] behavior mode. See include/dt-bindings/net/mscc-phy-vsc8531.h + for available modes. + minimum: 0 + maximum: 15 + default: 0 + + vsc8531,led-3-mode: + $ref: /schemas/types.yaml#/definitions/uint32 + description: LED[3] behavior mode. See include/dt-bindings/net/mscc-phy-vsc8531.h + for available modes. + minimum: 0 + maximum: 15 + default: 8 + + load-save-gpios: + description: GPIO phandle used for the load/save operation of the PTP hardware + clock (PHC). + maxItems: 1 + +dependencies: + vsc8531,edge-slowdown: + - vsc8531,vddmac + +required: + - compatible + - reg + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/gpio/gpio.h> + #include <dt-bindings/net/mscc-phy-vsc8531.h> + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethernet-phy@0 { + compatible = "ethernet-phy-id0007.0772", "ethernet-phy-ieee802.3-c22"; + reg = <0>; + vsc8531,vddmac = <3300>; + vsc8531,edge-slowdown = <7>; + vsc8531,led-0-mode = <VSC8531_LINK_1000_ACTIVITY>; + vsc8531,led-1-mode = <VSC8531_LINK_100_ACTIVITY>; + load-save-gpios = <&gpio 10 GPIO_ACTIVE_HIGH>; + }; + }; diff --git a/Documentation/devicetree/bindings/net/nxp,netc-blk-ctrl.yaml b/Documentation/devicetree/bindings/net/nxp,netc-blk-ctrl.yaml index 97389fd5dbbf..deea4fd73d76 100644 --- a/Documentation/devicetree/bindings/net/nxp,netc-blk-ctrl.yaml +++ b/Documentation/devicetree/bindings/net/nxp,netc-blk-ctrl.yaml @@ -21,6 +21,7 @@ maintainers: properties: compatible: enum: + - nxp,imx94-netc-blk-ctrl - nxp,imx95-netc-blk-ctrl reg: diff --git a/Documentation/devicetree/bindings/net/pse-pd/ti,tps23881.yaml b/Documentation/devicetree/bindings/net/pse-pd/ti,tps23881.yaml index bb1ee3398655..0b3803f647b7 100644 --- a/Documentation/devicetree/bindings/net/pse-pd/ti,tps23881.yaml +++ b/Documentation/devicetree/bindings/net/pse-pd/ti,tps23881.yaml @@ -16,6 +16,7 @@ properties: compatible: enum: - ti,tps23881 + - ti,tps23881b reg: maxItems: 1 diff --git a/Documentation/devicetree/bindings/net/qcom,ethqos.yaml b/Documentation/devicetree/bindings/net/qcom,ethqos.yaml index e7ee0d9efed8..423959cb928d 100644 --- a/Documentation/devicetree/bindings/net/qcom,ethqos.yaml +++ b/Documentation/devicetree/bindings/net/qcom,ethqos.yaml @@ -73,6 +73,14 @@ properties: dma-coherent: true + interconnects: + maxItems: 2 + + interconnect-names: + items: + - const: cpu-mac + - const: mac-mem + phys: true phy-names: diff --git a/Documentation/devicetree/bindings/net/rockchip-dwmac.yaml b/Documentation/devicetree/bindings/net/rockchip-dwmac.yaml index 0ac7c4b47d6b..d17112527dab 100644 --- a/Documentation/devicetree/bindings/net/rockchip-dwmac.yaml +++ b/Documentation/devicetree/bindings/net/rockchip-dwmac.yaml @@ -24,6 +24,7 @@ select: - rockchip,rk3366-gmac - rockchip,rk3368-gmac - rockchip,rk3399-gmac + - rockchip,rk3506-gmac - rockchip,rk3528-gmac - rockchip,rk3568-gmac - rockchip,rk3576-gmac @@ -50,6 +51,7 @@ properties: - rockchip,rv1108-gmac - items: - enum: + - rockchip,rk3506-gmac - rockchip,rk3528-gmac - rockchip,rk3568-gmac - rockchip,rk3576-gmac @@ -148,6 +150,7 @@ allOf: compatible: contains: enum: + - rockchip,rk3506-gmac - rockchip,rk3528-gmac then: properties: diff --git a/Documentation/devicetree/bindings/net/snps,dwmac.yaml b/Documentation/devicetree/bindings/net/snps,dwmac.yaml index 658c004e6a5c..dd3c72e8363e 100644 --- a/Documentation/devicetree/bindings/net/snps,dwmac.yaml +++ b/Documentation/devicetree/bindings/net/snps,dwmac.yaml @@ -86,10 +86,14 @@ properties: - rockchip,rk3328-gmac - rockchip,rk3366-gmac - rockchip,rk3368-gmac + - rockchip,rk3399-gmac + - rockchip,rk3506-gmac + - rockchip,rk3528-gmac + - rockchip,rk3568-gmac - rockchip,rk3576-gmac - rockchip,rk3588-gmac - - rockchip,rk3399-gmac - rockchip,rv1108-gmac + - rockchip,rv1126-gmac - snps,dwmac - snps,dwmac-3.40a - snps,dwmac-3.50a diff --git a/Documentation/devicetree/bindings/net/sophgo,sg2044-dwmac.yaml b/Documentation/devicetree/bindings/net/sophgo,sg2044-dwmac.yaml index ce21979a2d9a..e8d3814db0e9 100644 --- a/Documentation/devicetree/bindings/net/sophgo,sg2044-dwmac.yaml +++ b/Documentation/devicetree/bindings/net/sophgo,sg2044-dwmac.yaml @@ -70,6 +70,25 @@ required: allOf: - $ref: snps,dwmac.yaml# + - if: + properties: + compatible: + contains: + const: sophgo,sg2042-dwmac + then: + properties: + phy-mode: + enum: + - rgmii-rxid + - rgmii-id + else: + properties: + phy-mode: + enum: + - rgmii + - rgmii-rxid + - rgmii-txid + - rgmii-id unevaluatedProperties: false diff --git a/Documentation/devicetree/bindings/net/wireless/mediatek,mt76.yaml b/Documentation/devicetree/bindings/net/wireless/mediatek,mt76.yaml index eabceb849537..ae6b97cdc44b 100644 --- a/Documentation/devicetree/bindings/net/wireless/mediatek,mt76.yaml +++ b/Documentation/devicetree/bindings/net/wireless/mediatek,mt76.yaml @@ -151,6 +151,12 @@ properties: - ETSI - JP + country: + $ref: /schemas/types.yaml#/definitions/string + pattern: '^[A-Z]{2}$' + description: + ISO 3166-1 alpha-2 country code for power limits + patternProperties: "^txpower-[256]g$": type: object @@ -210,6 +216,66 @@ properties: minItems: 13 maxItems: 13 + paths-cck: + $ref: /schemas/types.yaml#/definitions/uint8-array + minItems: 4 + maxItems: 4 + description: + 4 half-dBm backoff values (1 - 4 antennas, single spacial + stream) + + paths-ofdm: + $ref: /schemas/types.yaml#/definitions/uint8-array + minItems: 4 + maxItems: 4 + description: + 4 half-dBm backoff values (1 - 4 antennas, single spacial + stream) + + paths-ofdm-bf: + $ref: /schemas/types.yaml#/definitions/uint8-array + minItems: 4 + maxItems: 4 + description: + 4 half-dBm backoff values for beamforming + (1 - 4 antennas, single spacial stream) + + paths-ru: + $ref: /schemas/types.yaml#/definitions/uint8-matrix + description: + Sets of half-dBm backoff values for 802.11ax rates for + 1T1ss (aka 1 transmitting antenna with 1 spacial stream), + 2T1ss, 3T1ss, 4T1ss, 2T2ss, 3T2ss, 4T2ss, 3T3ss, 4T3ss + and 4T4ss. + Each set starts with the number of channel bandwidth or + resource unit settings for which the rate set applies, + followed by 10 power limit values. The order of the + channel resource unit settings is RU26, RU52, RU106, + RU242/SU20, RU484/SU40, RU996/SU80 and RU2x996/SU160. + minItems: 1 + maxItems: 7 + items: + minItems: 11 + maxItems: 11 + + paths-ru-bf: + $ref: /schemas/types.yaml#/definitions/uint8-matrix + description: + Sets of half-dBm backoff (beamforming) values for 802.11ax + rates for 1T1ss (aka 1 transmitting antenna with 1 spacial + stream), 2T1ss, 3T1ss, 4T1ss, 2T2ss, 3T2ss, 4T2ss, 3T3ss, + 4T3ss and 4T4ss. + Each set starts with the number of channel bandwidth or + resource unit settings for which the rate set applies, + followed by 10 power limit values. The order of the + channel resource unit settings is RU26, RU52, RU106, + RU242/SU20, RU484/SU40, RU996/SU80 and RU2x996/SU160. + minItems: 1 + maxItems: 7 + items: + minItems: 11 + maxItems: 11 + txs-delta: $ref: /schemas/types.yaml#/definitions/uint32-array description: |