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-rw-r--r--Documentation/devicetree/bindings/riscv/extensions.yaml19
1 files changed, 11 insertions, 8 deletions
diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Documentation/devicetree/bindings/riscv/extensions.yaml
index 565cb2cbb49b..6a4697b36b8d 100644
--- a/Documentation/devicetree/bindings/riscv/extensions.yaml
+++ b/Documentation/devicetree/bindings/riscv/extensions.yaml
@@ -117,8 +117,9 @@ properties:
- const: h
description:
- The standard H extension for hypervisors as ratified in the 20191213
- version of the privileged ISA specification.
+ The standard H extension for hypervisors as ratified in the RISC-V
+ Instruction Set Manual, Volume II Privileged Architecture,
+ Document Version 20211203.
# multi-letter extensions, sorted alphanumerically
- const: smaia
@@ -202,20 +203,22 @@ properties:
- const: svinval
description:
The standard Svinval supervisor-level extension for fine-grained
- address-translation cache invalidation as ratified in the 20191213
- version of the privileged ISA specification.
+ address-translation cache invalidation as ratified in the RISC-V
+ Instruction Set Manual, Volume II Privileged Architecture,
+ Document Version 20211203.
- const: svnapot
description:
The standard Svnapot supervisor-level extensions for napot
- translation contiguity as ratified in the 20191213 version of the
- privileged ISA specification.
+ translation contiguity as ratified in the RISC-V Instruction Set
+ Manual, Volume II Privileged Architecture, Document Version
+ 20211203.
- const: svpbmt
description:
The standard Svpbmt supervisor-level extensions for page-based
- memory types as ratified in the 20191213 version of the privileged
- ISA specification.
+ memory types as ratified in the RISC-V Instruction Set Manual,
+ Volume II Privileged Architecture, Document Version 20211203.
- const: svrsw60t59b
description: