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-rw-r--r--drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c29
-rw-r--r--drivers/gpu/drm/amd/amdgpu/mes_v12_1.c22
-rw-r--r--drivers/gpu/drm/amd/amdgpu/sdma_v7_1.c5
-rw-r--r--drivers/gpu/drm/amd/amdgpu/soc_v1_0.c29
-rw-r--r--drivers/gpu/drm/amd/amdgpu/soc_v1_0.h2
5 files changed, 45 insertions, 42 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c b/drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c
index c43f9a9fe662..277db5ef9ca7 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c
@@ -59,13 +59,6 @@ MODULE_FIRMWARE("amdgpu/gc_12_1_0_rlc.bin");
(SH_MEM_ALIGNMENT_MODE_UNALIGNED_GFX12_1_0 << SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT) | \
(3 << SH_MEM_CONFIG__INITIAL_INST_PREFETCH__SHIFT))
-#define XCC_REG_RANGE_0_LOW 0x1260 /* XCC gfxdec0 lower Bound */
-#define XCC_REG_RANGE_0_HIGH 0x3C00 /* XCC gfxdec0 upper Bound */
-#define XCC_REG_RANGE_1_LOW 0xA000 /* XCC gfxdec1 lower Bound */
-#define XCC_REG_RANGE_1_HIGH 0x10000 /* XCC gfxdec1 upper Bound */
-#define NORMALIZE_XCC_REG_OFFSET(offset) \
- (offset & 0xFFFF)
-
static void gfx_v12_1_xcc_disable_gpa_mode(struct amdgpu_device *adev, int xcc_id);
static void gfx_v12_1_set_ring_funcs(struct amdgpu_device *adev);
static void gfx_v12_1_set_irq_funcs(struct amdgpu_device *adev);
@@ -228,28 +221,14 @@ static void gfx_v12_1_set_kiq_pm4_funcs(struct amdgpu_device *adev)
adev->gfx.kiq[i].pmf = &gfx_v12_1_kiq_pm4_funcs;
}
-static uint32_t gfx_v12_1_normalize_xcc_reg_offset(uint32_t reg)
-{
- uint32_t normalized_reg = NORMALIZE_XCC_REG_OFFSET(reg);
-
- /* If it is an XCC reg, normalize the reg to keep
- lower 16 bits in local xcc */
-
- if (((normalized_reg >= XCC_REG_RANGE_0_LOW) && (normalized_reg < XCC_REG_RANGE_0_HIGH)) ||
- ((normalized_reg >= XCC_REG_RANGE_1_LOW) && (normalized_reg < XCC_REG_RANGE_1_HIGH)))
- return normalized_reg;
- else
- return reg;
-}
-
static void gfx_v12_1_wait_reg_mem(struct amdgpu_ring *ring, int eng_sel,
int mem_space, int opt, uint32_t addr0,
uint32_t addr1, uint32_t ref,
uint32_t mask, uint32_t inv)
{
if (mem_space == 0) {
- addr0 = gfx_v12_1_normalize_xcc_reg_offset(addr0);
- addr1 = gfx_v12_1_normalize_xcc_reg_offset(addr1);
+ addr0 = soc_v1_0_normalize_xcc_reg_offset(addr0);
+ addr1 = soc_v1_0_normalize_xcc_reg_offset(addr1);
}
amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
@@ -3426,7 +3405,7 @@ static void gfx_v12_1_ring_emit_rreg(struct amdgpu_ring *ring, uint32_t reg,
{
struct amdgpu_device *adev = ring->adev;
- reg = gfx_v12_1_normalize_xcc_reg_offset(reg);
+ reg = soc_v1_0_normalize_xcc_reg_offset(reg);
amdgpu_ring_write(ring, PACKET3(PACKET3_COPY_DATA, 4));
amdgpu_ring_write(ring, 0 | /* src: register*/
@@ -3446,7 +3425,7 @@ static void gfx_v12_1_ring_emit_wreg(struct amdgpu_ring *ring,
{
uint32_t cmd = 0;
- reg = gfx_v12_1_normalize_xcc_reg_offset(reg);
+ reg = soc_v1_0_normalize_xcc_reg_offset(reg);
switch (ring->funcs->type) {
case AMDGPU_RING_TYPE_KIQ:
diff --git a/drivers/gpu/drm/amd/amdgpu/mes_v12_1.c b/drivers/gpu/drm/amd/amdgpu/mes_v12_1.c
index 16e9dd56b0c8..17d7b1731b9c 100644
--- a/drivers/gpu/drm/amd/amdgpu/mes_v12_1.c
+++ b/drivers/gpu/drm/amd/amdgpu/mes_v12_1.c
@@ -45,15 +45,8 @@ static int mes_v12_1_kiq_hw_fini(struct amdgpu_device *adev, uint32_t xcc_id);
#define MES_EOP_SIZE 2048
#define regCP_HQD_IB_CONTROL_MES_12_1_DEFAULT 0x100000
-#define XCC_REG_RANGE_0_LOW 0x1260 /* XCC gfxdec0 lower Bound */
-#define XCC_REG_RANGE_0_HIGH 0x3C00 /* XCC gfxdec0 upper Bound */
-#define XCC_REG_RANGE_1_LOW 0xA000 /* XCC gfxdec1 lower Bound */
-#define XCC_REG_RANGE_1_HIGH 0x10000 /* XCC gfxdec1 upper Bound */
#define XCC_MID_MASK 0x41000000
-#define NORMALIZE_XCC_REG_OFFSET(offset) \
- (offset & 0x3FFFF)
-
static void mes_v12_1_ring_set_wptr(struct amdgpu_ring *ring)
{
struct amdgpu_device *adev = ring->adev;
@@ -508,10 +501,9 @@ static uint32_t mes_v12_1_get_xcc_from_reg(uint32_t reg_offset)
static void mes_v12_1_get_rrmt(uint32_t reg, uint32_t xcc_id,
struct RRMT_OPTION *rrmt_opt)
{
- uint32_t normalized_reg = NORMALIZE_XCC_REG_OFFSET(reg);
+ uint32_t normalized_reg = soc_v1_0_normalize_xcc_reg_offset(reg);
- if (((normalized_reg >= XCC_REG_RANGE_0_LOW) && (normalized_reg < XCC_REG_RANGE_0_HIGH)) ||
- ((normalized_reg >= XCC_REG_RANGE_1_LOW) && (normalized_reg < XCC_REG_RANGE_1_HIGH))) {
+ if (soc_v1_0_normalize_xcc_reg_range(normalized_reg)) {
rrmt_opt->xcd_die_id = mes_v12_1_get_xcc_from_reg(reg);
rrmt_opt->mode = (xcc_id == rrmt_opt->xcd_die_id) ?
MES_RRMT_MODE_LOCAL_XCD : MES_RRMT_MODE_REMOTE_XCD;
@@ -548,7 +540,7 @@ static int mes_v12_1_misc_op(struct amdgpu_mes *mes,
&misc_pkt.read_reg.rrmt_opt);
if (misc_pkt.read_reg.rrmt_opt.mode != MES_RRMT_MODE_REMOTE_MID) {
misc_pkt.read_reg.reg_offset =
- NORMALIZE_XCC_REG_OFFSET(misc_pkt.read_reg.reg_offset);
+ soc_v1_0_normalize_xcc_reg_offset(misc_pkt.read_reg.reg_offset);
}
break;
case MES_MISC_OP_WRITE_REG:
@@ -560,7 +552,7 @@ static int mes_v12_1_misc_op(struct amdgpu_mes *mes,
&misc_pkt.write_reg.rrmt_opt);
if (misc_pkt.write_reg.rrmt_opt.mode != MES_RRMT_MODE_REMOTE_MID) {
misc_pkt.write_reg.reg_offset =
- NORMALIZE_XCC_REG_OFFSET(misc_pkt.write_reg.reg_offset);
+ soc_v1_0_normalize_xcc_reg_offset(misc_pkt.write_reg.reg_offset);
}
break;
case MES_MISC_OP_WRM_REG_WAIT:
@@ -575,7 +567,7 @@ static int mes_v12_1_misc_op(struct amdgpu_mes *mes,
&misc_pkt.wait_reg_mem.rrmt_opt1);
if (misc_pkt.wait_reg_mem.rrmt_opt1.mode != MES_RRMT_MODE_REMOTE_MID) {
misc_pkt.wait_reg_mem.reg_offset1 =
- NORMALIZE_XCC_REG_OFFSET(misc_pkt.wait_reg_mem.reg_offset1);
+ soc_v1_0_normalize_xcc_reg_offset(misc_pkt.wait_reg_mem.reg_offset1);
}
break;
case MES_MISC_OP_WRM_REG_WR_WAIT:
@@ -594,11 +586,11 @@ static int mes_v12_1_misc_op(struct amdgpu_mes *mes,
if (misc_pkt.wait_reg_mem.rrmt_opt1.mode != MES_RRMT_MODE_REMOTE_MID) {
misc_pkt.wait_reg_mem.reg_offset1 =
- NORMALIZE_XCC_REG_OFFSET(misc_pkt.wait_reg_mem.reg_offset1);
+ soc_v1_0_normalize_xcc_reg_offset(misc_pkt.wait_reg_mem.reg_offset1);
}
if (misc_pkt.wait_reg_mem.rrmt_opt2.mode != MES_RRMT_MODE_REMOTE_MID) {
misc_pkt.wait_reg_mem.reg_offset2 =
- NORMALIZE_XCC_REG_OFFSET(misc_pkt.wait_reg_mem.reg_offset2);
+ soc_v1_0_normalize_xcc_reg_offset(misc_pkt.wait_reg_mem.reg_offset2);
}
break;
case MES_MISC_OP_SET_SHADER_DEBUGGER:
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v7_1.c b/drivers/gpu/drm/amd/amdgpu/sdma_v7_1.c
index 6ffe05cc1d1e..5bc45c3e00d1 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v7_1.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v7_1.c
@@ -42,6 +42,7 @@
#include "sdma_v7_1.h"
#include "v12_structs.h"
#include "mes_userqueue.h"
+#include "soc_v1_0.h"
MODULE_FIRMWARE("amdgpu/sdma_7_1_0.bin");
@@ -1220,7 +1221,7 @@ static void sdma_v7_1_ring_emit_wreg(struct amdgpu_ring *ring,
* Use Register WRITE command instead, which OPCODE is same as SRBM WRITE
*/
amdgpu_ring_write(ring, SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_SRBM_WRITE));
- amdgpu_ring_write(ring, reg << 2);
+ amdgpu_ring_write(ring, soc_v1_0_normalize_xcc_reg_offset(reg) << 2);
amdgpu_ring_write(ring, val);
}
@@ -1229,7 +1230,7 @@ static void sdma_v7_1_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg,
{
amdgpu_ring_write(ring, SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_POLL_REGMEM) |
SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* equal */
- amdgpu_ring_write(ring, reg << 2);
+ amdgpu_ring_write(ring, soc_v1_0_normalize_xcc_reg_offset(reg) << 2);
amdgpu_ring_write(ring, 0);
amdgpu_ring_write(ring, val); /* reference */
amdgpu_ring_write(ring, mask); /* mask */
diff --git a/drivers/gpu/drm/amd/amdgpu/soc_v1_0.c b/drivers/gpu/drm/amd/amdgpu/soc_v1_0.c
index 23544cef4101..baa353ee7d1c 100644
--- a/drivers/gpu/drm/amd/amdgpu/soc_v1_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/soc_v1_0.c
@@ -34,6 +34,13 @@
#include "gc/gc_12_1_0_sh_mask.h"
#include "mp/mp_15_0_8_offset.h"
+#define XCC_REG_RANGE_0_LOW 0x1260 /* XCC gfxdec0 lower Bound */
+#define XCC_REG_RANGE_0_HIGH 0x3C00 /* XCC gfxdec0 upper Bound */
+#define XCC_REG_RANGE_1_LOW 0xA000 /* XCC gfxdec1 lower Bound */
+#define XCC_REG_RANGE_1_HIGH 0x10000 /* XCC gfxdec1 upper Bound */
+#define NORMALIZE_XCC_REG_OFFSET(offset) \
+ (offset & 0xFFFF)
+
/* Initialized doorbells for amdgpu including multimedia
* KFD can use all the rest in 2M doorbell bar */
static void soc_v1_0_doorbell_index_init(struct amdgpu_device *adev)
@@ -784,3 +791,25 @@ int soc_v1_0_init_soc_config(struct amdgpu_device *adev)
return 0;
}
+
+bool soc_v1_0_normalize_xcc_reg_range(uint32_t reg)
+{
+ if (((reg >= XCC_REG_RANGE_0_LOW) && (reg < XCC_REG_RANGE_0_HIGH)) ||
+ ((reg >= XCC_REG_RANGE_1_LOW) && (reg < XCC_REG_RANGE_1_HIGH)))
+ return true;
+ else
+ return false;
+}
+
+uint32_t soc_v1_0_normalize_xcc_reg_offset(uint32_t reg)
+{
+ uint32_t normalized_reg = NORMALIZE_XCC_REG_OFFSET(reg);
+
+ /* If it is an XCC reg, normalize the reg to keep
+ * lower 16 bits in local xcc */
+
+ if (soc_v1_0_normalize_xcc_reg_range(normalized_reg))
+ return normalized_reg;
+ else
+ return reg;
+}
diff --git a/drivers/gpu/drm/amd/amdgpu/soc_v1_0.h b/drivers/gpu/drm/amd/amdgpu/soc_v1_0.h
index 23517c3a3d1b..296b653db987 100644
--- a/drivers/gpu/drm/amd/amdgpu/soc_v1_0.h
+++ b/drivers/gpu/drm/amd/amdgpu/soc_v1_0.h
@@ -30,5 +30,7 @@ void soc_v1_0_grbm_select(struct amdgpu_device *adev,
u32 queue, u32 vmid,
int xcc_id);
int soc_v1_0_init_soc_config(struct amdgpu_device *adev);
+bool soc_v1_0_normalize_xcc_reg_range(uint32_t reg);
+uint32_t soc_v1_0_normalize_xcc_reg_offset(uint32_t reg);
#endif
generated by cgit v1.2.3 (git 2.39.0) at 2026-04-20 03:53:12 +0300