diff options
3 files changed, 96 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile index c8194a95681d..75676b908299 100644 --- a/arch/arm64/boot/dts/freescale/Makefile +++ b/arch/arm64/boot/dts/freescale/Makefile @@ -230,11 +230,17 @@ imx8mp-phyboard-pollux-etml1010g3dra-dtbs += imx8mp-phyboard-pollux-rdk.dtb \ imx8mp-phyboard-pollux-etml1010g3dra.dtbo imx8mp-phyboard-pollux-peb-av-10-dtbs += imx8mp-phyboard-pollux-rdk.dtb \ imx8mp-phyboard-pollux-peb-av-10.dtbo +imx8mp-phyboard-pollux-peb-av-10-etml1010g3dra-dtbs += imx8mp-phyboard-pollux-rdk.dtb \ + imx8mp-phyboard-pollux-peb-av-10-etml1010g3dra.dtbo +imx8mp-phyboard-pollux-peb-av-10-ph128800t006-dtbs += imx8mp-phyboard-pollux-rdk.dtb \ + imx8mp-phyboard-pollux-peb-av-10-ph128800t006.dtbo imx8mp-phyboard-pollux-ph128800t006-dtbs += imx8mp-phyboard-pollux-rdk.dtb \ imx8mp-phyboard-pollux-ph128800t006.dtbo imx8mp-phyboard-pollux-rdk-no-eth-dtbs += imx8mp-phyboard-pollux-rdk.dtb imx8mp-phycore-no-eth.dtbo dtb-$(CONFIG_ARCH_MXC) += imx8mp-phyboard-pollux-etml1010g3dra.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-phyboard-pollux-peb-av-10.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8mp-phyboard-pollux-peb-av-10-etml1010g3dra.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8mp-phyboard-pollux-peb-av-10-ph128800t006.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-phyboard-pollux-ph128800t006.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-phyboard-pollux-rdk-no-eth.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-prt8ml.dtb diff --git a/arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-peb-av-10-etml1010g3dra.dtso b/arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-peb-av-10-etml1010g3dra.dtso new file mode 100644 index 000000000000..aceb5b6056ef --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-peb-av-10-etml1010g3dra.dtso @@ -0,0 +1,45 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright (C) 2025 PHYTEC Messtechnik GmbH + */ + +/dts-v1/; +/plugin/; + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/clock/imx8mp-clock.h> +#include "imx8mp-phyboard-pollux-peb-av-10.dtsi" + +&backlight_lvds0 { + brightness-levels = <0 8 16 32 64 128 255>; + default-brightness-level = <8>; + enable-gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>; + num-interpolated-steps = <2>; + pwms = <&pwm4 0 50000 0>; + status = "okay"; +}; + +&lcdif2 { + status = "okay"; +}; + +&lvds_bridge { + assigned-clocks = <&clk IMX8MP_CLK_MEDIA_LDB>, <&clk IMX8MP_VIDEO_PLL1>; + assigned-clock-parents = <&clk IMX8MP_VIDEO_PLL1_OUT>; + /* + * The LVDS panel uses 72.4 MHz pixel clock, set IMX8MP_VIDEO_PLL1 to + * 72.4 * 7 = 506.8 MHz so the LDB serializer and LCDIFv3 scanout + * engine can reach accurate pixel clock of exactly 72.4 MHz. + */ + assigned-clock-rates = <0>, <506800000>; + status = "okay"; +}; + +&panel_lvds0 { + compatible = "edt,etml1010g3dra"; + status = "okay"; +}; + +&pwm4 { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-peb-av-10-ph128800t006.dtso b/arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-peb-av-10-ph128800t006.dtso new file mode 100644 index 000000000000..559286f384be --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-peb-av-10-ph128800t006.dtso @@ -0,0 +1,45 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright (C) 2025 PHYTEC Messtechnik GmbH + */ + +/dts-v1/; +/plugin/; + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/clock/imx8mp-clock.h> +#include "imx8mp-phyboard-pollux-peb-av-10.dtsi" + +&backlight_lvds0 { + brightness-levels = <0 8 16 32 64 128 255>; + default-brightness-level = <8>; + enable-gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>; + num-interpolated-steps = <2>; + pwms = <&pwm4 0 66667 0>; + status = "okay"; +}; + +&lcdif2 { + status = "okay"; +}; + +&lvds_bridge { + assigned-clocks = <&clk IMX8MP_CLK_MEDIA_LDB>, <&clk IMX8MP_VIDEO_PLL1>; + assigned-clock-parents = <&clk IMX8MP_VIDEO_PLL1_OUT>; + /* + * The LVDS panel uses 66.5 MHz pixel clock, set IMX8MP_VIDEO_PLL1 to + * 66.5 * 7 = 465.5 MHz so the LDB serializer and LCDIFv3 scanout + * engine can reach accurate pixel clock of exactly 66.5 MHz. + */ + assigned-clock-rates = <0>, <465500000>; + status = "okay"; +}; + +&panel_lvds0 { + compatible = "powertip,ph128800t006-zhc01"; + status = "okay"; +}; + +&pwm4 { + status = "okay"; +}; |