diff options
| -rw-r--r-- | arch/arm64/boot/dts/freescale/imx93.dtsi | 24 |
1 files changed, 24 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/freescale/imx93.dtsi b/arch/arm64/boot/dts/freescale/imx93.dtsi index 5436b48b30e8..b9abe143cb56 100644 --- a/arch/arm64/boot/dts/freescale/imx93.dtsi +++ b/arch/arm64/boot/dts/freescale/imx93.dtsi @@ -43,6 +43,30 @@ }; }; }; + + soc@0 { + npu@4a900000 { + compatible = "fsl,imx93-npu", "arm,ethos-u65"; + reg = <0x4a900000 0x1000>; + interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>; + power-domains = <&mlmix>; + clocks = <&clk IMX93_CLK_ML>, <&clk IMX93_CLK_ML_APB>; + clock-names = "core", "apb"; + sram = <&sram>; + assigned-clocks = <&clk IMX93_CLK_ML>, <&clk IMX93_CLK_ML_APB>; + assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1>, + <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>; + assigned-clock-rates = <800000000>, <133000000>; + }; + }; + + sram: sram@20480000 { + compatible = "mmio-sram"; + reg = <0x0 0x20480000 0x0 0x18000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x0 0x20480000 0x18000>; + }; }; &aips1 { |