diff options
| -rw-r--r-- | drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c | 20 |
1 files changed, 20 insertions, 0 deletions
diff --git a/drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c b/drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c index 2dad6b7b61b2..3547d91b25d3 100644 --- a/drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c +++ b/drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c @@ -198,6 +198,11 @@ #define RK3568_DSI0_TURNDISABLE BIT(2) #define RK3568_DSI0_FORCERXMODE BIT(0) +#define RK3506_SYS_GRF_SOC_CON6 0x0018 +#define RK3506_DSI_FORCETXSTOPMODE (0xf << 4) +#define RK3506_DSI_TURNDISABLE BIT(2) +#define RK3506_DSI_FORCERXMODE BIT(0) + /* * Note these registers do not appear in the datasheet, they are * however present in the BSP driver which is where these values @@ -1661,6 +1666,18 @@ static const struct rockchip_dw_dsi_chip_data rk3399_chip_data[] = { { /* sentinel */ } }; +static const struct rockchip_dw_dsi_chip_data rk3506_chip_data[] = { + { + .reg = 0xff640000, + .lanecfg1_grf_reg = RK3506_SYS_GRF_SOC_CON6, + .lanecfg1 = (FIELD_PREP_WM16_CONST(RK3506_DSI_TURNDISABLE, 0) | + FIELD_PREP_WM16_CONST(RK3506_DSI_FORCERXMODE, 0) | + FIELD_PREP_WM16_CONST(RK3506_DSI_FORCETXSTOPMODE, 0)), + .max_data_lanes = 2, + }, + { /* sentinel */ } +}; + static const struct rockchip_dw_dsi_chip_data rk3568_chip_data[] = { { .reg = 0xfe060000, @@ -1712,6 +1729,9 @@ static const struct of_device_id dw_mipi_dsi_rockchip_dt_ids[] = { .compatible = "rockchip,rk3399-mipi-dsi", .data = &rk3399_chip_data, }, { + .compatible = "rockchip,rk3506-mipi-dsi", + .data = &rk3506_chip_data, + }, { .compatible = "rockchip,rk3568-mipi-dsi", .data = &rk3568_chip_data, }, { |