diff options
| -rw-r--r-- | arch/arm64/boot/dts/qcom/lemans.dtsi | 105 |
1 files changed, 105 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/qcom/lemans.dtsi b/arch/arm64/boot/dts/qcom/lemans.dtsi index 6788e4d5b413..808827b83553 100644 --- a/arch/arm64/boot/dts/qcom/lemans.dtsi +++ b/arch/arm64/boot/dts/qcom/lemans.dtsi @@ -2985,6 +2985,14 @@ <&apss_funnel1_out>; }; }; + + port@5 { + reg = <5>; + + funnel1_in5: endpoint { + remote-endpoint = <&dlct0_funnel_out>; + }; + }; }; }; @@ -3142,6 +3150,60 @@ }; }; + tpda@4ad3000 { + compatible = "qcom,coresight-tpda", "arm,primecell"; + reg = <0x0 0x4ad3000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@10 { + reg = <16>; + dlct0_tpda_in16: endpoint { + remote-endpoint = <&turing0_funnel_out>; + }; + }; + }; + + out-ports { + port { + dlct0_tpda_out: endpoint { + remote-endpoint = + <&dlct0_funnel_in0>; + }; + }; + }; + + }; + + funnel@4ad4000 { + compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; + reg = <0x0 0x4ad4000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + in-ports { + port { + dlct0_funnel_in0: endpoint { + remote-endpoint = <&dlct0_tpda_out>; + }; + }; + }; + + out-ports { + port { + dlct0_funnel_out: endpoint { + remote-endpoint = <&funnel1_in5>; + }; + }; + }; + }; + funnel@4b04000 { compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; reg = <0x0 0x4b04000 0x0 0x1000>; @@ -3414,6 +3476,35 @@ clock-names = "apb_pclk"; }; + funnel@4b83000 { + compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; + reg = <0x0 0x4b83000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + + turing0_funnel_in1: endpoint { + remote-endpoint = <&turing_llm_tpdm_out>; + }; + }; + }; + + out-ports { + port { + turing0_funnel_out: endpoint { + remote-endpoint = <&dlct0_tpda_in16>; + }; + }; + }; + }; + etm@6040000 { compatible = "arm,primecell"; reg = <0x0 0x6040000 0x0 0x1000>; @@ -8490,6 +8581,20 @@ <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; }; + turing-llm-tpdm { + compatible = "qcom,coresight-static-tpdm"; + + qcom,cmb-element-bits = <32>; + + out-ports { + port { + turing_llm_tpdm_out: endpoint { + remote-endpoint = <&turing0_funnel_in1>; + }; + }; + }; + }; + pcie0: pcie@1c00000 { compatible = "qcom,pcie-sa8775p"; reg = <0x0 0x01c00000 0x0 0x3000>, |