diff options
| -rw-r--r-- | drivers/clk/meson/c3-peripherals.c | 204 | ||||
| -rw-r--r-- | drivers/clk/meson/s4-peripherals.c | 508 |
2 files changed, 103 insertions, 609 deletions
diff --git a/drivers/clk/meson/c3-peripherals.c b/drivers/clk/meson/c3-peripherals.c index 02c9820cd986..fd35f9b79947 100644 --- a/drivers/clk/meson/c3-peripherals.c +++ b/drivers/clk/meson/c3-peripherals.c @@ -48,6 +48,15 @@ #define SPIFC_CLK_CTRL 0x1a0 #define NNA_CLK_CTRL 0x220 +#define C3_COMP_SEL(_name, _reg, _shift, _mask, _pdata) \ + MESON_COMP_SEL(c3_, _name, _reg, _shift, _mask, _pdata, NULL, 0, 0) + +#define C3_COMP_DIV(_name, _reg, _shift, _width) \ + MESON_COMP_DIV(c3_, _name, _reg, _shift, _width, 0, CLK_SET_RATE_PARENT) + +#define C3_COMP_GATE(_name, _reg, _bit) \ + MESON_COMP_GATE(c3_, _name, _reg, _bit, CLK_SET_RATE_PARENT) + static struct clk_regmap c3_rtc_xtal_clkin = { .data = &(struct clk_regmap_gate_data) { .offset = RTC_BY_OSCIN_CTRL0, @@ -512,146 +521,61 @@ static const struct clk_parent_data c3_pwm_parents[] = { { .fw_name = "fdiv3" } }; -#define C3_PWM_CLK_MUX(_name, _reg, _shift) { \ - .data = &(struct clk_regmap_mux_data) { \ - .offset = _reg, \ - .mask = 0x3, \ - .shift = _shift, \ - }, \ - .hw.init = &(struct clk_init_data) { \ - .name = #_name "_sel", \ - .ops = &clk_regmap_mux_ops, \ - .parent_data = c3_pwm_parents, \ - .num_parents = ARRAY_SIZE(c3_pwm_parents), \ - }, \ -} - -#define C3_PWM_CLK_DIV(_name, _reg, _shift) { \ - .data = &(struct clk_regmap_div_data) { \ - .offset = _reg, \ - .shift = _shift, \ - .width = 8, \ - }, \ - .hw.init = &(struct clk_init_data) { \ - .name = #_name "_div", \ - .ops = &clk_regmap_divider_ops, \ - .parent_names = (const char *[]) { #_name "_sel" },\ - .num_parents = 1, \ - .flags = CLK_SET_RATE_PARENT, \ - }, \ -} - -#define C3_PWM_CLK_GATE(_name, _reg, _bit) { \ - .data = &(struct clk_regmap_gate_data) { \ - .offset = _reg, \ - .bit_idx = _bit, \ - }, \ - .hw.init = &(struct clk_init_data) { \ - .name = #_name, \ - .ops = &clk_regmap_gate_ops, \ - .parent_names = (const char *[]) { #_name "_div" },\ - .num_parents = 1, \ - .flags = CLK_SET_RATE_PARENT, \ - }, \ -} - -static struct clk_regmap c3_pwm_a_sel = - C3_PWM_CLK_MUX(pwm_a, PWM_CLK_AB_CTRL, 9); -static struct clk_regmap c3_pwm_a_div = - C3_PWM_CLK_DIV(pwm_a, PWM_CLK_AB_CTRL, 0); -static struct clk_regmap c3_pwm_a = - C3_PWM_CLK_GATE(pwm_a, PWM_CLK_AB_CTRL, 8); - -static struct clk_regmap c3_pwm_b_sel = - C3_PWM_CLK_MUX(pwm_b, PWM_CLK_AB_CTRL, 25); -static struct clk_regmap c3_pwm_b_div = - C3_PWM_CLK_DIV(pwm_b, PWM_CLK_AB_CTRL, 16); -static struct clk_regmap c3_pwm_b = - C3_PWM_CLK_GATE(pwm_b, PWM_CLK_AB_CTRL, 24); - -static struct clk_regmap c3_pwm_c_sel = - C3_PWM_CLK_MUX(pwm_c, PWM_CLK_CD_CTRL, 9); -static struct clk_regmap c3_pwm_c_div = - C3_PWM_CLK_DIV(pwm_c, PWM_CLK_CD_CTRL, 0); -static struct clk_regmap c3_pwm_c = - C3_PWM_CLK_GATE(pwm_c, PWM_CLK_CD_CTRL, 8); - -static struct clk_regmap c3_pwm_d_sel = - C3_PWM_CLK_MUX(pwm_d, PWM_CLK_CD_CTRL, 25); -static struct clk_regmap c3_pwm_d_div = - C3_PWM_CLK_DIV(pwm_d, PWM_CLK_CD_CTRL, 16); -static struct clk_regmap c3_pwm_d = - C3_PWM_CLK_GATE(pwm_d, PWM_CLK_CD_CTRL, 24); - -static struct clk_regmap c3_pwm_e_sel = - C3_PWM_CLK_MUX(pwm_e, PWM_CLK_EF_CTRL, 9); -static struct clk_regmap c3_pwm_e_div = - C3_PWM_CLK_DIV(pwm_e, PWM_CLK_EF_CTRL, 0); -static struct clk_regmap c3_pwm_e = - C3_PWM_CLK_GATE(pwm_e, PWM_CLK_EF_CTRL, 8); - -static struct clk_regmap c3_pwm_f_sel = - C3_PWM_CLK_MUX(pwm_f, PWM_CLK_EF_CTRL, 25); -static struct clk_regmap c3_pwm_f_div = - C3_PWM_CLK_DIV(pwm_f, PWM_CLK_EF_CTRL, 16); -static struct clk_regmap c3_pwm_f = - C3_PWM_CLK_GATE(pwm_f, PWM_CLK_EF_CTRL, 24); - -static struct clk_regmap c3_pwm_g_sel = - C3_PWM_CLK_MUX(pwm_g, PWM_CLK_GH_CTRL, 9); -static struct clk_regmap c3_pwm_g_div = - C3_PWM_CLK_DIV(pwm_g, PWM_CLK_GH_CTRL, 0); -static struct clk_regmap c3_pwm_g = - C3_PWM_CLK_GATE(pwm_g, PWM_CLK_GH_CTRL, 8); - -static struct clk_regmap c3_pwm_h_sel = - C3_PWM_CLK_MUX(pwm_h, PWM_CLK_GH_CTRL, 25); -static struct clk_regmap c3_pwm_h_div = - C3_PWM_CLK_DIV(pwm_h, PWM_CLK_GH_CTRL, 16); -static struct clk_regmap c3_pwm_h = - C3_PWM_CLK_GATE(pwm_h, PWM_CLK_GH_CTRL, 24); - -static struct clk_regmap c3_pwm_i_sel = - C3_PWM_CLK_MUX(pwm_i, PWM_CLK_IJ_CTRL, 9); -static struct clk_regmap c3_pwm_i_div = - C3_PWM_CLK_DIV(pwm_i, PWM_CLK_IJ_CTRL, 0); -static struct clk_regmap c3_pwm_i = - C3_PWM_CLK_GATE(pwm_i, PWM_CLK_IJ_CTRL, 8); - -static struct clk_regmap c3_pwm_j_sel = - C3_PWM_CLK_MUX(pwm_j, PWM_CLK_IJ_CTRL, 25); -static struct clk_regmap c3_pwm_j_div = - C3_PWM_CLK_DIV(pwm_j, PWM_CLK_IJ_CTRL, 16); -static struct clk_regmap c3_pwm_j = - C3_PWM_CLK_GATE(pwm_j, PWM_CLK_IJ_CTRL, 24); - -static struct clk_regmap c3_pwm_k_sel = - C3_PWM_CLK_MUX(pwm_k, PWM_CLK_KL_CTRL, 9); -static struct clk_regmap c3_pwm_k_div = - C3_PWM_CLK_DIV(pwm_k, PWM_CLK_KL_CTRL, 0); -static struct clk_regmap c3_pwm_k = - C3_PWM_CLK_GATE(pwm_k, PWM_CLK_KL_CTRL, 8); - -static struct clk_regmap c3_pwm_l_sel = - C3_PWM_CLK_MUX(pwm_l, PWM_CLK_KL_CTRL, 25); -static struct clk_regmap c3_pwm_l_div = - C3_PWM_CLK_DIV(pwm_l, PWM_CLK_KL_CTRL, 16); -static struct clk_regmap c3_pwm_l = - C3_PWM_CLK_GATE(pwm_l, PWM_CLK_KL_CTRL, 24); - -static struct clk_regmap c3_pwm_m_sel = - C3_PWM_CLK_MUX(pwm_m, PWM_CLK_MN_CTRL, 9); -static struct clk_regmap c3_pwm_m_div = - C3_PWM_CLK_DIV(pwm_m, PWM_CLK_MN_CTRL, 0); -static struct clk_regmap c3_pwm_m = - C3_PWM_CLK_GATE(pwm_m, PWM_CLK_MN_CTRL, 8); - -static struct clk_regmap c3_pwm_n_sel = - C3_PWM_CLK_MUX(pwm_n, PWM_CLK_MN_CTRL, 25); -static struct clk_regmap c3_pwm_n_div = - C3_PWM_CLK_DIV(pwm_n, PWM_CLK_MN_CTRL, 16); -static struct clk_regmap c3_pwm_n = - C3_PWM_CLK_GATE(pwm_n, PWM_CLK_MN_CTRL, 24); +static C3_COMP_SEL(pwm_a, PWM_CLK_AB_CTRL, 9, 0x3, c3_pwm_parents); +static C3_COMP_DIV(pwm_a, PWM_CLK_AB_CTRL, 0, 8); +static C3_COMP_GATE(pwm_a, PWM_CLK_AB_CTRL, 8); + +static C3_COMP_SEL(pwm_b, PWM_CLK_AB_CTRL, 25, 0x3, c3_pwm_parents); +static C3_COMP_DIV(pwm_b, PWM_CLK_AB_CTRL, 16, 8); +static C3_COMP_GATE(pwm_b, PWM_CLK_AB_CTRL, 24); + +static C3_COMP_SEL(pwm_c, PWM_CLK_CD_CTRL, 9, 0x3, c3_pwm_parents); +static C3_COMP_DIV(pwm_c, PWM_CLK_CD_CTRL, 0, 8); +static C3_COMP_GATE(pwm_c, PWM_CLK_CD_CTRL, 8); + +static C3_COMP_SEL(pwm_d, PWM_CLK_CD_CTRL, 25, 0x3, c3_pwm_parents); +static C3_COMP_DIV(pwm_d, PWM_CLK_CD_CTRL, 16, 8); +static C3_COMP_GATE(pwm_d, PWM_CLK_CD_CTRL, 24); + +static C3_COMP_SEL(pwm_e, PWM_CLK_EF_CTRL, 9, 0x3, c3_pwm_parents); +static C3_COMP_DIV(pwm_e, PWM_CLK_EF_CTRL, 0, 8); +static C3_COMP_GATE(pwm_e, PWM_CLK_EF_CTRL, 8); + +static C3_COMP_SEL(pwm_f, PWM_CLK_EF_CTRL, 25, 0x3, c3_pwm_parents); +static C3_COMP_DIV(pwm_f, PWM_CLK_EF_CTRL, 16, 8); +static C3_COMP_GATE(pwm_f, PWM_CLK_EF_CTRL, 24); + +static C3_COMP_SEL(pwm_g, PWM_CLK_GH_CTRL, 9, 0x3, c3_pwm_parents); +static C3_COMP_DIV(pwm_g, PWM_CLK_GH_CTRL, 0, 8); +static C3_COMP_GATE(pwm_g, PWM_CLK_GH_CTRL, 8); + +static C3_COMP_SEL(pwm_h, PWM_CLK_GH_CTRL, 25, 0x3, c3_pwm_parents); +static C3_COMP_DIV(pwm_h, PWM_CLK_GH_CTRL, 16, 8); +static C3_COMP_GATE(pwm_h, PWM_CLK_GH_CTRL, 24); + +static C3_COMP_SEL(pwm_i, PWM_CLK_IJ_CTRL, 9, 0x3, c3_pwm_parents); +static C3_COMP_DIV(pwm_i, PWM_CLK_IJ_CTRL, 0, 8); +static C3_COMP_GATE(pwm_i, PWM_CLK_IJ_CTRL, 8); + +static C3_COMP_SEL(pwm_j, PWM_CLK_IJ_CTRL, 25, 0x3, c3_pwm_parents); +static C3_COMP_DIV(pwm_j, PWM_CLK_IJ_CTRL, 16, 8); +static C3_COMP_GATE(pwm_j, PWM_CLK_IJ_CTRL, 24); + +static C3_COMP_SEL(pwm_k, PWM_CLK_KL_CTRL, 9, 0x3, c3_pwm_parents); +static C3_COMP_DIV(pwm_k, PWM_CLK_KL_CTRL, 0, 8); +static C3_COMP_GATE(pwm_k, PWM_CLK_KL_CTRL, 8); + +static C3_COMP_SEL(pwm_l, PWM_CLK_KL_CTRL, 25, 0x3, c3_pwm_parents); +static C3_COMP_DIV(pwm_l, PWM_CLK_KL_CTRL, 16, 8); +static C3_COMP_GATE(pwm_l, PWM_CLK_KL_CTRL, 24); + +static C3_COMP_SEL(pwm_m, PWM_CLK_MN_CTRL, 9, 0x3, c3_pwm_parents); +static C3_COMP_DIV(pwm_m, PWM_CLK_MN_CTRL, 0, 8); +static C3_COMP_GATE(pwm_m, PWM_CLK_MN_CTRL, 8); + +static C3_COMP_SEL(pwm_n, PWM_CLK_MN_CTRL, 25, 0x3, c3_pwm_parents); +static C3_COMP_DIV(pwm_n, PWM_CLK_MN_CTRL, 16, 8); +static C3_COMP_GATE(pwm_n, PWM_CLK_MN_CTRL, 24); static const struct clk_parent_data c3_spicc_parents[] = { { .fw_name = "oscin" }, diff --git a/drivers/clk/meson/s4-peripherals.c b/drivers/clk/meson/s4-peripherals.c index 3e048e645b08..6d69b132d1e1 100644 --- a/drivers/clk/meson/s4-peripherals.c +++ b/drivers/clk/meson/s4-peripherals.c @@ -62,6 +62,15 @@ #define CLKCTRL_PWM_CLK_IJ_CTRL 0x190 #define CLKCTRL_DEMOD_CLK_CTRL 0x200 +#define S4_COMP_SEL(_name, _reg, _shift, _mask, _pdata) \ + MESON_COMP_SEL(s4_, _name, _reg, _shift, _mask, _pdata, NULL, 0, 0) + +#define S4_COMP_DIV(_name, _reg, _shift, _width) \ + MESON_COMP_DIV(s4_, _name, _reg, _shift, _width, 0, CLK_SET_RATE_PARENT) + +#define S4_COMP_GATE(_name, _reg, _bit) \ + MESON_COMP_GATE(s4_, _name, _reg, _bit, CLK_SET_RATE_PARENT) + static struct clk_regmap s4_rtc_32k_by_oscin_clkin = { .data = &(struct clk_regmap_gate_data){ .offset = CLKCTRL_RTC_BY_OSCIN_CTRL0, @@ -2559,484 +2568,45 @@ static const struct clk_parent_data s4_pwm_parents[] = { { .fw_name = "fclk_div3", }, }; -static struct clk_regmap s4_pwm_a_sel = { - .data = &(struct clk_regmap_mux_data) { - .offset = CLKCTRL_PWM_CLK_AB_CTRL, - .mask = 0x3, - .shift = 9, - }, - .hw.init = &(struct clk_init_data){ - .name = "pwm_a_sel", - .ops = &clk_regmap_mux_ops, - .parent_data = s4_pwm_parents, - .num_parents = ARRAY_SIZE(s4_pwm_parents), - .flags = 0, - }, -}; - -static struct clk_regmap s4_pwm_a_div = { - .data = &(struct clk_regmap_div_data) { - .offset = CLKCTRL_PWM_CLK_AB_CTRL, - .shift = 0, - .width = 8, - }, - .hw.init = &(struct clk_init_data){ - .name = "pwm_a_div", - .ops = &clk_regmap_divider_ops, - .parent_hws = (const struct clk_hw *[]) { - &s4_pwm_a_sel.hw - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - }, -}; - -static struct clk_regmap s4_pwm_a = { - .data = &(struct clk_regmap_gate_data) { - .offset = CLKCTRL_PWM_CLK_AB_CTRL, - .bit_idx = 8, - }, - .hw.init = &(struct clk_init_data){ - .name = "pwm_a_gate", - .ops = &clk_regmap_gate_ops, - .parent_hws = (const struct clk_hw *[]) { - &s4_pwm_a_div.hw - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - }, -}; - -static struct clk_regmap s4_pwm_b_sel = { - .data = &(struct clk_regmap_mux_data) { - .offset = CLKCTRL_PWM_CLK_AB_CTRL, - .mask = 0x3, - .shift = 25, - }, - .hw.init = &(struct clk_init_data){ - .name = "pwm_b_sel", - .ops = &clk_regmap_mux_ops, - .parent_data = s4_pwm_parents, - .num_parents = ARRAY_SIZE(s4_pwm_parents), - .flags = 0, - }, -}; - -static struct clk_regmap s4_pwm_b_div = { - .data = &(struct clk_regmap_div_data) { - .offset = CLKCTRL_PWM_CLK_AB_CTRL, - .shift = 16, - .width = 8, - }, - .hw.init = &(struct clk_init_data){ - .name = "pwm_b_div", - .ops = &clk_regmap_divider_ops, - .parent_hws = (const struct clk_hw *[]) { - &s4_pwm_b_sel.hw - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - }, -}; - -static struct clk_regmap s4_pwm_b = { - .data = &(struct clk_regmap_gate_data) { - .offset = CLKCTRL_PWM_CLK_AB_CTRL, - .bit_idx = 24, - }, - .hw.init = &(struct clk_init_data){ - .name = "pwm_b", - .ops = &clk_regmap_gate_ops, - .parent_hws = (const struct clk_hw *[]) { - &s4_pwm_b_div.hw - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - }, -}; - -static struct clk_regmap s4_pwm_c_sel = { - .data = &(struct clk_regmap_mux_data) { - .offset = CLKCTRL_PWM_CLK_CD_CTRL, - .mask = 0x3, - .shift = 9, - }, - .hw.init = &(struct clk_init_data){ - .name = "pwm_c_mux", - .ops = &clk_regmap_mux_ops, - .parent_data = s4_pwm_parents, - .num_parents = ARRAY_SIZE(s4_pwm_parents), - .flags = 0, - }, -}; - -static struct clk_regmap s4_pwm_c_div = { - .data = &(struct clk_regmap_div_data) { - .offset = CLKCTRL_PWM_CLK_CD_CTRL, - .shift = 0, - .width = 8, - }, - .hw.init = &(struct clk_init_data){ - .name = "pwm_c_div", - .ops = &clk_regmap_divider_ops, - .parent_hws = (const struct clk_hw *[]) { - &s4_pwm_c_sel.hw - }, - .num_parents = 1, - }, -}; - -static struct clk_regmap s4_pwm_c = { - .data = &(struct clk_regmap_gate_data) { - .offset = CLKCTRL_PWM_CLK_CD_CTRL, - .bit_idx = 8, - }, - .hw.init = &(struct clk_init_data){ - .name = "pwm_c", - .ops = &clk_regmap_gate_ops, - .parent_hws = (const struct clk_hw *[]) { - &s4_pwm_c_div.hw - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - }, -}; - -static struct clk_regmap s4_pwm_d_sel = { - .data = &(struct clk_regmap_mux_data) { - .offset = CLKCTRL_PWM_CLK_CD_CTRL, - .mask = 0x3, - .shift = 25, - }, - .hw.init = &(struct clk_init_data){ - .name = "pwm_d_sel", - .ops = &clk_regmap_mux_ops, - .parent_data = s4_pwm_parents, - .num_parents = ARRAY_SIZE(s4_pwm_parents), - .flags = 0, - }, -}; - -static struct clk_regmap s4_pwm_d_div = { - .data = &(struct clk_regmap_div_data) { - .offset = CLKCTRL_PWM_CLK_CD_CTRL, - .shift = 16, - .width = 8, - }, - .hw.init = &(struct clk_init_data){ - .name = "pwm_d_div", - .ops = &clk_regmap_divider_ops, - .parent_hws = (const struct clk_hw *[]) { - &s4_pwm_d_sel.hw - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - }, -}; - -static struct clk_regmap s4_pwm_d = { - .data = &(struct clk_regmap_gate_data) { - .offset = CLKCTRL_PWM_CLK_CD_CTRL, - .bit_idx = 24, - }, - .hw.init = &(struct clk_init_data){ - .name = "pwm_d", - .ops = &clk_regmap_gate_ops, - .parent_hws = (const struct clk_hw *[]) { - &s4_pwm_d_div.hw - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - }, -}; - -static struct clk_regmap s4_pwm_e_sel = { - .data = &(struct clk_regmap_mux_data) { - .offset = CLKCTRL_PWM_CLK_EF_CTRL, - .mask = 0x3, - .shift = 9, - }, - .hw.init = &(struct clk_init_data){ - .name = "pwm_e_sel", - .ops = &clk_regmap_mux_ops, - .parent_data = s4_pwm_parents, - .num_parents = ARRAY_SIZE(s4_pwm_parents), - .flags = 0, - }, -}; - -static struct clk_regmap s4_pwm_e_div = { - .data = &(struct clk_regmap_div_data) { - .offset = CLKCTRL_PWM_CLK_EF_CTRL, - .shift = 0, - .width = 8, - }, - .hw.init = &(struct clk_init_data){ - .name = "pwm_e_div", - .ops = &clk_regmap_divider_ops, - .parent_hws = (const struct clk_hw *[]) { - &s4_pwm_e_sel.hw - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - }, -}; - -static struct clk_regmap s4_pwm_e = { - .data = &(struct clk_regmap_gate_data) { - .offset = CLKCTRL_PWM_CLK_EF_CTRL, - .bit_idx = 8, - }, - .hw.init = &(struct clk_init_data){ - .name = "pwm_e", - .ops = &clk_regmap_gate_ops, - .parent_hws = (const struct clk_hw *[]) { - &s4_pwm_e_div.hw - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - }, -}; - -static struct clk_regmap s4_pwm_f_sel = { - .data = &(struct clk_regmap_mux_data) { - .offset = CLKCTRL_PWM_CLK_EF_CTRL, - .mask = 0x3, - .shift = 25, - }, - .hw.init = &(struct clk_init_data){ - .name = "pwm_f_sel", - .ops = &clk_regmap_mux_ops, - .parent_data = s4_pwm_parents, - .num_parents = ARRAY_SIZE(s4_pwm_parents), - .flags = 0, - }, -}; +static S4_COMP_SEL(pwm_a, CLKCTRL_PWM_CLK_AB_CTRL, 9, 0x3, s4_pwm_parents); +static S4_COMP_DIV(pwm_a, CLKCTRL_PWM_CLK_AB_CTRL, 0, 8); +static S4_COMP_GATE(pwm_a, CLKCTRL_PWM_CLK_AB_CTRL, 8); -static struct clk_regmap s4_pwm_f_div = { - .data = &(struct clk_regmap_div_data) { - .offset = CLKCTRL_PWM_CLK_EF_CTRL, - .shift = 16, - .width = 8, - }, - .hw.init = &(struct clk_init_data){ - .name = "pwm_f_div", - .ops = &clk_regmap_divider_ops, - .parent_hws = (const struct clk_hw *[]) { - &s4_pwm_f_sel.hw - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - }, -}; +static S4_COMP_SEL(pwm_b, CLKCTRL_PWM_CLK_AB_CTRL, 25, 0x3, s4_pwm_parents); +static S4_COMP_DIV(pwm_b, CLKCTRL_PWM_CLK_AB_CTRL, 16, 8); +static S4_COMP_GATE(pwm_b, CLKCTRL_PWM_CLK_AB_CTRL, 24); -static struct clk_regmap s4_pwm_f = { - .data = &(struct clk_regmap_gate_data) { - .offset = CLKCTRL_PWM_CLK_EF_CTRL, - .bit_idx = 24, - }, - .hw.init = &(struct clk_init_data){ - .name = "pwm_f", - .ops = &clk_regmap_gate_ops, - .parent_hws = (const struct clk_hw *[]) { - &s4_pwm_f_div.hw - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - }, -}; +static S4_COMP_SEL(pwm_c, CLKCTRL_PWM_CLK_CD_CTRL, 9, 0x3, s4_pwm_parents); +static S4_COMP_DIV(pwm_c, CLKCTRL_PWM_CLK_CD_CTRL, 0, 8); +static S4_COMP_GATE(pwm_c, CLKCTRL_PWM_CLK_CD_CTRL, 8); -static struct clk_regmap s4_pwm_g_sel = { - .data = &(struct clk_regmap_mux_data) { - .offset = CLKCTRL_PWM_CLK_GH_CTRL, - .mask = 0x3, - .shift = 9, - }, - .hw.init = &(struct clk_init_data){ - .name = "pwm_g_sel", - .ops = &clk_regmap_mux_ops, - .parent_data = s4_pwm_parents, - .num_parents = ARRAY_SIZE(s4_pwm_parents), - .flags = 0, - }, -}; +static S4_COMP_SEL(pwm_d, CLKCTRL_PWM_CLK_CD_CTRL, 25, 0x3, s4_pwm_parents); +static S4_COMP_DIV(pwm_d, CLKCTRL_PWM_CLK_CD_CTRL, 16, 8); +static S4_COMP_GATE(pwm_d, CLKCTRL_PWM_CLK_CD_CTRL, 24); -static struct clk_regmap s4_pwm_g_div = { - .data = &(struct clk_regmap_div_data) { - .offset = CLKCTRL_PWM_CLK_GH_CTRL, - .shift = 0, - .width = 8, - }, - .hw.init = &(struct clk_init_data){ - .name = "pwm_g_div", - .ops = &clk_regmap_divider_ops, - .parent_hws = (const struct clk_hw *[]) { - &s4_pwm_g_sel.hw - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - }, -}; +static S4_COMP_SEL(pwm_e, CLKCTRL_PWM_CLK_EF_CTRL, 9, 0x3, s4_pwm_parents); +static S4_COMP_DIV(pwm_e, CLKCTRL_PWM_CLK_EF_CTRL, 0, 8); +static S4_COMP_GATE(pwm_e, CLKCTRL_PWM_CLK_EF_CTRL, 8); -static struct clk_regmap s4_pwm_g = { - .data = &(struct clk_regmap_gate_data) { - .offset = CLKCTRL_PWM_CLK_GH_CTRL, - .bit_idx = 8, - }, - .hw.init = &(struct clk_init_data){ - .name = "pwm_g", - .ops = &clk_regmap_gate_ops, - .parent_hws = (const struct clk_hw *[]) { - &s4_pwm_g_div.hw - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - }, -}; +static S4_COMP_SEL(pwm_f, CLKCTRL_PWM_CLK_EF_CTRL, 25, 0x3, s4_pwm_parents); +static S4_COMP_DIV(pwm_f, CLKCTRL_PWM_CLK_EF_CTRL, 16, 8); +static S4_COMP_GATE(pwm_f, CLKCTRL_PWM_CLK_EF_CTRL, 24); -static struct clk_regmap s4_pwm_h_sel = { - .data = &(struct clk_regmap_mux_data) { - .offset = CLKCTRL_PWM_CLK_GH_CTRL, - .mask = 0x3, - .shift = 25, - }, - .hw.init = &(struct clk_init_data){ - .name = "pwm_h_sel", - .ops = &clk_regmap_mux_ops, - .parent_data = s4_pwm_parents, - .num_parents = ARRAY_SIZE(s4_pwm_parents), - .flags = 0, - }, -}; +static S4_COMP_SEL(pwm_g, CLKCTRL_PWM_CLK_GH_CTRL, 9, 0x3, s4_pwm_parents); +static S4_COMP_DIV(pwm_g, CLKCTRL_PWM_CLK_GH_CTRL, 0, 8); +static S4_COMP_GATE(pwm_g, CLKCTRL_PWM_CLK_GH_CTRL, 8); -static struct clk_regmap s4_pwm_h_div = { - .data = &(struct clk_regmap_div_data) { - .offset = CLKCTRL_PWM_CLK_GH_CTRL, - .shift = 16, - .width = 8, - }, - .hw.init = &(struct clk_init_data){ - .name = "pwm_h_div", - .ops = &clk_regmap_divider_ops, - .parent_hws = (const struct clk_hw *[]) { - &s4_pwm_h_sel.hw - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - }, -}; +static S4_COMP_SEL(pwm_h, CLKCTRL_PWM_CLK_GH_CTRL, 25, 0x3, s4_pwm_parents); +static S4_COMP_DIV(pwm_h, CLKCTRL_PWM_CLK_GH_CTRL, 16, 8); +static S4_COMP_GATE(pwm_h, CLKCTRL_PWM_CLK_GH_CTRL, 24); -static struct clk_regmap s4_pwm_h = { - .data = &(struct clk_regmap_gate_data) { - .offset = CLKCTRL_PWM_CLK_GH_CTRL, - .bit_idx = 24, - }, - .hw.init = &(struct clk_init_data){ - .name = "pwm_h", - .ops = &clk_regmap_gate_ops, - .parent_hws = (const struct clk_hw *[]) { - &s4_pwm_h_div.hw - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - }, -}; +static S4_COMP_SEL(pwm_i, CLKCTRL_PWM_CLK_IJ_CTRL, 9, 0x3, s4_pwm_parents); +static S4_COMP_DIV(pwm_i, CLKCTRL_PWM_CLK_IJ_CTRL, 0, 8); +static S4_COMP_GATE(pwm_i, CLKCTRL_PWM_CLK_IJ_CTRL, 8); -static struct clk_regmap s4_pwm_i_sel = { - .data = &(struct clk_regmap_mux_data) { - .offset = CLKCTRL_PWM_CLK_IJ_CTRL, - .mask = 0x3, - .shift = 9, - }, - .hw.init = &(struct clk_init_data){ - .name = "pwm_i_sel", - .ops = &clk_regmap_mux_ops, - .parent_data = s4_pwm_parents, - .num_parents = ARRAY_SIZE(s4_pwm_parents), - .flags = 0, - }, -}; - -static struct clk_regmap s4_pwm_i_div = { - .data = &(struct clk_regmap_div_data) { - .offset = CLKCTRL_PWM_CLK_IJ_CTRL, - .shift = 0, - .width = 8, - }, - .hw.init = &(struct clk_init_data){ - .name = "pwm_i_div", - .ops = &clk_regmap_divider_ops, - .parent_hws = (const struct clk_hw *[]) { - &s4_pwm_i_sel.hw - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - }, -}; - -static struct clk_regmap s4_pwm_i = { - .data = &(struct clk_regmap_gate_data) { - .offset = CLKCTRL_PWM_CLK_IJ_CTRL, - .bit_idx = 8, - }, - .hw.init = &(struct clk_init_data){ - .name = "pwm_i", - .ops = &clk_regmap_gate_ops, - .parent_hws = (const struct clk_hw *[]) { - &s4_pwm_i_div.hw - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - }, -}; - -static struct clk_regmap s4_pwm_j_sel = { - .data = &(struct clk_regmap_mux_data) { - .offset = CLKCTRL_PWM_CLK_IJ_CTRL, - .mask = 0x3, - .shift = 25, - }, - .hw.init = &(struct clk_init_data){ - .name = "pwm_j_sel", - .ops = &clk_regmap_mux_ops, - .parent_data = s4_pwm_parents, - .num_parents = ARRAY_SIZE(s4_pwm_parents), - .flags = 0, - }, -}; - -static struct clk_regmap s4_pwm_j_div = { - .data = &(struct clk_regmap_div_data) { - .offset = CLKCTRL_PWM_CLK_IJ_CTRL, - .shift = 16, - .width = 8, - }, - .hw.init = &(struct clk_init_data){ - .name = "pwm_j_div", - .ops = &clk_regmap_divider_ops, - .parent_hws = (const struct clk_hw *[]) { - &s4_pwm_j_sel.hw - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - }, -}; - -static struct clk_regmap s4_pwm_j = { - .data = &(struct clk_regmap_gate_data) { - .offset = CLKCTRL_PWM_CLK_IJ_CTRL, - .bit_idx = 24, - }, - .hw.init = &(struct clk_init_data){ - .name = "pwm_j", - .ops = &clk_regmap_gate_ops, - .parent_hws = (const struct clk_hw *[]) { - &s4_pwm_j_div.hw - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - }, -}; +static S4_COMP_SEL(pwm_j, CLKCTRL_PWM_CLK_IJ_CTRL, 25, 0x3, s4_pwm_parents); +static S4_COMP_DIV(pwm_j, CLKCTRL_PWM_CLK_IJ_CTRL, 16, 8); +static S4_COMP_GATE(pwm_j, CLKCTRL_PWM_CLK_IJ_CTRL, 24); static struct clk_regmap s4_saradc_sel = { .data = &(struct clk_regmap_mux_data) { |