diff options
| -rw-r--r-- | Documentation/devicetree/bindings/sound/renesas,fsi.yaml | 60 |
1 files changed, 55 insertions, 5 deletions
diff --git a/Documentation/devicetree/bindings/sound/renesas,fsi.yaml b/Documentation/devicetree/bindings/sound/renesas,fsi.yaml index df91991699a7..803945b7f82f 100644 --- a/Documentation/devicetree/bindings/sound/renesas,fsi.yaml +++ b/Documentation/devicetree/bindings/sound/renesas,fsi.yaml @@ -9,9 +9,6 @@ title: Renesas FIFO-buffered Serial Interface (FSI) maintainers: - Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> -allOf: - - $ref: dai-common.yaml# - properties: $nodename: pattern: "^sound@.*" @@ -38,7 +35,32 @@ properties: maxItems: 1 clocks: - maxItems: 1 + minItems: 1 + items: + - description: Main FSI module clock + - description: | + SPU bus/bridge clock. On R8A7740, this clock must be enabled to allow + register access as the FSI block is connected behind the SPU bus. + - description: CPG DIV6 functional clocks for FSI port A + - description: CPG DIV6 functional clocks for FSI port B + - description: FSI dividers for port A used for audio clock generation + - description: FSI dividers for port B used for audio clock generation + - description: External clock inputs for FSI port A provided by the board + - description: External clock inputs for FSI port B provided by the board + + clock-names: + minItems: 1 + maxItems: 8 + items: + enum: + - fck # Main FSI module clock + - spu # optional SPU bus/bridge clock + - icka # optional CPG DIV6 functional clocks for FSI port A + - ickb # optional CPG DIV6 functional clocks for FSI port B + - diva # optional FSI dividers for port A used for audio clock generation + - divb # optional FSI dividers for port B used for audio clock generation + - xcka # optional External clock inputs for FSI port A provided by the board + - xckb # optional External clock inputs for FSI port B provided by the board power-domains: maxItems: 1 @@ -69,6 +91,30 @@ required: unevaluatedProperties: false +allOf: + - $ref: dai-common.yaml# + - if: + properties: + compatible: + contains: + const: renesas,fsi2-r8a7740 + then: + required: + - clock-names + + properties: + clock-names: + minItems: 2 + items: + - const: fck + - const: spu + - enum: [icka, ickb, diva, divb, xcka, xckb] + - enum: [icka, ickb, diva, divb, xcka, xckb] + - enum: [icka, ickb, diva, divb, xcka, xckb] + - enum: [icka, ickb, diva, divb, xcka, xckb] + - enum: [icka, ickb, diva, divb, xcka, xckb] + - enum: [icka, ickb, diva, divb, xcka, xckb] + examples: - | #include <dt-bindings/clock/r8a7740-clock.h> @@ -77,7 +123,11 @@ examples: compatible = "renesas,fsi2-r8a7740", "renesas,sh_fsi2"; reg = <0xfe1f0000 0x400>; interrupts = <GIC_SPI 9 0x4>; - clocks = <&mstp3_clks R8A7740_CLK_FSI>; + clocks = <&mstp3_clks R8A7740_CLK_FSI>, <&spu_clk>, + <&fsia_clk>, <&fsiack_clk>, <&fsidiva_clk>, + <&fsib_clk>, <&fsibck_clk>, <&fsidivb_clk>; + clock-names = "fck", "spu", "icka", "xcka", "diva", + "ickb", "xckb", "divb"; power-domains = <&pd_a4mp>; #sound-dai-cells = <1>; |