diff options
| -rw-r--r-- | drivers/gpu/drm/xe/xe_guc.c | 11 |
1 files changed, 7 insertions, 4 deletions
diff --git a/drivers/gpu/drm/xe/xe_guc.c b/drivers/gpu/drm/xe/xe_guc.c index ecc843d91f62..04a57af85d9e 100644 --- a/drivers/gpu/drm/xe/xe_guc.c +++ b/drivers/gpu/drm/xe/xe_guc.c @@ -532,12 +532,15 @@ static void guc_enable_irq(struct xe_guc *guc) REG_FIELD_PREP(ENGINE0_MASK, GUC_INTR_GUC2HOST) : REG_FIELD_PREP(ENGINE1_MASK, GUC_INTR_GUC2HOST); + /* Primary GuC and media GuC share a single enable bit */ xe_mmio_write32(gt, GUC_SG_INTR_ENABLE, REG_FIELD_PREP(ENGINE1_MASK, GUC_INTR_GUC2HOST)); - if (xe_gt_is_media_type(gt)) - xe_mmio_rmw32(gt, GUC_SG_INTR_MASK, events, 0); - else - xe_mmio_write32(gt, GUC_SG_INTR_MASK, ~events); + + /* + * There are separate mask bits for primary and media GuCs, so use + * a RMW operation to avoid clobbering the other GuC's setting. + */ + xe_mmio_rmw32(gt, GUC_SG_INTR_MASK, events, 0); } int xe_guc_enable_communication(struct xe_guc *guc) |