diff options
| -rw-r--r-- | drivers/pci/controller/pcie-rzg3s-host.c | 37 |
1 files changed, 9 insertions, 28 deletions
diff --git a/drivers/pci/controller/pcie-rzg3s-host.c b/drivers/pci/controller/pcie-rzg3s-host.c index 83ec66a70823..2809112e6317 100644 --- a/drivers/pci/controller/pcie-rzg3s-host.c +++ b/drivers/pci/controller/pcie-rzg3s-host.c @@ -73,6 +73,7 @@ #define RZG3S_PCI_PINTRCVIE_INTX(i) BIT(i) #define RZG3S_PCI_PINTRCVIE_MSI BIT(4) +/* Register is R/W1C, it doesn't require locking. */ #define RZG3S_PCI_PINTRCVIS 0x114 #define RZG3S_PCI_PINTRCVIS_INTX(i) BIT(i) #define RZG3S_PCI_PINTRCVIS_MSI BIT(4) @@ -114,6 +115,8 @@ #define RZG3S_PCI_MSIRE_ENA BIT(0) #define RZG3S_PCI_MSIRM(id) (0x608 + (id) * 0x10) + +/* Register is R/W1C, it doesn't require locking. */ #define RZG3S_PCI_MSIRS(id) (0x60c + (id) * 0x10) #define RZG3S_PCI_AWBASEL(id) (0x1000 + (id) * 0x20) @@ -439,28 +442,9 @@ static void __iomem *rzg3s_pcie_root_map_bus(struct pci_bus *bus, return host->pcie + where; } -/* Serialized by 'pci_lock' */ -static int rzg3s_pcie_root_write(struct pci_bus *bus, unsigned int devfn, - int where, int size, u32 val) -{ - struct rzg3s_pcie_host *host = bus->sysdata; - int ret; - - /* Enable access control to the CFGU */ - writel_relaxed(RZG3S_PCI_PERM_CFG_HWINIT_EN, - host->axi + RZG3S_PCI_PERM); - - ret = pci_generic_config_write(bus, devfn, where, size, val); - - /* Disable access control to the CFGU */ - writel_relaxed(0, host->axi + RZG3S_PCI_PERM); - - return ret; -} - static struct pci_ops rzg3s_pcie_root_ops = { .read = pci_generic_config_read, - .write = rzg3s_pcie_root_write, + .write = pci_generic_config_write, .map_bus = rzg3s_pcie_root_map_bus, }; @@ -526,8 +510,6 @@ static void rzg3s_pcie_msi_irq_ack(struct irq_data *d) u8 reg_bit = d->hwirq % RZG3S_PCI_MSI_INT_PER_REG; u8 reg_id = d->hwirq / RZG3S_PCI_MSI_INT_PER_REG; - guard(raw_spinlock_irqsave)(&host->hw_lock); - writel_relaxed(BIT(reg_bit), host->axi + RZG3S_PCI_MSIRS(reg_id)); } @@ -859,8 +841,6 @@ static void rzg3s_pcie_intx_irq_ack(struct irq_data *d) { struct rzg3s_pcie_host *host = irq_data_get_irq_chip_data(d); - guard(raw_spinlock_irqsave)(&host->hw_lock); - rzg3s_pcie_update_bits(host->axi, RZG3S_PCI_PINTRCVIS, RZG3S_PCI_PINTRCVIS_INTX(d->hwirq), RZG3S_PCI_PINTRCVIS_INTX(d->hwirq)); @@ -1065,14 +1045,14 @@ static int rzg3s_pcie_config_init(struct rzg3s_pcie_host *host) writel_relaxed(0xffffffff, host->pcie + RZG3S_PCI_CFG_BARMSK00L); writel_relaxed(0xffffffff, host->pcie + RZG3S_PCI_CFG_BARMSK00U); + /* Disable access control to the CFGU */ + writel_relaxed(0, host->axi + RZG3S_PCI_PERM); + /* Update bus info */ writeb_relaxed(primary_bus, host->pcie + PCI_PRIMARY_BUS); writeb_relaxed(secondary_bus, host->pcie + PCI_SECONDARY_BUS); writeb_relaxed(subordinate_bus, host->pcie + PCI_SUBORDINATE_BUS); - /* Disable access control to the CFGU */ - writel_relaxed(0, host->axi + RZG3S_PCI_PERM); - return 0; } @@ -1162,7 +1142,8 @@ static int rzg3s_pcie_resets_prepare_and_get(struct rzg3s_pcie_host *host) static int rzg3s_pcie_host_parse_port(struct rzg3s_pcie_host *host) { - struct device_node *of_port = of_get_next_child(host->dev->of_node, NULL); + struct device_node *of_port __free(device_node) = + of_get_next_child(host->dev->of_node, NULL); struct rzg3s_pcie_port *port = &host->port; int ret; |