diff options
| -rw-r--r-- | arch/arm64/boot/dts/renesas/r9a09g087.dtsi | 31 |
1 files changed, 31 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/renesas/r9a09g087.dtsi b/arch/arm64/boot/dts/renesas/r9a09g087.dtsi index bb46a936eb4d..4a1339561332 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g087.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a09g087.dtsi @@ -260,6 +260,37 @@ status = "disabled"; }; + canfd: can@80040000 { + compatible = "renesas,r9a09g087-canfd", "renesas,r9a09g077-canfd"; + reg = <0 0x80040000 0 0x20000>; + interrupts = <GIC_SPI 633 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 632 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 627 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 628 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 626 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 630 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 631 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 629 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "g_err", "g_recc", + "ch0_err", "ch0_rec", "ch0_trx", + "ch1_err", "ch1_rec", "ch1_trx"; + clocks = <&cpg CPG_MOD 310>, + <&cpg CPG_CORE R9A09G087_CLK_PCLKH>, + <&cpg CPG_CORE R9A09G087_PCLKCAN>; + clock-names = "fck", "ram_clk", "can_clk"; + assigned-clocks = <&cpg CPG_CORE R9A09G087_PCLKCAN>; + assigned-clock-rates = <80000000>; + power-domains = <&cpg>; + status = "disabled"; + + channel0 { + status = "disabled"; + }; + channel1 { + status = "disabled"; + }; + }; + wdt0: watchdog@80082000 { compatible = "renesas,r9a09g087-wdt", "renesas,r9a09g077-wdt"; reg = <0 0x80082000 0 0x400>, |