diff options
| -rw-r--r-- | arch/arm64/boot/dts/rockchip/rk3588-base.dtsi | 64 | ||||
| -rw-r--r-- | arch/arm64/boot/dts/rockchip/rk3588-extra.dtsi | 30 |
2 files changed, 94 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi index a81a193fa136..dd1d26be391c 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi @@ -1320,6 +1320,21 @@ status = "disabled"; }; + spdif_tx2: spdif-tx@fddb0000 { + compatible = "rockchip,rk3588-spdif", "rockchip,rk3568-spdif"; + reg = <0x0 0xfddb0000 0x0 0x1000>; + assigned-clock-parents = <&cru PLL_AUPLL>; + assigned-clocks = <&cru CLK_SPDIF2_DP0_SRC>; + clock-names = "mclk", "hclk"; + clocks = <&cru MCLK_SPDIF2>, <&cru HCLK_SPDIF2_DP0>; + dma-names = "tx"; + dmas = <&dmac1 6>; + interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH 0>; + power-domains = <&power RK3588_PD_VO0>; + #sound-dai-cells = <0>; + status = "disabled"; + }; + i2s4_8ch: i2s@fddc0000 { compatible = "rockchip,rk3588-i2s-tdm"; reg = <0x0 0xfddc0000 0x0 0x1000>; @@ -1337,6 +1352,21 @@ status = "disabled"; }; + spdif_tx3: spdif-tx@fdde0000 { + compatible = "rockchip,rk3588-spdif", "rockchip,rk3568-spdif"; + reg = <0x0 0xfdde0000 0x0 0x1000>; + assigned-clock-parents = <&cru PLL_AUPLL>; + assigned-clocks = <&cru CLK_SPDIF3_SRC>; + clock-names = "mclk", "hclk"; + clocks = <&cru MCLK_SPDIF3>, <&cru HCLK_SPDIF3>; + dma-names = "tx"; + dmas = <&dmac1 7>; + interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH 0>; + power-domains = <&power RK3588_PD_VO1>; + #sound-dai-cells = <0>; + status = "disabled"; + }; + i2s5_8ch: i2s@fddf0000 { compatible = "rockchip,rk3588-i2s-tdm"; reg = <0x0 0xfddf0000 0x0 0x1000>; @@ -2018,6 +2048,40 @@ status = "disabled"; }; + spdif_tx0: spdif-tx@fe4e0000 { + compatible = "rockchip,rk3588-spdif", "rockchip,rk3568-spdif"; + reg = <0x0 0xfe4e0000 0x0 0x1000>; + assigned-clock-parents = <&cru PLL_AUPLL>; + assigned-clocks = <&cru CLK_SPDIF0_SRC>; + clock-names = "mclk", "hclk"; + clocks = <&cru MCLK_SPDIF0>, <&cru HCLK_SPDIF0>; + dma-names = "tx"; + dmas = <&dmac0 5>; + interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH 0>; + pinctrl-0 = <&spdif0m0_tx>; + pinctrl-names = "default"; + power-domains = <&power RK3588_PD_AUDIO>; + #sound-dai-cells = <0>; + status = "disabled"; + }; + + spdif_tx1: spdif-tx@fe4f0000 { + compatible = "rockchip,rk3588-spdif", "rockchip,rk3568-spdif"; + reg = <0x0 0xfe4f0000 0x0 0x1000>; + assigned-clock-parents = <&cru PLL_AUPLL>; + assigned-clocks = <&cru CLK_SPDIF1_SRC>; + clock-names = "mclk", "hclk"; + clocks = <&cru MCLK_SPDIF1>, <&cru HCLK_SPDIF1>; + dma-names = "tx"; + dmas = <&dmac1 5>; + interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH 0>; + pinctrl-0 = <&spdif1m0_tx>; + pinctrl-names = "default"; + power-domains = <&power RK3588_PD_AUDIO>; + #sound-dai-cells = <0>; + status = "disabled"; + }; + gic: interrupt-controller@fe600000 { compatible = "arm,gic-v3"; reg = <0x0 0xfe600000 0 0x10000>, /* GICD */ diff --git a/arch/arm64/boot/dts/rockchip/rk3588-extra.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-extra.dtsi index 4a950907ea6f..505cdd7b518e 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-extra.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588-extra.dtsi @@ -67,6 +67,21 @@ }; }; + spdif_tx5: spdif-tx@fddb8000 { + compatible = "rockchip,rk3588-spdif", "rockchip,rk3568-spdif"; + reg = <0x0 0xfddb8000 0x0 0x1000>; + assigned-clock-parents = <&cru PLL_AUPLL>; + assigned-clocks = <&cru CLK_SPDIF5_DP1_SRC>; + clock-names = "mclk", "hclk"; + clocks = <&cru MCLK_SPDIF5>, <&cru HCLK_SPDIF5_DP1>; + dma-names = "tx"; + dmas = <&dmac1 22>; + interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH 0>; + power-domains = <&power RK3588_PD_VO0>; + #sound-dai-cells = <0>; + status = "disabled"; + }; + i2s8_8ch: i2s@fddc8000 { compatible = "rockchip,rk3588-i2s-tdm"; reg = <0x0 0xfddc8000 0x0 0x1000>; @@ -84,6 +99,21 @@ status = "disabled"; }; + spdif_tx4: spdif-tx@fdde8000 { + compatible = "rockchip,rk3588-spdif", "rockchip,rk3568-spdif"; + reg = <0x0 0xfdde8000 0x0 0x1000>; + assigned-clock-parents = <&cru PLL_AUPLL>; + assigned-clocks = <&cru CLK_SPDIF4_SRC>; + clock-names = "mclk", "hclk"; + clocks = <&cru MCLK_SPDIF4>, <&cru HCLK_SPDIF4>; + dma-names = "tx"; + dmas = <&dmac1 8>; + interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH 0>; + power-domains = <&power RK3588_PD_VO1>; + #sound-dai-cells = <0>; + status = "disabled"; + }; + i2s6_8ch: i2s@fddf4000 { compatible = "rockchip,rk3588-i2s-tdm"; reg = <0x0 0xfddf4000 0x0 0x1000>; |