diff options
| -rw-r--r-- | drivers/phy/freescale/phy-fsl-lynx-core.c | 27 |
1 files changed, 26 insertions, 1 deletions
diff --git a/drivers/phy/freescale/phy-fsl-lynx-core.c b/drivers/phy/freescale/phy-fsl-lynx-core.c index f49d594622cb..802e32dc6dca 100644 --- a/drivers/phy/freescale/phy-fsl-lynx-core.c +++ b/drivers/phy/freescale/phy-fsl-lynx-core.c @@ -40,6 +40,27 @@ enum lynx_lane_mode phy_interface_to_lane_mode(phy_interface_t intf) } EXPORT_SYMBOL_NS_GPL(phy_interface_to_lane_mode, "PHY_FSL_LYNX"); +/* By default, assume that if we know how to get the PCCR register and + * protocol converter for a lane, that protocol is supported. + */ +static bool lynx_lane_supports_mode_default(struct lynx_lane *lane, + enum lynx_lane_mode mode) +{ + struct lynx_priv *priv = lane->priv; + struct lynx_pccr pccr; + + if (!priv->info->get_pccr || !priv->info->get_pcvt_offset) + return false; + + if (priv->info->get_pccr(mode, lane->id, &pccr) < 0) + return false; + + if (priv->info->get_pcvt_offset(lane->id, mode) < 0) + return false; + + return true; +} + /* A lane mode is supported if we have a PLL that can provide its required * clock net, and if there is a protocol converter for that mode on that lane. */ @@ -48,8 +69,12 @@ bool lynx_lane_supports_mode(struct lynx_lane *lane, enum lynx_lane_mode mode) struct lynx_priv *priv = lane->priv; int i; - if (!priv->info->lane_supports_mode(lane->id, mode)) + if (priv->info->lane_supports_mode) { + if (!priv->info->lane_supports_mode(lane->id, mode)) + return false; + } else if (!lynx_lane_supports_mode_default(lane, mode)) { return false; + } for (i = 0; i < LYNX_NUM_PLL; i++) { if (!priv->pll[i].enabled) |