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| author | Stephen Boyd <sboyd@kernel.org> | 2025-03-11 20:56:09 +0300 |
|---|---|---|
| committer | Stephen Boyd <sboyd@kernel.org> | 2025-03-11 20:56:09 +0300 |
| commit | ca1de84113b09dfcd902b7e2f557ee0eefc75214 (patch) | |
| tree | 252f3cdd1c40fcd741a4432450e2aeebfab52a1d /tools/testing/selftests/net/lib/py/utils.py | |
| parent | 2014c95afecee3e76ca4a56956a936e23283f05b (diff) | |
| parent | f863d4cc79a7e2f8c734d1fac84dc275805f41c7 (diff) | |
| download | linux-ca1de84113b09dfcd902b7e2f557ee0eefc75214.tar.xz | |
Merge tag 'v6.15-rockchip-clk1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into clk-rockchip
Pull Rockchip clk driver updates from Heiko Stuebner:
- New clock controller drivers for Rockchip rk3528 and rk3562
- Fix a parent for Rockchip rk3328 clk_ref_usb3otg
- Add camera interface clocks for Rockchip rk3188
* tag 'v6.15-rockchip-clk1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip:
clk: rockchip: Add clock controller for the RK3562
dt-bindings: clock: Add RK3562 cru
clk: rockchip: rk3528: Add reset lookup table
clk: rockchip: Add clock controller driver for RK3528 SoC
clk: rockchip: Add PLL flag ROCKCHIP_PLL_FIXED_MODE
dt-bindings: clock: Document clock and reset unit of RK3528
clk: rockchip: rk3328: fix wrong clk_ref_usb3otg parent
clk: rockchip: rk3568: mark hclk_vi as critical
clk: rockchip: rk3188: use PCLK_CIF0/1 clock IDs on RK3066
dt-bindings: clock: rk3188-common: add PCLK_CIF0/PCLK_CIF1
Diffstat (limited to 'tools/testing/selftests/net/lib/py/utils.py')
0 files changed, 0 insertions, 0 deletions