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| author | Fabrizio Castro <fabrizio.castro.jz@renesas.com> | 2025-02-20 18:01:04 +0300 |
|---|---|---|
| committer | Geert Uytterhoeven <geert+renesas@glider.be> | 2025-03-04 11:04:20 +0300 |
| commit | 4d6952981244d1e455e2469cfd93e3b5eaddc4a7 (patch) | |
| tree | 9ced7a466be9c88e0c2318506628569d37166731 /tools/testing/selftests/net/lib/py/utils.py | |
| parent | 9b12504e8c8c2f1f7e5f16afdd829603dd0c9508 (diff) | |
| download | linux-4d6952981244d1e455e2469cfd93e3b5eaddc4a7.tar.xz | |
clk: renesas: r9a09g057: Add entries for the DMACs
Add clock and reset entries for the Renesas RZ/V2H(P) DMAC IPs.
Signed-off-by: Fabrizio Castro <fabrizio.castro.jz@renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20250220150110.738619-2-fabrizio.castro.jz@renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Diffstat (limited to 'tools/testing/selftests/net/lib/py/utils.py')
0 files changed, 0 insertions, 0 deletions