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| author | Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> | 2025-09-04 18:55:06 +0300 |
|---|---|---|
| committer | Geert Uytterhoeven <geert+renesas@glider.be> | 2025-09-11 21:23:15 +0300 |
| commit | 23c59916bafa396265c12112bc94f373ad560b16 (patch) | |
| tree | 5b6d571e61d766fa711376e2107f23a92bf563eb /tools/testing/selftests/net/lib/py/utils.py | |
| parent | 09e3a0467375fe7bb19c66eaf5ad3edfd90ea16c (diff) | |
| download | linux-23c59916bafa396265c12112bc94f373ad560b16.tar.xz | |
clk: renesas: r9a09g057: Add clock and reset entries for I3C
Add module clock entries for the I3C controller on the RZ/V2H(P)
(R9A09G057) SoC.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://patch.msgid.link/20250904155507.245744-2-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Diffstat (limited to 'tools/testing/selftests/net/lib/py/utils.py')
0 files changed, 0 insertions, 0 deletions