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authorXiang Liu <xiang.liu@amd.com>2025-03-21 15:47:23 +0300
committerAlex Deucher <alexander.deucher@amd.com>2025-03-27 00:44:27 +0300
commitf3f05a0ec584855c53f2d95024e23259f3ee101d (patch)
treeb5ff3f79915614f0b1721332d92fb312263da20a /tools/testing/selftests/bpf/prog_tests/prog_array_init.c
parent704bc361e3a4ead1c0eb40acc255b636b788dc89 (diff)
downloadlinux-f3f05a0ec584855c53f2d95024e23259f3ee101d.tar.xz
drm/amdgpu: Use correct gfx deferred error count
In the case of parsing GFX deferred error from SMU corrected error channel, the error count should be set to 1 instead of parsing from MISC0 register, which is 0. Signed-off-by: Xiang Liu <xiang.liu@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'tools/testing/selftests/bpf/prog_tests/prog_array_init.c')
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