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| author | Ian Rogers <irogers@google.com> | 2025-12-02 19:53:35 +0300 |
|---|---|---|
| committer | Namhyung Kim <namhyung@kernel.org> | 2025-12-03 22:02:06 +0300 |
| commit | 1d341e543f1cdbca4fbf00f55f005e937762f7a3 (patch) | |
| tree | ec75c51202030628c97e612580859af5cab931b7 /tools/perf | |
| parent | 5a341ccbdda901b5b492101bc98e443540f5598d (diff) | |
| download | linux-1d341e543f1cdbca4fbf00f55f005e937762f7a3.tar.xz | |
perf vendor events intel: Update graniterapids events from 1.15 to 1.16
The updated events were published in:
https://github.com/intel/perfmon/commit/b4acc3fd520eb098db41083010b65b75ae906c96
Signed-off-by: Ian Rogers <irogers@google.com>
Reviewed-by: Dapeng Mi <dapeng1.mi@linux.intel.com>
Signed-off-by: Namhyung Kim <namhyung@kernel.org>
Diffstat (limited to 'tools/perf')
| -rw-r--r-- | tools/perf/pmu-events/arch/x86/graniterapids/cache.json | 4 | ||||
| -rw-r--r-- | tools/perf/pmu-events/arch/x86/graniterapids/uncore-cache.json | 9 | ||||
| -rw-r--r-- | tools/perf/pmu-events/arch/x86/mapfile.csv | 2 |
3 files changed, 12 insertions, 3 deletions
diff --git a/tools/perf/pmu-events/arch/x86/graniterapids/cache.json b/tools/perf/pmu-events/arch/x86/graniterapids/cache.json index 7edb73583b07..db28866444b6 100644 --- a/tools/perf/pmu-events/arch/x86/graniterapids/cache.json +++ b/tools/perf/pmu-events/arch/x86/graniterapids/cache.json @@ -488,12 +488,12 @@ "UMask": "0x2" }, { - "BriefDescription": "Retired load instructions which data sources missed L3 but serviced from local dram", + "BriefDescription": "Retired load instructions which data sources missed L3 but serviced from dram homed in the local socket", "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xd3", "EventName": "MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM", - "PublicDescription": "Retired load instructions which data sources missed L3 but serviced from local DRAM. Available PDIST counters: 0", + "PublicDescription": "Retired load instructions which data sources missed L3 but serviced from DRAM homed in the local socket. Available PDIST counters: 0", "RetirementLatencyMax": 4146, "RetirementLatencyMean": 115.83, "RetirementLatencyMin": 0, diff --git a/tools/perf/pmu-events/arch/x86/graniterapids/uncore-cache.json b/tools/perf/pmu-events/arch/x86/graniterapids/uncore-cache.json index b782f6d54fc2..721fc42797b1 100644 --- a/tools/perf/pmu-events/arch/x86/graniterapids/uncore-cache.json +++ b/tools/perf/pmu-events/arch/x86/graniterapids/uncore-cache.json @@ -10,6 +10,15 @@ "Unit": "CHACMS" }, { + "BriefDescription": "UNC_CHACMS_DISTRESS_ASSERTED", + "Counter": "0,1,2,3", + "EventCode": "0x35", + "EventName": "UNC_CHACMS_DISTRESS_ASSERTED", + "PerPkg": "1", + "PortMask": "0x000", + "Unit": "CHACMS" + }, + { "BriefDescription": "Counts the number of cycles FAST trigger is received from the global FAST distress wire.", "Counter": "0,1,2,3", "EventCode": "0x34", diff --git a/tools/perf/pmu-events/arch/x86/mapfile.csv b/tools/perf/pmu-events/arch/x86/mapfile.csv index c25f718cfd54..521718b0d4e0 100644 --- a/tools/perf/pmu-events/arch/x86/mapfile.csv +++ b/tools/perf/pmu-events/arch/x86/mapfile.csv @@ -13,7 +13,7 @@ GenuineIntel-6-CF,v1.20,emeraldrapids,core GenuineIntel-6-5[CF],v13,goldmont,core GenuineIntel-6-7A,v1.01,goldmontplus,core GenuineIntel-6-B6,v1.10,grandridge,core -GenuineIntel-6-A[DE],v1.15,graniterapids,core +GenuineIntel-6-A[DE],v1.16,graniterapids,core GenuineIntel-6-(3C|45|46),v36,haswell,core GenuineIntel-6-3F,v29,haswellx,core GenuineIntel-6-7[DE],v1.24,icelake,core |