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authorRyder Lee <ryder.lee@mediatek.com>2018-04-17 15:30:27 +0300
committerStephen Boyd <sboyd@kernel.org>2018-05-16 01:17:49 +0300
commitbf61099a21f5a4da3b0551a88d7b3551fa4fff08 (patch)
tree7b38a09f9ea99c75d8c76fb1cb1008dbe599a791 /tools/perf/util/scripting-engines/trace-event-python.c
parent60cc43fc888428bb2f18f08997432d426a243338 (diff)
downloadlinux-bf61099a21f5a4da3b0551a88d7b3551fa4fff08.tar.xz
clk: mediatek: correct the clocks for MT2701 HDMI PHY module
The hdmitx_dig_cts clock signal is not a child of clk26m, and the actual output of the PLL block is derived from the tvdpll via a configurable PLL post-divider. It is used as the PLL reference input to the HDMI PHY module. Fixes: e9862118272a ("clk: mediatek: Add MT2701 clock support") Signed-off-by: Chunhui Dai <chunhui.dai@mediatek.com> Signed-off-by: Ryder Lee <ryder.lee@mediatek.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Diffstat (limited to 'tools/perf/util/scripting-engines/trace-event-python.c')
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