diff options
| author | Mukesh Ojha <quic_mojha@quicinc.com> | 2024-03-21 20:37:35 +0300 |
|---|---|---|
| committer | Bjorn Andersson <andersson@kernel.org> | 2024-04-21 20:08:30 +0300 |
| commit | b9718298e028f9edbe0fcdf48c02a1c355409410 (patch) | |
| tree | 2bb3bef11d141831188868524890fe73e6c59b64 /tools/perf/scripts/python | |
| parent | 2e4955167ec5c04534cebea9e8273a907e7a75e1 (diff) | |
| download | linux-b9718298e028f9edbe0fcdf48c02a1c355409410.tar.xz | |
firmware: qcom: scm: Modify only the download bits in TCSR register
Crashdump collection is done based on DLOAD bits of TCSR register.
To retain other bits, scm driver need to read the register and
modify only the DLOAD bits, as other bits in TCSR may have their
own significance.
Co-developed-by: Poovendhan Selvaraj <quic_poovendh@quicinc.com>
Signed-off-by: Poovendhan Selvaraj <quic_poovendh@quicinc.com>
Signed-off-by: Mukesh Ojha <quic_mojha@quicinc.com>
Tested-by: Kathiravan Thirumoorthy <quic_kathirav@quicinc.com> # IPQ9574 and IPQ5332
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Elliot Berman <quic_eberman@quicinc.com>
Link: https://lore.kernel.org/r/1711042655-31948-1-git-send-email-quic_mojha@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Diffstat (limited to 'tools/perf/scripts/python')
0 files changed, 0 insertions, 0 deletions