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| author | Marek Vasut <marex@denx.de> | 2024-06-25 15:02:33 +0300 |
|---|---|---|
| committer | Robert Foss <rfoss@kernel.org> | 2024-06-27 12:07:07 +0300 |
| commit | 9c433c87e81c2dfc005b72b9fe822b065ffa044e (patch) | |
| tree | f7507fba190fac87554ec6a81d545ddf17eeecf9 /tools/perf/scripts/python | |
| parent | 3f13e53bcf30583ab804d94973157d515330dd6e (diff) | |
| download | linux-9c433c87e81c2dfc005b72b9fe822b065ffa044e.tar.xz | |
drm/bridge: tc358767: Set LSCLK divider for SYSCLK to 1
The only information in the datasheet regarding this divider is a note
in SYS_PLLPARAM register documentation which states that when LSCLK is
270 MHz, LSCLK_DIV should be 1. What should LSCLK_DIV be set to when
LSCLK is 162 MHz (for DP 1.62G mode) is unclear, but empirical test
confirms using LSCLK_DIV 1 has no adverse effects either. In the worst
case, the internal TC358767 clock would run faster.
Reviewed-by: Alexander Stein <alexander.stein@ew.tq-group.com>
Signed-off-by: Marek Vasut <marex@denx.de>
Signed-off-by: Robert Foss <rfoss@kernel.org>
Link: https://patchwork.freedesktop.org/patch/msgid/20240625120334.145320-4-marex@denx.de
Diffstat (limited to 'tools/perf/scripts/python')
0 files changed, 0 insertions, 0 deletions