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| author | Rajneesh Bhardwaj <rajneesh.bhardwaj@intel.com> | 2016-10-07 13:31:12 +0300 |
|---|---|---|
| committer | Darren Hart <dvhart@linux.intel.com> | 2016-12-13 20:28:54 +0300 |
| commit | 8434709ba71473f75572245c247d3c1e92509cf3 (patch) | |
| tree | c3b7e8a3f3fbecf9a9d4f028647c76b91c46d091 /tools/perf/scripts/python | |
| parent | 5241b1938a4d33eee3d3b43f23067c8e5b96db45 (diff) | |
| download | linux-8434709ba71473f75572245c247d3c1e92509cf3.tar.xz | |
platform/x86: intel_pmc_core: Fix PWRMBASE mask and mmio reg len
On Sunrise Point PCH, the Power Management Controller provides 4K bytes of
memory space for various power management and debug registers. This fix is
needed to access power management & debug registers that are mapped at a
higher offset.
Also, this provides a fix for correctly masking the PWRMBASE as the initial
bits (0-11) are reserved.
Signed-off-by: Rajneesh Bhardwaj <rajneesh.bhardwaj@intel.com>
Signed-off-by: Darren Hart <dvhart@linux.intel.com>
Diffstat (limited to 'tools/perf/scripts/python')
0 files changed, 0 insertions, 0 deletions