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| author | Duy Nguyen <duy.nguyen.rh@renesas.com> | 2024-01-25 18:34:30 +0300 |
|---|---|---|
| committer | Geert Uytterhoeven <geert+renesas@glider.be> | 2024-01-31 13:04:14 +0300 |
| commit | 3bbdf8c3d32103e21d9a826e40340fa59fc579ea (patch) | |
| tree | 40200a44505fe69668da30ab90aa740a8b07547d /tools/perf/scripts/python | |
| parent | 2a8998479328a6eb6a2b07a68c7a756fe717b9e2 (diff) | |
| download | linux-3bbdf8c3d32103e21d9a826e40340fa59fc579ea.tar.xz | |
dt-bindings: clock: Add R8A779H0 V4M CPG Core Clock Definitions
Add all Clock Pulse Generator Core Clock Outputs for the Renesas R-Car
V4M (R8A779H0) SoC.
Signed-off-by: Duy Nguyen <duy.nguyen.rh@renesas.com>
Signed-off-by: Hai Pham <hai.pham.ud@renesas.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/11acbd2a30b58607474e9c32eb798b3a00e85e73.1706194617.git.geert+renesas@glider.be
Diffstat (limited to 'tools/perf/scripts/python')
0 files changed, 0 insertions, 0 deletions