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| author | Olof Johansson <olof@lixom.net> | 2019-11-04 04:27:39 +0300 |
|---|---|---|
| committer | Olof Johansson <olof@lixom.net> | 2019-11-04 04:27:40 +0300 |
| commit | 2687aa23f5d577ddc40bb575b12b19aab656b405 (patch) | |
| tree | 2d6e5d4f5bde1a5634537461612ce9a24794e33e /tools/perf/scripts/python | |
| parent | c267d9960cc5f447ddc8863ed13af5b7d12d2f06 (diff) | |
| parent | 4053aa65c517fba954af05e826bb97b2eaefe92a (diff) | |
| download | linux-2687aa23f5d577ddc40bb575b12b19aab656b405.tar.xz | |
Merge tag 'tegra-for-5.5-arm-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into arm/dt
ARM: tegra: Device tree changes for v5.5-rc1
Adds support for CPU frequency scaling on Tegra20 and Tegra30, EMC
frequency scaling on Tegra30, SMMU support for VDE on Tegra30, the
STMPE ADC found on Toradex T30 modules as well as fixes for eDP
support on Venice2.
* tag 'tegra-for-5.5-arm-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux:
ARM: tegra: cardhu-a04: Add CPU Operating Performance Points
ARM: tegra: cardhu-a04: Set up voltage regulators for DVFS
ARM: tegra: trimslice: Add CPU Operating Performance Points
ARM: tegra: paz00: Add CPU Operating Performance Points
ARM: tegra: paz00: Set up voltage regulators for DVFS
ARM: tegra: Add CPU Operating Performance Points for Tegra30
ARM: tegra: Add CPU Operating Performance Points for Tegra20
ARM: tegra: Add Tegra30 CPU clock
ARM: tegra: Add Tegra20 CPU clock
ARM: tegra: Add External Memory Controller node on Tegra30
ARM: tegra: nyan-big: Add timings for RAM codes 4 and 6
ARM: tegra: Connect SMMU with Video Decoder Engine on Tegra30
ARM: tegra: Add eDP power supplies on Venice2
ARM: tegra: Add SOR0_OUT clock on Tegra124
ARM: tegra: Add stmpe-adc DT node to Toradex T30 modules
Link: https://lore.kernel.org/r/20191102144521.3863321-6-thierry.reding@gmail.com
Signed-off-by: Olof Johansson <olof@lixom.net>
Diffstat (limited to 'tools/perf/scripts/python')
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