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| author | Mika Kuoppala <mika.kuoppala@linux.intel.com> | 2012-10-29 18:59:26 +0400 |
|---|---|---|
| committer | Daniel Vetter <daniel.vetter@ffwll.ch> | 2012-11-12 02:51:09 +0400 |
| commit | 17f10fdc010254b8e9c0f1779abdaaee4757cabf (patch) | |
| tree | dc514c52a0091c6212afd2a9d188e45f706c733c /tools/perf/scripts/python | |
| parent | 00c09d70df6b30c980f20facc1db3def3f5a637e (diff) | |
| download | linux-17f10fdc010254b8e9c0f1779abdaaee4757cabf.tar.xz | |
drm/i915/ringbuffer: exclude last 2 cachelines on 845g on all callpaths
Make intel_render_ring_init_dri and intel_init_ring_buffer symmetrical
with regards of workaround introduced by:
commit 27c1cbd06a7620b354cbb363834f3bb8df4f410d
Author: Chris Wilson <chris@chris-wilson.co.uk>
Date: Mon Apr 9 13:59:46 2012 +0100
drm/i915/ringbuffer: Exclude last 2 cachlines of ring on 845g
Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'tools/perf/scripts/python')
0 files changed, 0 insertions, 0 deletions