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| author | Siddharth Vadapalli <s-vadapalli@ti.com> | 2023-03-15 09:23:04 +0300 |
|---|---|---|
| committer | Nishanth Menon <nm@ti.com> | 2023-03-20 20:46:23 +0300 |
| commit | a2ff7f1108f6eeaa73a60378ed891b634a3bba61 (patch) | |
| tree | 9e9bda821f037687079fdb472ebfdb7c7bd63de2 /tools/perf/scripts/python/task-analyzer.py | |
| parent | 6cd4b7cfbcca4a45f06a8031f299c4019221a4ce (diff) | |
| download | linux-a2ff7f1108f6eeaa73a60378ed891b634a3bba61.tar.xz | |
arm64: dts: ti: k3-j721e: Add CPSW9G nodes
TI's J721E SoC has a 9 port Ethernet Switch instance with 8 external
ports and 1 host port, referred to as CPSW9G.
Add device-tree nodes for CPSW9G and disable it by default. Device-tree
overlays will be used to enable it.
Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
Reviewed-by: Andrew Davis <afd@ti.com>
Link: https://lore.kernel.org/r/20230315062307.1612220-2-s-vadapalli@ti.com
Signed-off-by: Nishanth Menon <nm@ti.com>
Diffstat (limited to 'tools/perf/scripts/python/task-analyzer.py')
0 files changed, 0 insertions, 0 deletions