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| author | Bibek Kumar Patro <quic_bibekkum@quicinc.com> | 2024-12-12 18:14:01 +0300 |
|---|---|---|
| committer | Will Deacon <will@kernel.org> | 2025-01-07 16:55:28 +0300 |
| commit | 9fe18d825a5854f1ed6d6f91b45190d3a20f9f23 (patch) | |
| tree | 2865b95eef07a8d3984ac26c1c7acf9b00c7e9bc /tools/perf/scripts/python/task-analyzer.py | |
| parent | 7f2ef1bfc758f0f206eac863ff8ee417d5bb1493 (diff) | |
| download | linux-9fe18d825a5854f1ed6d6f91b45190d3a20f9f23.tar.xz | |
iommu/arm-smmu: Introduce ACTLR custom prefetcher settings
Currently in Qualcomm SoCs the default prefetch is set to 1 which allows
the TLB to fetch just the next page table. MMU-500 features ACTLR
register which is implementation defined and is used for Qualcomm SoCs
to have a custom prefetch setting enabling TLB to prefetch the next set
of page tables accordingly allowing for faster translations.
ACTLR value is unique for each SMR (Stream matching register) and stored
in a pre-populated table. This value is set to the register during
context bank initialisation.
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Bibek Kumar Patro <quic_bibekkum@quicinc.com>
Link: https://lore.kernel.org/r/20241212151402.159102-5-quic_bibekkum@quicinc.com
Signed-off-by: Will Deacon <will@kernel.org>
Diffstat (limited to 'tools/perf/scripts/python/task-analyzer.py')
0 files changed, 0 insertions, 0 deletions