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| author | José Roberto de Souza <jose.souza@intel.com> | 2024-12-27 21:32:19 +0300 |
|---|---|---|
| committer | José Roberto de Souza <jose.souza@intel.com> | 2025-01-02 16:35:16 +0300 |
| commit | 88fca61ba5e2ecd0552b9dea2500a16da12d0106 (patch) | |
| tree | 017082436264998ac7f99e1a59b7af9799210307 /tools/perf/scripts/python/task-analyzer.py | |
| parent | fba0f039affdd0c8767f24e41d5dbef49addea78 (diff) | |
| download | linux-88fca61ba5e2ecd0552b9dea2500a16da12d0106.tar.xz | |
Revert "drm/xe: Force write completion of MI_STORE_DATA_IMM"
This reverts commit 1460bb1fef9ccf7390af0d74a15252442fd6effd.
In all places the MI_STORE_DATA_IMM are not followed by a read of
the same memory address in the same batch buffer and the posted writes
are flushed with PIPE_CONTROL or MI_FLUSH_DW in xe_ring_ops.c functions
so there is no need to set this register.
Reviewed-by: Ashutosh Dixit <ashutosh.dixit@intel.com>
Cc: Thomas Hellström <thomas.hellstrom@linux.intel.com>
Cc: Ashutosh Dixit <ashutosh.dixit@intel.com>
Fixes: 1460bb1fef9c ("drm/xe: Force write completion of MI_STORE_DATA_IMM")
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20241227183230.101334-1-jose.souza@intel.com
Diffstat (limited to 'tools/perf/scripts/python/task-analyzer.py')
0 files changed, 0 insertions, 0 deletions