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| author | Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> | 2024-10-19 11:47:27 +0300 |
|---|---|---|
| committer | Geert Uytterhoeven <geert+renesas@glider.be> | 2024-10-25 11:54:21 +0300 |
| commit | 49991cca67d584a59cb10d48825cce3d11f7d843 (patch) | |
| tree | 33250834b911caf696f3c07b9e02c52a38a9c286 /tools/perf/scripts/python/task-analyzer.py | |
| parent | 9852d85ec9d492ebef56dc5f229416c925758edc (diff) | |
| download | linux-49991cca67d584a59cb10d48825cce3d11f7d843.tar.xz | |
dt-bindings: clock: r9a08g045-cpg: Add power domain ID for RTC
The RTC and VBATTB don't share the MSTOP control bit (but only the bus
clock and the reset signal). As the MSTOP control is modeled though power
domains add power domain ID for the RTC device available on the
Renesas RZ/G3S SoC.
Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20241019084738.3370489-2-claudiu.beznea.uj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Diffstat (limited to 'tools/perf/scripts/python/task-analyzer.py')
0 files changed, 0 insertions, 0 deletions