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| author | Anup Patel <apatel@ventanamicro.com> | 2024-10-20 22:47:33 +0300 |
|---|---|---|
| committer | Anup Patel <anup@brainfault.org> | 2024-10-28 14:14:05 +0300 |
| commit | 3e7d154ad89be46b41bb47a0a8a19ecf8e0ca3f3 (patch) | |
| tree | 258c42aec91c5e3bd0f3bd4fb62c6b404020375d /tools/perf/scripts/python/task-analyzer.py | |
| parent | 68c72a6557b072bff79658b9c0fdb0e69148e32d (diff) | |
| download | linux-3e7d154ad89be46b41bb47a0a8a19ecf8e0ca3f3.tar.xz | |
RISC-V: KVM: Save trap CSRs in kvm_riscv_vcpu_enter_exit()
Save trap CSRs in the kvm_riscv_vcpu_enter_exit() function instead of
the kvm_arch_vcpu_ioctl_run() function so that HTVAL and HTINST CSRs
are accessed in more optimized manner while running under some other
hypervisor.
Signed-off-by: Anup Patel <apatel@ventanamicro.com>
Reviewed-by: Atish Patra <atishp@rivosinc.com>
Link: https://lore.kernel.org/r/20241020194734.58686-13-apatel@ventanamicro.com
Signed-off-by: Anup Patel <anup@brainfault.org>
Diffstat (limited to 'tools/perf/scripts/python/task-analyzer.py')
0 files changed, 0 insertions, 0 deletions