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| author | Dan Williams <dan.j.williams@intel.com> | 2023-01-26 02:32:57 +0300 |
|---|---|---|
| committer | Dan Williams <dan.j.williams@intel.com> | 2023-01-26 02:32:57 +0300 |
| commit | 172738bbccdb4ef76bdd72fc72a315c741c39161 (patch) | |
| tree | 2fafe17a1eff9ec82a67067c819b6599e7294a37 /tools/perf/scripts/python/task-analyzer.py | |
| parent | af3ea9ab61d728d5a8be01bbec6d5cf7551b9600 (diff) | |
| download | linux-172738bbccdb4ef76bdd72fc72a315c741c39161.tar.xz | |
cxl/port: Link the 'parent_dport' in portX/ and endpointX/ sysfs
Similar to the justification in:
1b58b4cac6fc ("cxl/port: Record parent dport when adding ports")
...userspace wants to know the routing information for ports for
calculating the memdev order for region creation among other things.
Cache the information the kernel discovers at enumeration time in a
'parent_dport' attribute to save userspace the time of trawling sysfs
to recover the same information.
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Link: https://lore.kernel.org/r/167124082375.1626103.6047000000121298560.stgit@dwillia2-xfh.jf.intel.com
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Diffstat (limited to 'tools/perf/scripts/python/task-analyzer.py')
0 files changed, 0 insertions, 0 deletions