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| author | Nikunj A Dadhania <nikunj@amd.com> | 2025-01-06 15:46:26 +0300 |
|---|---|---|
| committer | Borislav Petkov (AMD) <bp@alien8.de> | 2025-01-07 23:26:06 +0300 |
| commit | 0f0502b8865c0a4c402e73aeb0fb406acc19d0d2 (patch) | |
| tree | ac2403a7ae384732a6c2604301c4f0952462f13b /tools/perf/scripts/python/task-analyzer.py | |
| parent | 85b60ca9ad2c94661acf86a0c11278246cc5ea86 (diff) | |
| download | linux-0f0502b8865c0a4c402e73aeb0fb406acc19d0d2.tar.xz | |
x86/sev: Change TSC MSR behavior for Secure TSC enabled guests
Secure TSC enabled guests should not write to the MSR_IA32_TSC (0x10) register
as the subsequent TSC value reads are undefined. On AMD, MSR_IA32_TSC is
intercepted by the hypervisor by default. MSR_IA32_TSC read/write accesses
should not exit to the hypervisor for such guests.
Accesses to MSR_IA32_TSC need special handling in the #VC handler for the
guests with Secure TSC enabled. Writes to MSR_IA32_TSC should be ignored and
flagged once with a warning, and reads of MSR_IA32_TSC should return the
result of the RDTSC instruction.
[ bp: Massage commit message. ]
Suggested-by: Borislav Petkov (AMD) <bp@alien8.de>
Signed-off-by: Nikunj A Dadhania <nikunj@amd.com>
Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de>
Reviewed-by: Tom Lendacky <thomas.lendacky@amd.com>
Link: https://lore.kernel.org/r/20250106124633.1418972-7-nikunj@amd.com
Diffstat (limited to 'tools/perf/scripts/python/task-analyzer.py')
0 files changed, 0 insertions, 0 deletions