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authorThéo Lebrun <theo.lebrun@bootlin.com>2024-11-06 19:03:58 +0300
committerStephen Boyd <sboyd@kernel.org>2024-11-15 01:52:27 +0300
commit0b28f9ee4b993621258615b591f0175c30340b06 (patch)
tree1b3d7fe04e3555e93524c46ac4c267d846eb2f2c /tools/perf/scripts/python/task-analyzer.py
parent5e01124a2c0a42dc6b587b0b09b204a5389f8d7b (diff)
downloadlinux-0b28f9ee4b993621258615b591f0175c30340b06.tar.xz
clk: eyeq: add EyeQ6H central fixed factor clocks
Previous setup was: - pll-cpu clock registered from driver at of_clk_init(); - occ-cpu clock registered from DT using fixed-factor-clock compatible. Now that drivers/clk/clk-eyeq.c supports registering fixed factors, use that capability to register occ-cpu. Also switch from hard-coded index 0 for pll-cpu to using the EQ6HC_CENTRAL_PLL_CPU constant by exposed dt-bindings headers. occ-cpu is exposed at of_clk_init() because it gets used by both the DT CPU nodes and the GIC timer. Signed-off-by: Théo Lebrun <theo.lebrun@bootlin.com> Link: https://lore.kernel.org/r/20241106-mbly-clk-v2-7-84cfefb3f485@bootlin.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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