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authorMarek BehĂșn <kabel@kernel.org>2024-08-07 19:41:03 +0300
committerThomas Gleixner <tglx@linutronix.de>2024-08-08 18:15:01 +0300
commitd6ca3f440239fb4fa85228ead4c5e8b286645b7e (patch)
tree3400e6d63b23f18fdb07d531ad5c81a9b679b4ab /tools/perf/scripts/python/syscall-counts.py
parent4042a965a5e62c8d298d642cbf72b14f41687319 (diff)
downloadlinux-d6ca3f440239fb4fa85228ead4c5e8b286645b7e.tar.xz
irqchip/armada-370-xp: Allow mapping only per-CPU interrupts
On platforms where MPIC is not the top-level interrupt controller the driver currently only supports handling of the per-CPU interrupts (the first 29 interrupts). This is obvious from the code of mpic_handle_cascade_irq(), which reads only one cause register. Bound the number of available interrupts in the interrupt domain to 29 for these platforms. The corresponding device-trees refer only to per-CPU interrupts via MPIC, the other interrupts are referred to via GIC. Signed-off-by: Marek BehĂșn <kabel@kernel.org> Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
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